JP3340782B2 - Thin-film semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor device,
In particular, the present invention relates to a structure of a thin film semiconductor element used for an active matrix type liquid crystal display device or the like.

[0002]

2. Description of the Related Art In recent years, thin-film semiconductor elements (hereinafter abbreviated as TFTs) have been widely used as elements of active matrix type liquid crystal display devices and image sensors. Improvement in semiconductor characteristics is desired.

The configuration of a conventional TFT will be described with reference to FIG. 2 taking an inverted stagger type TFT as an example. FIG. 2 (a)
2A is a plan view, FIG. 2B is a sectional view taken along line II-II of FIG. 2A, and FIG. 2C is a sectional view taken along line IV-IV of FIG. A gate electrode layer 3 is formed on an insulating substrate 7 made of glass or the like, and a gate insulating layer 4, a semiconductor layer 5, and a channel protective layer 1 are sequentially formed. After forming the channel protective layer 1 so as to obtain a predetermined channel length, the contact layer 6,
A source 2 and a drain 2 are formed. In this state, the source and the drain are short-circuited by the contact layer 6. Therefore, the contact layer 6 on the channel protection layer 1 is removed using the source 2 and the drain 2 as a mask. Where source 2
And the width of the drain 2 is formed wider than the width of the channel protective layer. That is, if the width of the source or the drain is W ₁ and the width of the channel protective layer is W ₀ , W ₀ > W ₁ . This is because it is necessary to reduce the resistance between the source and the drain by increasing the width of the channel layer. In addition, in order to ensure protection of the channel layer, it is necessary to increase the width of the channel protection layer to facilitate alignment.

The problem of such a TFT will be described with reference to an example in which the TFT is used for an active matrix type liquid crystal display device. The TFT functions as a switching element for selectively writing electric charge to each pixel formed in a matrix. For this reason, it is necessary to be able to sufficiently write the electric charge in the ON state, and to have a performance of holding the electric charge written in the pixel for a necessary time in the OFF state. Therefore, it is important that the on / off ratio is sufficiently ensured to perform the switching function. In principle, a TFT used in a liquid crystal display device using transmitted light cannot avoid receiving light irradiation. Therefore, TF using amorphous silicon or polycrystalline silicon
In T, a carrier excited by light is generated, and a leak current is liable to occur particularly in an off state. It is an essential technology for a TFT to reduce the value of the drain leak current generated in the off state and sufficiently secure the on / off ratio. If the on / off ratio cannot be kept large, for example, when a normally white liquid crystal material is used, the pixel becomes white and is recognized as a defect of the display device. When the device is used under a condition where light is irradiated due to its structure or use environment, such as for a liquid crystal display device, a display defect based on a decrease in the on / off ratio of the TFT is likely to occur.

As a measure for lowering the drain leak current value and ensuring a sufficient ON / OFF ratio, provision of a black matrix or a shielding film has been considered in order to avoid light irradiation to the TFT. Further, a method of increasing the auxiliary capacitance of the pixel electrode so that the leakage current of the TFT can be ignored has been considered. Further, a method of using a source and a drain as a shielding layer to prevent light irradiation on a semiconductor layer has been proposed (US Pat. No. 5,051,800).

[0006]

However, when a black matrix usually formed on the counter electrode side is provided, there is a gap of several μm between the black matrix and the TFT, and the liquid crystal composition is sandwiched between them. Because
Light from the backlight and the use environment is irradiated to the TFT due to irregular reflection in the liquid crystal device. Although there is a method of increasing the area of the black matrix, the aperture ratio of the liquid crystal display device is reduced, and the image quality is deteriorated. Also, TF
The method of disposing the light shielding film directly on T has problems that the potential of the shielding film affects the operation of the TFT, making it difficult to determine the potential, and the possibility of short-circuit between layers. In addition, the number of manufacturing steps increases, and the process becomes complicated. Therefore, there is a problem that the production yield of the device using the TFT is lowered.

A method for increasing the auxiliary capacitance of the pixel electrode is as follows.
There are problems such as a decrease in the aperture ratio of the liquid crystal display device and a need for a TFT having a high mobility capable of writing electric charge to a pixel due to the large auxiliary capacitance.

A method for avoiding light irradiation on the semiconductor layer by using the source and the drain as a shielding layer is that the semiconductor layer and the source and the drain have a contact portion via the contact layer at the tip of the shielding layer in the channel region. There is a problem that it cannot be lowered sufficiently.

As described above, the conventional technique has a problem that it is difficult to efficiently reduce the leak current of the TFT.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has been made without complicating the manufacturing process, and is not limited to a TFT.
TF which can reduce the leakage current of the TFT due to light irradiation without deteriorating the performance of the device using
It is intended to provide T.

[0011]

Means for Solving the Problems The TFT of the present invention comprises a substrate, a gate electrode layer provided on the substrate, and a semiconductor layer provided on the gate electrode layer via an insulating layer. A TFT comprising: a channel region; a channel protection layer provided on the channel region; and a source and a drain electrically connected through the channel region. Having an overlapping region on the layer, the source and the drain
Region where at least one of the end faces in the width direction of the inboard overlaps with each other
Outside and both in the width direction of the semiconductor layer.
The end faces are both end faces in the width direction of the channel protective layer.
It is characterized by overlapping each other. The width direction is semi-conductive.
The channel width direction, which is the direction along the channel width of the body layer,
means.

The TFT of the present invention will be described with reference to FIG.
FIG. 1A is a plan view, and FIG.
1 (c) is a sectional view taken along line II-II of FIG. 1 (a), and FIG. 1 (d) is a sectional view taken along line IV-IV of FIG. 1 (a). On a transparent substrate 7, a gate electrode layer 3, a gate insulating layer 4, a semiconductor layer 5, and a channel protective layer 1 are provided.
Further, the source and the drain 2 electrically connected to the semiconductor layer 5 via the contact layer 6 are provided thereon. The source and the drain 2 have a region overlapping the channel protection layer 1. Ji further channel protective layer
There are few end faces that define the channel width (hereinafter, referred to as width faces).
At least, the source and the drain overlap so that the width faces of the source and the drain are outside. Therefore, they may overlap so as to cover only one width surface of the channel protection layer, or may overlap so as to cover both width surfaces. The electrode width W ₁ of the source and the drain 2 is larger than the width W ₀ of the channel protective layer 1,
In addition, it is more preferable that the TFTs overlap each other so as to cover both width faces, because the leak current of the TFT can be reduced.
When overlapping so as to cover only one width surface, TF
The parasitic capacitance of T can be reduced.

As shown in FIG. 1, having an overlap intersection with the semiconductor layer at the overlap intersection between the source and drain and the channel protection layer means that the source and drain 2 have overlap at the overlap intersection III between the source and drain 2 and the channel protection layer 1. Are in direct contact with the semiconductor layer 5 and not through the contact layer 6 (FIGS. 1C and 1D). With such a structure, the leak current can be significantly reduced. Here, the source and the drain 2 may be made of a low-resistance semiconductor layer or a metal, or may be a stack of these.

[0014]

FIG. 3 (a), FIG. 3 (b), FIG. 3 (c) show that the structure of the present invention greatly reduces the leakage current.
This will be described below. FIGS. 3A and 3B show conventional TFs.
FIG. 3C shows the planar structure of the TFT according to the present invention. FIG. 3B shows that the semiconductor layer 5 is removed by etching except for the channel region.
And different.

The present invention has been made as a result of paying attention to the fact that the presence or absence of a leakage current path caused by light irradiation greatly affects a leakage current value. Therefore, the TFT of the present invention has a structure in which a leakage current path generated by light irradiation is blocked.

In a liquid crystal display device, an image sensor, or the like,
Amorphous silicon is often used as a semiconductor layer that can be deposited over a large area at low cost. Amorphous silicon becomes electrically conductive when irradiated with light due to its properties. For this reason, if a leak current path exists between the source and the drain, the leak current flows to a channel region which should be controlled by the gate potential. For example, FIG.
In the case of the TFT having the structure described above, the leakage current paths generated by light irradiation are A → B, A ′ → B ′ and C → D, C ′ → D ′
It is. In the case of FIG. 3B, the leakage current path is A →
B, A ′ → B ′. Leak current paths are A → B, A ′
→ In B ′, points A (or A ′) and points B (or B ′) are points where the contact layer 6 is in contact with a region (hatched region) having high electrical conductivity by light irradiation. For this reason, if there is a potential difference between the source and the drain, a leak current flows. Further FIG.
In the case of (a), if the semiconductor layer 5 remains in a region other than the channel region as seen in the leakage current path C → D, the semiconductor layer and the contact region are in contact with each other by a line like AC or BF. Is even larger than in the case of FIG. FIG. 3C showing the planar structure of the TFT of the present invention.
In, the region indicated by the hatched portion becomes highly conductive by light irradiation, but there is no place where this region is in contact with the contact layer. Therefore, with the structure of the present invention, the leakage current path can be cut off.

[0017]

Embodiment 1 Hereinafter, a TFT according to the present invention will be specifically described with reference to FIG. The gate electrode layer 3 is formed on the substrate 7. For example, when a TFT is used for a liquid crystal display device, glass,
A transparent substrate such as quartz is used as the material of the substrate 7. For the gate electrode layer 3, a single layer of molybdenum (Mo), tantalum (Ta), aluminum (Al) or a laminated film of these metals is used as a material, and is formed into a desired shape by plasma etching or wet etching. It is formed.

Next, a gate insulating layer 4, a semiconductor layer 5, and a channel protective layer 1 are sequentially deposited. Specifically, the following examples can be given. A material such as a silicon nitride film (SiN _x ), a silicon oxide film (SiO _x ) or a laminated film of a silicon nitride film and a silicon oxide film is used as the gate insulating layer 4, and a plasma CVD method or the like is used as a deposition method. I do.
The semiconductor layer 5 is made of amorphous silicon or the like, and the channel protective layer 1 is made of a material such as a silicon nitride film or a silicon oxide film. After the laminated film is deposited, the channel protection layer 1 is formed so as to obtain a desired channel length. Next, as the contact layer 6, an n + contact layer doped with an impurity such as phosphorus (P) is deposited.
Thereafter, the semiconductor layer 5 and the contact layer 6 are separated for element isolation.
Is patterned. At the time of this patterning, the channel width of the TFT is determined. Therefore, when forming the channel protection layer 1 in consideration of relaxing the patterning alignment accuracy, it is preferable to form the channel protection layer 1 larger than the actual channel width. Since the channel protection layer 1 is formed to be larger than a desired channel width, the channel protection layer 1 is simultaneously etched in an element isolation etching step. Such etching can be easily realized by using an etching method having no selectivity between the channel protective layer 1 and the semiconductor layer 5. For example, when a silicon nitride film is used for the channel protective layer 1 and amorphous silicon is used for the semiconductor layer 5, perfluoromethane (CF ₄ ) and oxygen (
A dry etching method using an O ₂ ) -based mixed gas is preferred.

Next, a source 2 and a drain 2 are formed. As the electrode material, for example, molybdenum (Mo), chromium (Cr), aluminum (Al), or a laminated film of these can be used. When this electrode layer is formed, the width of the source 2 and the drain 2 in the channel width direction of the channel protective layer 1 is formed such that W ₀ <W ₁ as shown in FIG. Thereafter, the contact layer 6 is etched using the source 2 and the drain 2 as a mask.

The TF of the present embodiment thus formed
The T structure is different from the conventional TFT structure shown in FIG.
The feature is that the source 2 and the drain 2 are wider than the channel protective layer 1, the semiconductor layer 5, and the contact layer 6 in the channel width direction. That is, in the conventional example, W ₀ >
Whereas a W _1, this embodiment is W ₀ <W _1.
Therefore, there is no need to increase or complicate the TFT manufacturing process.

FIG. 4 shows the characteristics of the TFT of this embodiment in comparison with the conventional example. 4, I _d the TFT - shows the V _g characteristic, FIG. 4 (a) of this embodiment, FIG. 4 (b) shows a conventional example, respectively. Incidentally, I _d - V _g characteristic, respectively 70 lx light from the source and the drain side of the TFT, 250
1x, 750 lx irradiation and no light irradiation. For example, comparing current values at a gate voltage of 0 [V], it is found that the T
The FT has a clearly smaller leak current value. When such a TFT is used, a liquid crystal display device having excellent display quality can be obtained.

FIG. 5 can be considered as a special example of the TFT structure of this embodiment. 5A is a plan view, and FIG. 5B is a cross-sectional view taken along the line II of FIG. 5A. In FIG. 5, W ₀ = W ₁ . Therefore, the contact layer 6 and the semiconductor layer 5 are exposed in the cross section. For this reason, when the contact layer between the source 2 and the drain 2 is etched, the contact layer 6 and the semiconductor layer 5 are etched from the ends, thereby deteriorating the source / drain contact portions of the TFT, and failing to obtain good TFT characteristics. From the above, W ₀ = W ₁ is not desirable, and W ₀
<It is important that the W _1.

Embodiment 2 An embodiment capable of simplifying the manufacturing process will be described. A gate electrode layer is formed on a transparent insulating substrate, and a gate insulating layer, a semiconductor layer, and a channel protective layer are sequentially deposited.
In the step of patterning the channel protective layer, after applying a resist, the channel protective layer is formed in a self-aligned manner by a backside exposure method in which exposure is performed from the substrate side using the gate electrode layer as a mask. By using this method, the overlapping region between the gate electrode layer pattern and the source / drain pattern can be accurately controlled. Further, a reticle for patterning the channel protective layer is not required, and the manufacturing cost can be reduced. As for the channel width, a desired channel width can be determined using a mask for element isolation as shown in the first embodiment, so that there is no need to change the process as in the first embodiment. Subsequent manufacturing steps are the same as in the first embodiment.

According to the second embodiment, by adopting a self-aligned manufacturing process, the manufacturing process can be simplified and the manufacturing cost can be reduced.

[0025]

According to the TFT of the present invention, since the source and the drain are formed on the channel protective layer, the source and the drain are wider than the widths of the channel protective layer, the semiconductor layer and the contact layer.

Also, by adopting such a structure,
A TFT can be manufactured without increasing the number of conventional manufacturing steps or complicating the manufacturing steps.

Further, when the TFT of the present invention is used in a liquid crystal display device, a liquid crystal display device having excellent display quality can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a TFT of the present invention. FIG.
1 (a) is a plan view, FIG. 1 (b) is a sectional view taken along the line II of FIG. 1 (a), FIG. 1 (c) is a sectional view taken along the line II-II of FIG. ) Shows a cross-sectional view taken along line IV-IV of FIG.

FIG. 2 is a diagram showing a conventional TFT. Note that FIG.
2A is a plan view, FIG. 2B is a II-II cross-sectional view of FIG. 2A, and FIG. 2C is a IV-IV cross-sectional view of FIG. 2A.

FIG. 3 is a diagram illustrating a leakage current path. 3A and 3B show the planar structure of a conventional TFT, and FIG. 3C shows the planar structure of the TFT of the present invention.

It is a diagram showing a V _g characteristic - [4] I _d of the TFT. FIG. 4A shows the first embodiment, and FIG. 4B shows a conventional example.

FIG. 5 is a diagram showing a special example of a TFT structure according to the first embodiment. FIG. 5A is a plan view, and FIG.
(A) is a sectional view taken along line II.

[Explanation of symbols]

1 channel protection layer, 2 source and drain, 3 gate electrode layer, 4 gate insulating layer, 5
... Semiconductor layer, 6 Contact layer, 7 Substrate.

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kaichi Fukuda 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside the Toshiba Yokohama Office (72) Inventor Nobuki Ibaraki 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Co., Ltd. Toshiba Yokohama Office (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 29/786 H01L 21/336

Claims (1)

(57) [Claims] A channel region comprising a substrate, a gate electrode layer disposed on the substrate, a semiconductor layer disposed on the gate electrode layer via an insulating layer, and a channel region disposed on the channel region. A thin film semiconductor element comprising: a provided channel protection layer; and a source and a drain electrically connected through the channel region, wherein the source and the drain each have a region overlapping the channel protection layer. , Of said source and drain
At least one of the end faces in the width direction is larger than the overlapping area.
Both end faces on the outside and in the width direction of the semiconductor layer
Are both end faces in the width direction of the channel protective layer.
A thin film semiconductor device characterized by overlapping .