JPH0519831B2 - - Google Patents
Info
- Publication number
- JPH0519831B2 JPH0519831B2 JP10992883A JP10992883A JPH0519831B2 JP H0519831 B2 JPH0519831 B2 JP H0519831B2 JP 10992883 A JP10992883 A JP 10992883A JP 10992883 A JP10992883 A JP 10992883A JP H0519831 B2 JPH0519831 B2 JP H0519831B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- region
- insulating film
- main electrode
- tft
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010408 film Substances 0.000 claims description 47
- 239000010409 thin film Substances 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 7
- 239000011810 insulating material Substances 0.000 claims description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 239000011521 glass Substances 0.000 description 6
- 238000000137 annealing Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052749 magnesium Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- 239000012780 transparent material Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000007737 ion beam deposition Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
Description
【発明の詳細な説明】
＜産業上の利用分野＞
本発明は、非晶質や多結晶またはそれらをビー
ムアニールして結晶化した半導体薄膜を用うた薄
膜トランジスタ（TFT）に関するものである。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a thin film transistor (TFT) using a semiconductor thin film that is amorphous, polycrystalline, or crystallized by beam annealing.
＜従来技術＞
非晶質シリコン（ａ−Si）薄膜を例にとれば、
従来のTFTは、主に第１図ａまたは第１図ｂに
示す断面構造を有していた。第１図ａの例では、
絶縁体を表面に有する基板（例えばガラス、石
英、セラミツクス、SiO2でカバーされたSiや金
属）１の上にゲート金属４、ゲート絶縁膜６があ
り、その上に高抵抗ａ−Si領域５が形成されてい
る。ａ−Si領域５の両端にはソース電極３、ドレ
イン電極２などの主電極が配されている。表面保
護のため酸化膜等の絶縁膜７がａ−Si領域５上に
設けられることもある。ゲート電極４、ドレイン
やソース主電極２，３は、Al、Mg、Pt、Mo等
の金属やそのシリサイドで形成されたり、不純物
を添加したａ−Siで形成されることがある。第１
図ｂの例では、ゲート電極４が最上表面に設けら
れた例で、ゲート絶縁膜６を介して高抵抗ａ−Si
領域５の上にある。ドレイン・ソース配線１２，
１３は金属や半導体薄膜から成るドレイン・ソー
ス主電極領域２，３を介して行なわれている。ド
レイン・ソース電極領域２，３は、この場合ａ−
Si領域の下に設けられることが多い。<Prior art> Taking an amorphous silicon (a-Si) thin film as an example,
Conventional TFTs mainly had the cross-sectional structure shown in FIG. 1a or 1b. In the example in Figure 1a,
A gate metal 4 and a gate insulating film 6 are disposed on a substrate 1 having an insulator on its surface (e.g. glass, quartz, ceramics, Si covered with SiO 2 or metal) 1, and a high resistance a-Si region 5 is disposed on the substrate 1. is formed. Main electrodes such as a source electrode 3 and a drain electrode 2 are arranged at both ends of the a-Si region 5. An insulating film 7 such as an oxide film may be provided on the a-Si region 5 for surface protection. The gate electrode 4 and the drain and source main electrodes 2 and 3 may be formed of a metal such as Al, Mg, Pt, or Mo or a silicide thereof, or may be formed of a-Si doped with impurities. 1st
In the example shown in FIG. b, the gate electrode 4 is provided on the uppermost surface, and a high-resistance a-Si
It is above area 5. drain/source wiring 12,
13 is carried out via drain/source main electrode regions 2 and 3 made of metal or semiconductor thin films. In this case, the drain/source electrode regions 2 and 3 are a-
It is often provided under the Si region.
上述の如く、従来のTFTは簡単な構造でしか
も基板１として安価なガラスを用いることができ
るので、安価な集積回路、大面積のTFTアレイ
（例えば液晶表示パネル）等に応用されつつある。 As mentioned above, conventional TFTs have a simple structure and can use inexpensive glass as the substrate 1, so they are being applied to inexpensive integrated circuits, large-area TFT arrays (for example, liquid crystal display panels), and the like.
しかし、一般的にａ−Siは光によつて導電率が
著しく変化するので例えば液晶表示パネルへの適
用に当つては、遮光膜の形成が必要であつた。ま
た、ａ−Siはキヤリア移動度が一般的に小さいの
で高速動作においては極めてチヤンネル長Ｌを短
かくする必要があるが、イオン注入等を利用する
セルフアライメント技術の適用が困難であつた。
第１図の例の如き構造のTFTでは微細加工技術
を必要とされ、逆に大面積化が困難となる。 However, since the conductivity of a-Si generally changes significantly depending on light, it is necessary to form a light-shielding film when applying it to, for example, a liquid crystal display panel. Further, since a-Si generally has a low carrier mobility, it is necessary to make the channel length L extremely short in high-speed operation, but it has been difficult to apply self-alignment technology using ion implantation or the like.
A TFT with a structure like the example shown in FIG. 1 requires microfabrication technology, and conversely, it is difficult to increase the area.
＜発明の目的＞
本発明は、叙上の従来のTFTの問題点に鑑み
てなされたものである。本発明の目的の主たるも
のは、チヤンネル長の短い構造の縦型TFTと同
時に作りやすく、かつ、チヤンネル長を容易に選
定できるTFTを提供することにある。<Object of the Invention> The present invention has been made in view of the above-mentioned problems of conventional TFTs. The main object of the present invention is to provide a TFT that can be easily manufactured at the same time as a vertical TFT with a short channel length structure and whose channel length can be easily selected.
併せて、基板に透明材料を用いても遮光が容易
に得られるTFT構造を提供することにある。本
発明におけるTFTはソース及びドレイン電極が
絶縁膜の上面及び底面にそれぞれ形成され、チヤ
ンネル領域が前記絶縁膜の表面及び側面に接し、
かつ両端が前記ソース及びドレイン電極に接して
設けられ、チヤンネル領域の表面にゲート絶縁膜
とゲート電極が形成された構造を有するものであ
る。 Another object of the present invention is to provide a TFT structure that can easily block light even if a transparent material is used for the substrate. In the TFT of the present invention, source and drain electrodes are formed on the top and bottom surfaces of the insulating film, respectively, a channel region is in contact with the top and side surfaces of the insulating film,
The device has a structure in which both ends are provided in contact with the source and drain electrodes, and a gate insulating film and a gate electrode are formed on the surface of the channel region.
以下に図面を用いて本発明について詳述する。 The present invention will be explained in detail below using the drawings.
＜発明の構成＞
第２図には、本発明によるTFTの一部拡大断
面図が示されている。少なくとも表面が絶縁物か
ら成る基板１（例えば、SiO2や窒化膜コートさ
れたSi基板やステンレス等の金属基板、ガラスや
石英基板、セラミツクス基板、プラスチツク基板
など）の表面に、第１主電極薄膜領域（例えばド
レイン）２、絶縁膜１７、第２主電極領域（例え
ばソース）３が順次堆積され、第１主電極領域２
の端部と絶縁膜１７のそれがほぼ一致している。<Structure of the Invention> FIG. 2 shows a partially enlarged sectional view of a TFT according to the invention. A first main electrode thin film is formed on the surface of a substrate 1 whose at least the surface is made of an insulating material (for example, a Si substrate coated with SiO 2 or a nitride film, a metal substrate such as stainless steel, a glass or quartz substrate, a ceramic substrate, a plastic substrate, etc.). A region (e.g. drain) 2, an insulating film 17, and a second main electrode region (e.g. source) 3 are deposited in sequence, and the first main electrode region 2
The end of the insulating film 17 almost coincides with that of the insulating film 17.
第２主電極領域３は、絶縁膜１７の端部より内
側に位置している。高抵抗半導体薄膜領域５は、
第１、第２主電極領域２，３にその両側を接し、
その上にはゲート絶縁膜６、ゲート電極４が形成
されている。このTFTは、チヤンネル長Ｌとし
て第２主電極領域３の端部と絶縁膜１７の端部間
の距離及び絶縁膜１７の厚みとの和できめられ
る。 The second main electrode region 3 is located inside the end of the insulating film 17. The high resistance semiconductor thin film region 5 is
contacting the first and second main electrode regions 2 and 3 on both sides,
A gate insulating film 6 and a gate electrode 4 are formed thereon. The channel length L of this TFT is determined by the sum of the distance between the end of the second main electrode region 3 and the end of the insulating film 17 and the thickness of the insulating film 17.
本TFTは、高抵抗領域５が表面側をゲート電
極４で、裏面側を第１主電極領域２で覆われてい
るので、これらを遮光材で構成すれば、たとえ透
明基板１を用いても特別に遮光膜を設ける必要が
ない。 In this TFT, the high resistance region 5 is covered with the gate electrode 4 on the front side and the first main electrode region 2 on the back side, so if these are made of a light shielding material, even if the transparent substrate 1 is used. There is no need to provide a special light shielding film.
第３図ａ及び第３図ｂには本発明の他の実施例
によるTFTの断面構造例が示されている。第３
図ｂのＢ−B′断面は、第３図ａのＡ−A′断面に
直交する図である。本例においては、例えばガラ
ス基板１上に第１主電極としてのソース電極薄膜
領域３が形成され、その上に絶縁膜１７が堆積さ
れている。絶縁膜１７の端部の一部は、ソース電
極領域３より内側に形成されている。また、絶縁
膜１７上には第２主電極領域としてのドレイン電
極薄膜領域２が設けられ、その一部は絶縁膜１７
の端部より内側になつている。ドレイン電極領域
２、絶縁膜１７、ソース電極領域３が段階状にな
つた部分に高抵抗半導体薄膜領域５が設けられ、
さらにその上にゲート絶縁膜６、ゲート電極４が
形成され、トランジスタ動作部分TRを形造つて
いる。ドレイン及びソース電極領域２，３の一部
は、この例ではＡ−A′方向に延在し、それぞれ
ドレイン・ソース配線１２，１３に結合してい
る。トランジスタ動作部分TRは、前記階段状に
なつた部分に設けられるので、チヤンネル幅Ｗは
長くとれる特徴を有し、ソース電極領域３の端部
位置を変更することによりチヤンネル長を任意に
変えることができる。また、ドレイン電極領域お
よびソース電極領域の材質を遮光材とするだけで
容易にチヤンネル領域（高抵抗領域５）を完全に
遮光することができる。この場合、透明電極１を
用いても特別に遮光膜を設けることは必要がな
い。 FIGS. 3a and 3b show examples of cross-sectional structures of TFTs according to other embodiments of the present invention. Third
The BB' cross-section in FIG. 3b is perpendicular to the A-A' cross-section in FIG. 3a. In this example, a source electrode thin film region 3 as a first main electrode is formed on, for example, a glass substrate 1, and an insulating film 17 is deposited thereon. A part of the end portion of the insulating film 17 is formed inside the source electrode region 3. Further, a drain electrode thin film region 2 as a second main electrode region is provided on the insulating film 17, and a part of the drain electrode thin film region 2 is provided on the insulating film 17.
It is located inward from the edge. A high resistance semiconductor thin film region 5 is provided in a portion where the drain electrode region 2, the insulating film 17, and the source electrode region 3 are stepped.
Furthermore, a gate insulating film 6 and a gate electrode 4 are formed thereon to form a transistor operating portion TR. Parts of the drain and source electrode regions 2 and 3 extend in the AA' direction in this example and are coupled to the drain and source wirings 12 and 13, respectively. Since the transistor operating portion TR is provided in the stepped portion, the channel width W can be made long, and the channel length can be arbitrarily changed by changing the end position of the source electrode region 3. can. Further, the channel region (high resistance region 5) can be easily completely shielded from light by simply using a light shielding material for the drain electrode region and the source electrode region. In this case, even if the transparent electrode 1 is used, there is no need to provide a special light shielding film.
第４図には、本発明の他の実施例が示されてい
る。この例においては、ドレイン電極領域２が基
板１に接して設けられているが、ドレイン電極領
域２とソース電極領域３の重畳が極力小さくさ
れ、両電極間の容量を小さくしている。本発明に
おけるように、この重畳部分がわずかでも存在す
れば、上記ドレイン電極領域２とソース電極領域
３を遮光材で構成することにより高抵抗領域５を
完全に遮光することができる。したがつて、この
場合、ガラス基板を用いても新たに遮光膜を設け
る必要はない。 Another embodiment of the invention is shown in FIG. In this example, the drain electrode region 2 is provided in contact with the substrate 1, but the overlap between the drain electrode region 2 and the source electrode region 3 is minimized to reduce the capacitance between the two electrodes. As in the present invention, if even a slight overlap exists, the high resistance region 5 can be completely shielded from light by forming the drain electrode region 2 and the source electrode region 3 with a light shielding material. Therefore, in this case, there is no need to newly provide a light shielding film even if a glass substrate is used.
第５図ａ〜ｅには、本発明によるTFTT１と
絶縁膜の厚みによつてチヤンネル長Ｌがきめられ
る短チヤンネル縦型TFTT２とを同時に形成す
るときの工程断面図が示されている。第５図ａに
は、例えばガラス基板１上に、それぞれＴ１及び
Ｔ２のドレイン電極領域２，１０２を設け、さら
に絶縁膜１７を堆積した断面を示す。ドレイン電
極領域２，１０２は、例えば不純物を添加したａ
−Si、Cr、Pt、Al、Mo、Ｗ、Mg等の金属やそ
の硅化物等が用いられる。絶縁膜１７は、酸化硅
素膜、窒化硅素膜、酸化アルミニウムなどの他
に、ポリイミド等の樹脂が用いられ、誘電率が小
さく、かつ破壊電圧が高い程望ましい。この例で
は、例えば酸化膜を約1μｍの厚みでプラズマ
CVD（P.CVD）や光CVD等低温で形成する。 FIGS. 5a to 5e are cross-sectional views showing the process of simultaneously forming the TFTT 1 according to the present invention and a short channel vertical TFTT 2 whose channel length L is determined by the thickness of the insulating film. FIG. 5a shows a cross section in which, for example, drain electrode regions 2 and 102 of T1 and T2 are provided on a glass substrate 1, respectively, and an insulating film 17 is further deposited. The drain electrode region 2, 102 is made of, for example, a doped a
-Metals such as Si, Cr, Pt, Al, Mo, W, Mg, and their silicides are used. In addition to a silicon oxide film, a silicon nitride film, and an aluminum oxide film, the insulating film 17 is made of a resin such as polyimide, and it is desirable that the dielectric constant be low and the breakdown voltage be high. In this example, for example, an oxide film with a thickness of approximately 1 μm is coated with plasma.
Formed at low temperatures such as CVD (P.CVD) and photoCVD.
第５図ｂには、ドレイン電極領域２，１０２と
同様な材料から成るソース電極領域３，１０３を
Ｔ１，Ｔ２のそれぞれに形成した断面を示す。少
なくともトランジスタ動作領域が形成されるべき
部分のソース電極領域３，１０３は、ドレイン電
極領域２，１０２より内側に設けられている。第
５図ｃでは、レジスト８をマスクにして絶縁膜１
７を選択エツチした断面を示す。TFTT１では
レジスト８はソース電極領域３よりも幅広く残さ
れ、ソース電極領域３と絶縁膜１７とが階段状断
面を有する。一方、TFTT２では、絶縁膜１７
のエツチのマスクの一部としてソース電極領域１
０３が用いられ、ソース電極領域１０３と同一端
部を有する絶縁膜１１７が残される。レジスト８
を除去した後、高抵抗半導体薄膜５，１０５を選
択的に堆積し、さらにゲート絶縁６，１０６を堆
積した断面を第５図ｄに示す。高抵抗半導体薄膜
５，１０５は例えばＨやＦを添加されたａ−Si
で、PCVD、光CVD、分子線蒸着、イオンビー
ム堆積法等で形成され、ゲート絶縁膜６，１０６
と同様であり、時として連続して堆積される。 FIG. 5b shows a cross section in which source electrode regions 3 and 103 made of the same material as the drain electrode regions 2 and 102 are formed in T1 and T2, respectively. At least the portion of the source electrode region 3, 103 where the transistor operation region is to be formed is provided inside the drain electrode region 2, 102. In FIG. 5c, the insulating film 1 is shown using the resist 8 as a mask.
7 is selectively etched. In TFTT 1, resist 8 is left wider than source electrode region 3, and source electrode region 3 and insulating film 17 have a stepped cross section. On the other hand, in TFTT2, the insulating film 17
source electrode region 1 as part of the etching mask.
03 is used, and an insulating film 117 having the same end as the source electrode region 103 is left. resist 8
After removing, high resistance semiconductor thin films 5, 105 are selectively deposited, and a gate insulator 6, 106 is further deposited, and a cross section is shown in FIG. 5d. The high resistance semiconductor thin film 5, 105 is, for example, a-Si doped with H or F.
The gate insulating film 6,106 is formed by PCVD, photoCVD, molecular beam evaporation, ion beam deposition, etc.
similar to, and sometimes deposited in succession.
ａ−Si膜５，１０５には必要に応じ不純物が添
加される。また、半導体薄膜５，１０５として多
結晶やビームアニール等で結晶化された薄膜も用
いられる。第５図ｅには、コンタクト開孔後、
TFTT１及びＴ２のそれぞれのドレイン金属配
線１２，１１２、ソース金属配線１３，１１３
（図示せず）、ゲート電極４，１０４を形成した完
成断面図を示す。以上の製造方法によつて、チヤ
ンネル長Ｌが絶縁膜１７，１１７の厚み程度の短
かいTFT Ｔ２と、チヤンネル長がさらに長く自
由に値を選択できる本発明によるTFT Ｔ１を同
時に製作できる。 Impurities are added to the a-Si films 5 and 105 as necessary. Further, as the semiconductor thin film 5, 105, a polycrystalline film or a thin film crystallized by beam annealing or the like may be used. Figure 5e shows that after contact hole opening,
Drain metal wiring 12, 112 and source metal wiring 13, 113 of TFTT1 and T2, respectively
(not shown) shows a completed cross-sectional view with gate electrodes 4 and 104 formed. By the above manufacturing method, it is possible to simultaneously manufacture the TFT T2 with a short channel length L of about the thickness of the insulating films 17, 117 and the TFT T1 according to the present invention with a longer channel length whose value can be freely selected.
＜発明の効果＞
以上のように、本発明によるTFTは、短チヤ
ンネル縦型TFTと混載可能であるので、例えば、
高速動作を必要とする回路部に短チヤンネル縦型
TFTを用い、低速動作でもよいが、低リーク電
流や高耐圧の必要な回路部には、本発明のTFT
を用いた構成の集積回路を容易に実現することが
できる。この際、本発明のTFTはチヤンネル長
を容易に選定できるので、設計が容易である。<Effects of the Invention> As described above, since the TFT according to the present invention can be mounted together with a short channel vertical TFT, for example,
Short channel vertical type for circuit parts that require high-speed operation
TFTs can be used for low-speed operation, but the TFTs of the present invention can be used in circuit parts that require low leakage current and high withstand voltage.
It is possible to easily realize an integrated circuit having a configuration using the following. In this case, since the channel length of the TFT of the present invention can be easily selected, the design is easy.
また、本発明によるTFTは、第１の主電極薄
膜領域および第２の主電極薄膜領域は高抵抗領域
を介して重畳して配置されているので、これらを
不透明材料により構成することにより、たとえ、
基板に透明材料を用いても、新たに、遮光膜を設
置する必要がないなど顕著な効果を奏するもので
ある。本発明によるTFTは、従来のTFTと同一
基板上に混載できる層数、マスクを有するので、
さらに設計の幅を広げることができる。 Further, in the TFT according to the present invention, since the first main electrode thin film region and the second main electrode thin film region are arranged to overlap with each other with a high resistance region interposed therebetween, by constructing these from an opaque material, it is possible to ,
Even if a transparent material is used for the substrate, there are significant effects such as no need to newly install a light-shielding film. The TFT according to the present invention has the number of layers and masks that can be mounted on the same substrate as conventional TFTs, so
Furthermore, the range of designs can be expanded.
主にａ−Siを用いる例を述べてきたが、同時に
多結晶Siにも適用されるし、レーザやランプ等に
よるビームアニール技術を用いて高抵抗半導体領
域５，１０５として結晶層ひいては単結晶層を用
いることができ、特性の向上が図れる。材料とし
ても、Siに限らずGaAs等他の半導体薄膜に適用
されることはいうまでもない。本発明による
TFTの他の利点を述べれば、占有面積あたりの
チヤンネル幅Ｗを大きくできるので、液晶表示パ
ネル等に使用した場合に開口率を大きくでき、例
えば周辺回路を縦型TFTT２で形成した場合に
も容易に製造できる。叙上の様に、本発明は
TFTの応用範囲を広げ、工業的に極めて重要で
ある。 Although we have mainly described an example using a-Si, it can also be applied to polycrystalline Si, and a crystal layer or even a single crystal layer can be formed as a high-resistance semiconductor region 5, 105 using beam annealing technology using a laser or a lamp. can be used, and the characteristics can be improved. Needless to say, the material is not limited to Si, but can be applied to other semiconductor thin films such as GaAs. According to the present invention
Another advantage of TFT is that the channel width W per occupied area can be increased, so the aperture ratio can be increased when used in liquid crystal display panels, etc., and it can also be easily used when peripheral circuits are formed using vertical TFTT2, for example. can be manufactured. As mentioned above, the present invention
It expands the range of applications of TFT and is extremely important industrially.
第１図ａ及び第１図ｂは従来のTFTの構造断
面図、第２図は本発明によるTFTの一部拡大構
造断面図、第３図ａ及び第３図ｂは本発明による
TFTの構造断面図で互いに直角方向の断面図、
第４図は本発明によるTFTの他の実施例を示す
断面図、第５図ａ乃至ｅは本発明によるTFTの
製造工程を説明するための断面図である。
１……基板、２，１０２……ドレイン主電極薄
膜領域、３，１０３……ソース主電極薄膜領域、
４，１０４……ゲート電極、５，１０５……高抵
抗半導体薄膜、６，１０６……ゲート絶縁膜、
７，１７，１１７……絶縁膜。
1a and 1b are structural cross-sectional views of a conventional TFT, FIG. 2 is a partially enlarged structural cross-sectional view of a TFT according to the present invention, and FIGS. 3a and 3b are structural cross-sectional views according to the present invention.
Structural cross-sectional view of TFT, cross-sectional view at right angles to each other,
FIG. 4 is a cross-sectional view showing another embodiment of the TFT according to the present invention, and FIGS. 5 a to 5 e are cross-sectional views for explaining the manufacturing process of the TFT according to the present invention. 1...Substrate, 2,102...Drain main electrode thin film region, 3,103...Source main electrode thin film region,
4,104... Gate electrode, 5,105... High resistance semiconductor thin film, 6,106... Gate insulating film,
7, 17, 117...Insulating film.
Claims (1)
記基板上に設けられた第１主電極薄膜領域と、 上記第１主電極薄膜領域の上部に、少なくとも
一端が載置された絶縁膜と、 上記絶縁膜の内側上部に、少なくとも一端が載
置された第２主電極薄膜領域と、 上記第１および第２主電極薄膜領域に接し、か
つ、上記絶縁膜の上面および一端側面に設けられ
た高抵抗半導体薄膜領域と、 上記高抵抗半導体薄膜領域にゲート絶縁膜およ
びゲート電極とを設けてなる薄膜トランジスタ。 ２ 第１主電極薄膜領域と第２主電極薄膜領域と
は、少なくともその一部が絶縁膜を介して重なつ
ていることを特徴とする特許請求の範囲第１項記
載の薄膜トランジスタ。 ３ ゲート電極、第１主電極薄膜領域および第２
主電極薄膜領域とは、遮光性材料により構成され
ていることを特徴とする特許請求の範囲第２項記
載の薄膜トランジスタ。[Scope of Claims] 1. A substrate having at least a surface made of an insulating material, a first main electrode thin film region provided on the substrate, and at least one end placed on top of the first main electrode thin film region. an insulating film; a second main electrode thin film region having at least one end placed on the inner upper part of the insulating film; and a top surface and one end side surface of the insulating film that is in contact with the first and second main electrode thin film regions; A thin film transistor comprising: a high resistance semiconductor thin film region provided in the high resistance semiconductor thin film region; and a gate insulating film and a gate electrode provided in the high resistance semiconductor thin film region. 2. The thin film transistor according to claim 1, wherein the first main electrode thin film region and the second main electrode thin film region at least partially overlap with each other with an insulating film interposed therebetween. 3 Gate electrode, first main electrode thin film region and second
3. The thin film transistor according to claim 2, wherein the main electrode thin film region is made of a light-shielding material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10992883A JPS601868A (en) | 1983-06-17 | 1983-06-17 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10992883A JPS601868A (en) | 1983-06-17 | 1983-06-17 | Thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS601868A JPS601868A (en) | 1985-01-08 |
| JPH0519831B2 true JPH0519831B2 (en) | 1993-03-17 |
Family
ID=14522661
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10992883A Granted JPS601868A (en) | 1983-06-17 | 1983-06-17 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS601868A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6089958A (en) * | 1983-10-24 | 1985-05-20 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| JPH07120803B2 (en) * | 1985-08-12 | 1995-12-20 | 日本電信電話株式会社 | Insulated gate type thin film transistor and manufacturing method thereof |
| KR950001159B1 (en) * | 1991-12-27 | 1995-02-11 | 삼성전자 주식회사 | Tft and its manufacturing method for memory device |
| KR102551998B1 (en) * | 2018-11-20 | 2023-07-06 | 엘지디스플레이 주식회사 | Vertical structure transistor and electronic device |
-
1983
- 1983-06-17 JP JP10992883A patent/JPS601868A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS601868A (en) | 1985-01-08 |
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