CN102437196B - Low-temperature polycrystalline silicon thin-film transistor and manufacturing method thereof - Google Patents
Low-temperature polycrystalline silicon thin-film transistor and manufacturing method thereof Download PDFInfo
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- CN102437196B CN102437196B CN201110419036XA CN201110419036A CN102437196B CN 102437196 B CN102437196 B CN 102437196B CN 201110419036X A CN201110419036X A CN 201110419036XA CN 201110419036 A CN201110419036 A CN 201110419036A CN 102437196 B CN102437196 B CN 102437196B
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 56
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000010409 thin film Substances 0.000 title abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 229920005591 polysilicon Polymers 0.000 claims description 47
- 238000000034 method Methods 0.000 claims description 37
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 238000001259 photo etching Methods 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 15
- 239000011521 glass Substances 0.000 claims description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 239000003795 chemical substances by application Substances 0.000 claims description 9
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 8
- 238000002425 crystallisation Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 238000001035 drying Methods 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 230000008025 crystallization Effects 0.000 claims description 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 4
- 239000004411 aluminium Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 4
- 239000011651 chromium Substances 0.000 claims description 4
- 239000002131 composite material Substances 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 4
- 238000003475 lamination Methods 0.000 claims description 4
- 239000007790 solid phase Substances 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000003486 chemical etching Methods 0.000 claims description 3
- 229910000765 intermetallic Inorganic materials 0.000 claims description 3
- 238000005224 laser annealing Methods 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 239000007792 gaseous phase Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 48
- 239000010408 film Substances 0.000 description 22
- 238000010586 diagram Methods 0.000 description 15
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000004380 ashing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000839 emulsion Substances 0.000 description 1
- 238000007715 excimer laser crystallization Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L2029/42388—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor characterised by the shape of the insulating material
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Abstract
The invention discloses a low-temperature polycrystalline silicon thin-film transistor and a manufacturing method thereof, wherein the low-temperature polycrystalline silicon thin-film transistor comprises a grid electrode, a source electrode and a drain electrode, wherein the source electrode and the drain electrode are separated by a channel; silicon island patterns of polycrystalline silicon are formed among the grid electrode, the source electrode and the drain electrode, wherein the silicon island patterns of polycrystalline silicon at the channel part are provided with at least one groove so as to form a three-dimensional channel; and the depth of the groove is less than that of the channel. According to the low-temperature polycrystalline silicon thin-film transistor provided by the invention, the three-dimensional channel is formed on the silicon island patterns of polycrystalline silicon at the channel part through diffraction exposure, the width of the channel is increased effectively, thus the width to length ratio and aperture opening ratio of the thin-film transistor are increased, the structure is simple, and the low-temperature polycrystalline silicon thin-film transistor is easy to realize.
Description
Technical field
The present invention relates to a kind of manufacture method of thin-film transistor, relate in particular to a kind of manufacture method of low-temperature polysilicon film transistor.
Background technology
Organic light emitting display (OLED) is the active illuminating device.Compare present main flow flat panel display Thin Film Transistor-LCD (TFT-LCD), OLED has high-contrast, wide viewing angle, low-power consumption, the advantages such as volume is thinner, being expected to become the flat panel display of future generation after LCD, is one of the maximum technology that receives publicity in the present flat panel display.
Main low-temperature polysilicon film transistor (LTPS-TFT) driving OLED of using is luminous at present, and Fig. 1 is a kind of plane graph of prior art thin-film transistor, and Fig. 2 is according to the formed sectional view of A-A line among Fig. 1.As depicted in figs. 1 and 2, use first method deposition resilient coating, the then deposition of amorphous silicon on resilient coating of chemical vapour deposition (CVD) in glass substrate; Use the method for solid-phase crystallization or Excimer-Laser Crystallization to be converted into polysilicon amorphous silicon layer; At last etching polysilicon is become the silicon island shape and form successively insulating barrier, gate metal layer, dielectric layer and source in the above to leak metal layer pattern, and final formation drives thin-film transistor.
Because the electric current that the luminous needs of driving OLED are larger, so drive TFT need to have wider channel width and short channel length so that the ratio of width and length is enough large, thereby drive TFT can provide enough electric current with control and to drive organic electroluminescent LED luminous for OLED.
In order to guarantee the resolution of display screen, the area of pixel region needs as much as possible little, aperture opening ratio needs large as much as possible, therefore drive thin-film transistor and peripheral circuit can not surpass certain area, it is too wide that this has just determined that the channel width of thin-film transistor can not be done, the breadth length ratio that needs in this case to increase thin film transistor channel just can only solve by reducing length, but thin film transistor channel length is reduced to phenomenons such as to a certain degree can causing leakage current and raceway groove puncture, causes thin-film transistor to work.
Summary of the invention
Technical problem to be solved by this invention provides a kind of manufacture method of low-temperature polysilicon film transistor, can effectively increase channel width, thereby increases breadth length ratio and the aperture opening ratio of thin-film transistor, and simple in structure, easy to implement.
The present invention also provides a kind of low-temperature polysilicon film transistor manufacture method for solving the problems of the technologies described above, described low-temperature polysilicon film transistor comprises grid, source electrode and drain electrode, there is raceway groove to separate between described source electrode and the drain electrode, described grid and source electrode, be formed with polysilicon silicon island pattern between the drain electrode, thereby have at least a groove to form three-dimensional raceway groove on the polysilicon silicon island pattern at described raceway groove place, the degree of depth of described groove is less than the degree of depth of raceway groove, comprise the steps: at first to use chemical gaseous phase depositing process to deposit successively one deck resilient coating and an amorphous silicon layer at glass substrate, adopting quasi-molecule laser annealing or solid-phase crystallization method is polysilicon layer with the amorphous silicon layer crystallization; Use the first mask plate, form photoetching agent pattern by photoetching at polysilicon layer, described the first mask plate is many gray-tone masks plate, forms the first height photoresist layer and the second height photoresist layer at channel region, and described the first height is less than the second height; Use photoetching agent pattern, comprise the polysilicon silicon island pattern of raceway groove, source/drain contact region by the chemical drying method etching procedure formation first time; Removal has the photoresist of the first height; Then by the second time chemical drying method etching procedure form three-dimensional channel pattern; Continue deposition gate insulator and the first metal layer at the glass substrate with silicon island pattern, then form gate metallic pattern through photoetching and etching procedure; Having on the glass baseplate surface of gate metallic pattern, deposit again a dielectric layer; Then utilize the chemical etching operation above source/drain contact region, to form contact hole; At glass baseplate surface deposition the second metal level, then utilize photoetching and etching procedure at last, form source electrode and drain electrode.
Above-mentioned low-temperature polysilicon film transistor manufacture method, wherein, described gate insulator is silicon oxide layer, silicon nitride layer or composite insulation layer.
Above-mentioned low-temperature polysilicon film transistor manufacture method, wherein, described the first metal layer and the second metal level are an aluminium lamination, a tungsten layer, a chromium layer or metallic compound conductive layer.
Above-mentioned low-temperature polysilicon film transistor manufacture method, wherein, described dielectric layer is silica or silicon nitride.
The present invention contrasts prior art following beneficial effect: low-temperature polysilicon film transistor provided by the invention and manufacture method thereof, form three-dimensional raceway groove by the diffraction exposure at the polysilicon silicon island at raceway groove place pattern, effectively increase channel width, thereby increase breadth length ratio and the aperture opening ratio of thin-film transistor, and simple in structure, easy to implement.
Description of drawings
Fig. 1 is a kind of low-temperature polysilicon film transistor floor map;
Fig. 2 is for having a kind of low-temperature polysilicon film transistor now along A-A line sectional view;
Fig. 3 is that low-temperature polysilicon film transistor of the present invention is along A-A line sectional view;
Fig. 4 A is existing low-temperature polysilicon film transistor channel width schematic diagram;
Fig. 4 B is low-temperature polysilicon film transistor channel width schematic diagram of the present invention;
Fig. 5 A is that the present invention forms the resilient coating schematic diagram;
Fig. 5 B is that the present invention forms the amorphous silicon layer schematic diagram;
Fig. 5 C is that the present invention forms the polysilicon semiconductor layer schematic diagram;
Fig. 5 D is that polysilicon photoetching agent pattern of the present invention forms schematic diagram;
Fig. 5 E is that poly-silicon pattern of the present invention forms schematic diagram;
Fig. 5 F is photoresist shape schematic diagram behind the cineration technics of the present invention;
Fig. 5 G is that the three-dimensional raceway groove of the present invention forms schematic diagram;
Fig. 5 H is that the present invention forms the gate insulator schematic diagram;
Fig. 5 I is that the present invention forms the gate metal layer schematic diagram;
Fig. 5 J is that the present invention forms the gate pattern schematic diagram;
Fig. 5 K is that the present invention forms dielectric layer and source/drain contact hole schematic diagram;
Fig. 5 L is that the present invention forms source/leakage metal pattern schematic diagram.
Among the figure:
1 resilient coating, 2 ' amorphous silicon layer, 2 polysilicon layers
3 gate insulation layers, 4 dielectric layers, 5 photoetching agent patterns
6 mask plates, 21 grooves, 31 grids
42 drain electrodes of 41 source electrodes.
Embodiment
The invention will be further described below in conjunction with drawings and Examples.
Fig. 3 is that low-temperature polysilicon film transistor of the present invention is along A-A line sectional view; Fig. 4 is the present invention and existing a kind of low-temperature polysilicon film transistor channel width contrast schematic diagram.
See also Fig. 3, Fig. 4 A and Fig. 4 B, low-temperature polysilicon film transistor provided by the invention comprises grid 31, source electrode 41 and drains 42, described source electrode 41 and drain and have raceway groove to separate between 42, be formed with polysilicon silicon island pattern between described grid 31 and source electrode 41, the drain electrode 42, wherein, thereby have at least a groove 21 to form three-dimensional raceway groove on the polysilicon silicon island pattern at described raceway groove place, the degree of depth of described groove 21 is less than the degree of depth of raceway groove.The three-dimensional film transistor that the present invention forms, channel width has increased the height (L2+L4) of three-dimensional trench sidewalls, and length L 1+L3+L5 still equals existing length L; When adopting N groove/shape for lugs, the channel width of increase is N*(L2+L4), N is natural number, thereby obviously increases breadth length ratio.The minimum number of groove/projection is one, and the upper limit is determined jointly by the making precision of channel width, exposure machine resolution and MASK; The depth/height of groove/projection is determined by the degree of depth of raceway groove, can be slightly less than the degree of depth of raceway groove.
The below introduces low-temperature polysilicon film transistor manufacture method provided by the invention in detail:
Shown in Fig. 5 A, at first use chemical vapor deposition (CVD) method deposition one deck resilient coating 1 at array base palte (glass); Shown in Fig. 5 B, use chemical vapor deposition (CVD) method deposited amorphous silicon layer 2 ' at resilient coating 1; Shown in Fig. 5 C, adopting quasi-molecule laser annealing (ELA) or solid-phase crystallization (SPC) method is polysilicon layer 2 with the amorphous silicon crystallization.
Shown in Fig. 5 D, with the first mask plate 6, form photoetching agent pattern 5 by photoetching at polysilicon layer 2.The first mask plate is many GTGs photomask blank, can be divided into two kinds of Gray-tone mask and Half tone mask.Gray-tone mask produces the following slit of exposure machine resolution, covers a part of light source by this slit position again, to reach the effect of half exposure.On the other hand, Half tone mask is the film that utilizes " half sees through ", carries out half exposure.Because above dual mode all is to present 3 kinds the exposure level that " exposed portion " " half exposed portion " reaches " unexposed portion " behind 1 time exposure process, after development, can form the photoresist (emulsion) of 2 kinds of thickness; The present invention forms the first height photoresist layer and the second height photoresist layer at channel region, and described the first height is less than the second height.
Shown in Fig. 5 E, use photoetching agent pattern, form the polysilicon silicon island pattern that comprises raceway groove, source/drain contact region by chemical drying method etching (CDE) operation.
Shown in Fig. 5 F, after etching is finished, the photoresist on top, polysilicon silicon island is carried out the ashing operation, the photoresist with first height is removed, and obtains photoetching agent pattern as shown in the figure, forms at least one channel grooves 21.
Shown in Fig. 5 G, form the three-dimensional channel pattern of wanting required for the present invention by chemical drying method etching (CDE) operation for the second time.
Shown in Fig. 5 H, deposit gate insulator 3 by the chemical vapor deposition (CVD) method at the glass substrate with silicon island pattern, such as silicon oxide layer, silicon nitride layer or composite insulation layer;
Shown in Fig. 5 I, form a metal level by the physical vapor deposition (PVD) method at insulating barrier, this metal level can be an aluminium lamination, a tungsten layer, a chromium layer or other metals and metallic compound conductive layer, forms grid 31 metal patterns behind described the first metal layer process photoetching and the etching procedure.
Fig. 5 J～Fig. 5 L be among Fig. 1 along the formed sectional view of B-B line, the first metal layer that Fig. 5 I forms forms grid 31 metal patterns after through photoetching and etching procedure.
Shown in Fig. 5 K, have on the glass baseplate surface of gate metallic pattern, deposit again a dielectric layer 4, the material of this dielectric layer 4 can be silica or silicon nitride; Then utilize the chemical etching operation within the dielectric layer above source electrode ohmic contact zone and the drain electrode ohmic area and insulating barrier, to form respectively the contact hole of a through source electrode and the contact hole of drain electrode.
Shown in Fig. 5 L, at last at glass baseplate surface deposition the second metal level, such as an aluminium lamination, a tungsten layer, a chromium layer or other metal single layers or composite multi-layer conductive layer; Then utilize photoetching and etching procedure, form source electrode 41 and drain electrode 42, so just can be electrically connected to drain electrode to signal from source electrode, finish the manufacture process of whole low-temperature polysilicon film transistor.
Although the present invention discloses as above with preferred embodiment; so it is not to limit the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.
Claims (4)
1. the manufacture method of a low-temperature polysilicon film transistor, described low-temperature polysilicon film transistor comprises grid, source electrode and drain electrode, there is raceway groove to separate between described source electrode and the drain electrode, be formed with polysilicon silicon island pattern between described grid and source electrode, the drain electrode, thereby have at least a groove to form three-dimensional raceway groove on the polysilicon silicon island pattern at described raceway groove place, the degree of depth of described groove is characterized in that less than the degree of depth of raceway groove, comprises the steps:
At first use chemical gaseous phase depositing process to deposit successively one deck resilient coating and an amorphous silicon layer at glass substrate, adopting quasi-molecule laser annealing or solid-phase crystallization method is polysilicon layer with the amorphous silicon layer crystallization;
Use the first mask plate, form photoetching agent pattern by photoetching at polysilicon layer, described the first mask plate is many gray-tone masks plate, forms the first height photoresist layer and the second height photoresist layer at channel region, and described the first height is less than the second height;
Use photoetching agent pattern, comprise the polysilicon silicon island pattern of raceway groove, source/drain contact region by the chemical drying method etching procedure formation first time; Removal has the photoresist of the first height; Then by the second time chemical drying method etching procedure form three-dimensional channel pattern;
Continue deposition gate insulator and the first metal layer at the glass substrate with silicon island pattern, then form gate metallic pattern through photoetching and etching procedure;
Having on the glass baseplate surface of gate metallic pattern, deposit again a dielectric layer; Then utilize the chemical etching operation above source/drain contact region, to form contact hole;
At glass baseplate surface deposition the second metal level, then utilize photoetching and etching procedure at last, form source electrode and drain electrode.
2. the manufacture method of low-temperature polysilicon film transistor as claimed in claim 1 is characterized in that, described gate insulator is silicon oxide layer, silicon nitride layer or composite insulation layer.
3. the manufacture method of low-temperature polysilicon film transistor as claimed in claim 1 is characterized in that, described the first metal layer and the second metal level are an aluminium lamination, a tungsten layer, a chromium layer or metallic compound conductive layer.
4. the manufacture method of low-temperature polysilicon film transistor as claimed in claim 1 is characterized in that, described dielectric layer is silica or silicon nitride.
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| CN103824780B (en) * | 2014-02-28 | 2016-03-30 | 上海和辉光电有限公司 | A kind of low temperature polycrystalline silicon TFT device and manufacture method thereof |
| CN104617132B (en) * | 2014-12-31 | 2017-05-10 | 深圳市华星光电技术有限公司 | Low-temperature polycrystalline silicon thin film transistor and manufacturing method thereof |
| CN104576761B (en) * | 2015-02-06 | 2018-05-08 | 合肥京东方光电科技有限公司 | Thin film transistor (TFT) and its manufacture method, display base plate and display device |
| US10825839B2 (en) * | 2016-12-02 | 2020-11-03 | Innolux Corporation | Touch display device |
| CN107204375B (en) * | 2017-05-19 | 2019-11-26 | 深圳市华星光电技术有限公司 | Thin film transistor and its manufacturing method |
| CN110729359A (en) * | 2019-10-25 | 2020-01-24 | 深圳市华星光电半导体显示技术有限公司 | Thin film transistor, display panel and manufacturing method of thin film transistor |
| CN114005881B (en) * | 2021-10-27 | 2023-04-18 | 云谷（固安）科技有限公司 | Thin film transistor, preparation method thereof and pixel circuit |
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