CN103824780B - A kind of low temperature polycrystalline silicon TFT device and manufacture method thereof - Google Patents
A kind of low temperature polycrystalline silicon TFT device and manufacture method thereof Download PDFInfo
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- CN103824780B CN103824780B CN201410073494.6A CN201410073494A CN103824780B CN 103824780 B CN103824780 B CN 103824780B CN 201410073494 A CN201410073494 A CN 201410073494A CN 103824780 B CN103824780 B CN 103824780B
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 16
- 238000009413 insulation Methods 0.000 claims description 16
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- 230000008021 deposition Effects 0.000 claims description 13
- 235000012239 silicon dioxide Nutrition 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 230000004888 barrier function Effects 0.000 claims description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 238000003475 lamination Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 238000005240 physical vapour deposition Methods 0.000 claims description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 5
- 239000011733 molybdenum Substances 0.000 claims description 5
- 230000008859 change Effects 0.000 claims description 4
- 238000005224 laser annealing Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000002360 preparation method Methods 0.000 abstract description 7
- 239000007787 solid Substances 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910004205 SiNX Inorganic materials 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 239000010409 thin film Substances 0.000 description 5
- 239000010408 film Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000008280 blood Substances 0.000 description 1
- 210000004369 blood Anatomy 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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Abstract
The invention discloses a kind of new type low temperature polysilicon TFT device structure and manufacture method thereof, the application by first preparing one or more protruding figure, is then formed at least regional area that an active area covers described protruding figure dome top surface and at least one sidewall covering protruding figure and then forms channel region.The present invention is by the protruding figure of preparation one solid, then channel region is formed above it, can under the prerequisite not changing substrate projected area, effectively increase channel width, and then increase the breadth length ratio of raceway groove, improve ON state current Ion, and then improve driving force and the device performance of TFT device.
Description
Technical field
The present invention relates to field of semiconductor fabrication, a kind of new type low temperature polysilicon TFT device structure and manufacture method thereof are specifically set.
Background technology
Current Display Technique is towards high-resolution, high PPI(per inch pixel) development, the resolution of such as mobile phone has reached the level (1080 × 1920) of 1080P, and the resolution of TV reaches 4K(4096 × 2160 especially) rank, along with the continuous lifting of resolution, need the driving force improving constantly TFT device, therefore drive at pixel region and Drive() district all requires to improve Ion(ON state current).
Improving one of method of Ion is the breadth length ratio (W/L) increasing TFT device channel, and reference formula is as follows:
Linear district Ion formula is
Saturation region Ion equation is
Improve breadth length ratio and have two kinds of methods, one is increase channel width (W), but can affect aperture opening ratio, reduces the space of panel designs, and two is reduce channel length (L), but is limited in scope, and L is too small to be had and cause the breakdown risk of raceway groove.
Figure 1 shows that the sectional view of prior art TFT structure, Fig. 2 is the plane graph of prior art TFT structure; As shown in Figure 1-2, existing TFT structure comprises substrate 1, and has a resilient coating 2 at the disposed thereon of substrate 1, and this resilient coating 2 upper surface is formed with silicon island figure 3, and the surface of this silicon island figure 3 and the upper surface of resilient coating 2 deposit gate insulation layer 4 and grid 5 successively.If want to increase breadth length ratio according to above-mentioned raising breadth length ratio, the object increasing breadth length ratio is reached by increasing channel width W or reducing channel length, and in order to ensure the resolution of display screen, then the area of pixel region is little as much as possible, and aperture opening ratio is large as much as possible, namely thin-film transistor and peripheral circuit is driven can not to exceed certain area, it is too wide that this channel width just determining thin-film transistor can not be done, only have in this case and increase breadth length ratio by reducing channel length, but thin film transistor channel length is reduced to and to a certain degree can causes the phenomenons such as leakage current and raceway groove puncture, thin-film transistor is caused to work.Therefore, how under the prerequisite ensureing proper device operation, increase the breadth length ratio of raceway groove, for those skilled in the art endeavour the direction studied.
Chinese patent (CN102437196A) discloses a kind of low-temperature polysilicon film transistor and manufacture method thereof, described low-temperature polysilicon film transistor comprises grid, source electrode and drain electrode, raceway groove is had to separate between described source electrode and drain electrode, polysilicon silicon island figure is formed between described grid and source electrode, drain electrode, wherein, the polysilicon silicon island figure at described raceway groove place has a groove at least thus forms three-dimensional raceway groove, the degree of depth of described groove is less than the degree of depth of raceway groove.Low-temperature polysilicon film transistor provided by the invention, the polysilicon silicon island figure being exposed on raceway groove place is formed three-dimensional raceway groove, effectively increase channel width by diffraction, thus increases breadth length ratio and the aperture opening ratio of thin-film transistor.
This patent is by forming groove at diffraction with being dry-etched on the figure of silicon island, thus increases the surface area of silicon island, thus increases channel width.Although the method can increase channel width, but owing to have employed dry etching, to a great extent to Channel(raceway groove) surface causes damage, must cause Vfb(flat band voltage) change, thus affect Vth(critical voltage) value, affect the performance of device.
Chinese patent (CN1971390A) discloses a kind of TFTLCD dot structure, its by annular or polygonal TFT device layout on grid line (GATE), the via hole of pixel (VIAHOLE) part is the most important thing is also to be designed on grid line, this kind of design can increase the breadth length ratio (W/L) of raceway groove when not reducing aperture opening ratio, improve ON state current (Ion), the most important thing is to play certain restriction to the column shaped spacer (PS) that current color film (COLORFILTER) adopts.
This patent is by the via hole part of pixel being also designed on grid line, and then increases breadth length ratio, improves ON state current, but the processing step more complicated of this patent, realize difficulty comparatively large, therefore in the application of reality, receive certain restriction.
Summary of the invention
The invention provides a kind of low temperature polycrystalline silicon TFT device and manufacture method thereof, under the prerequisite ensureing device performance, effectively increase the breadth length ratio of raceway groove, improve ON state current, and then improve the driving force of TFT circuit.
The technical solution used in the present invention is:
A manufacture method for low temperature polycrystalline silicon TFT device, wherein, comprises the following steps:
Step S1, provide semi-conductive substrate, deposit a laying and a dielectric layer in the surface of described Semiconductor substrate successively;
Step S2, etch described dielectric layer and form the protruding figure be positioned on described laying, etching stopping is at described laying upper surface;
Step S3, deposit an amorphous silicon layer and cover above described protruding figure and laying, and the sidewall of described protruding figure is covered, and described amorphous silicon layer is converted into polysilicon layer;
Step S4, etch described polysilicon layer and form an active area, described active area covers at least regional area of described protruding figure dome top surface and covers at least one sidewall of protruding figure;
Step S5, form an insulating barrier and a gate material layers successively in described laying and active region;
Step S6, etch the gate insulation layer that described insulating barrier and described gate material layers form a grid and be positioned at below this grid;
Wherein, the lamination of described grid and gate insulation layer at least has the stacked gate above the channel region overlapping on active area, and the one source pole district of active area and a drain region lay respectively at the both sides of channel region.
Above-mentioned method, wherein, forms protruding figure described at least one in described step S2 on described laying.
Above-mentioned method, wherein, described active area covers the dome top surface of described protruding figure and the surface of both sides sidewall completely.
Above-mentioned method, wherein, described active area covers described protruding figure portion of upper surface and is positioned at the surface of sidewall of this portion of upper surface homonymy.
Above-mentioned method, wherein, described active area covers the liner layer portion upper surface near described protruding figure at least side sidewall.
Above-mentioned method, wherein, adopt plasma reinforced chemical vapour deposition technique to deposit respectively in step S1 and form described laying and dielectric layer, the temperature of deposition is 400 ~ 450 DEG C, described laying thickness is 400 ~ 500 dusts, and described thickness of dielectric layers is 2000 ~ 2500 dusts.
Above-mentioned method, wherein, described laying is silicon nitride layer, and described dielectric layer is silicon dioxide layer.
Above-mentioned method, wherein, the height of described protruding figure is 400 ~ 600 dusts, and the angle between described protruding figure both sides sidewall and described laying is 40 ° ~ 60 °.
Above-mentioned method, wherein, adopt chemical vapor deposition method to deposit described amorphous silicon layer, the temperature of deposition is 400 ~ 500 DEG C, and the thickness depositing described amorphous silicon layer is 400 ~ 500 dusts.
Above-mentioned method, wherein, adopts laser annealing technique that described amorphous silicon layer is converted into polysilicon layer in described step S3.
Above-mentioned method, wherein, adopt chemical vapor deposition method to deposit described insulating barrier, and described insulating barrier comprises silicon dioxide layer and is covered in the silicon nitride layer on this silicon dioxide layer.
Above-mentioned method, wherein, adopt described gate material layers deposited by physical vapour deposition (PVD), described gate material layers material is molybdenum, and the described gate of formation is 2000 ~ 3000 dusts.
A kind of low temperature polycrystalline silicon TFT device, wherein, described device comprises semi-conductive substrate, and described substrate is coated with a laying, and is positioned on this laying and is formed with protruding figure,
One active area covers at least regional area of described protruding figure dome top surface and covers at least one sidewall of protruding figure;
The gate insulation layer that described TFT device also comprises a grid and is positioned at below this grid, and the one source pole district of active area and a drain region lay respectively at the both sides of channel region;
Wherein, be formed with a lamination between described grid and described gate insulation layer, and this lamination at least has overlapping stacked gate on the active area, described stacked gate is positioned at the top of a channel region.
Above-mentioned device, wherein, is formed with at least one protruding figure on described substrate.
Above-mentioned device, wherein, described active area covers whole upper surface of described protruding figure and the surface of both sides sidewall, and covers the upper surface of the laying exposure between adjacent protrusion figure.
Above-mentioned device, wherein, described active area covers described protruding figure portion of upper surface and is positioned at the sidewall surfaces of this portion of upper surface homonymy.
Above-mentioned method, wherein, described active area covers the liner layer portion upper surface near described protruding figure at least side sidewall.
Above-mentioned TFT device, wherein, described laying is silicon nitride layer, and described silicon nitride layer thickness is 400 ~ 500 dusts.
Above-mentioned TFT device, wherein, described protruding figure material is silicon dioxide, and described protruding figure height is 400 ~ 600 dusts, and the angle between this protruding figure both sides sidewall and described laying is 40 ° ~ 60 °.
Above-mentioned TFT device, wherein, described gate insulation layer comprises silicon dioxide layer and silicon nitride layer from bottom to top successively, and described silicon dioxide layer thickness is 400 ~ 500 dusts, and described silicon nitride layer thickness is 700 ~ 800 dusts.
Above-mentioned TFT device, wherein, described gate is 2000 ~ 3000 dusts, and described grid material is molybdenum.
Owing to present invention employs above technical scheme, by preparing the protruding figure of at least one solid above laying, then proceeding follow-up preparation technology and forming raceway groove and metal gates.Under the prerequisite not increasing projected area, effectively add the width of raceway groove, and then increase the breadth length ratio of raceway groove, improve the ON state current of TFT drive circuit, and then be conducive to the performance of boost device.
Accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, the present invention and feature, profile and advantage will become more obvious.Mark identical in whole accompanying drawing indicates identical part.Deliberately proportionally do not draw accompanying drawing, focus on purport of the present invention is shown.
Fig. 1 is the sectional view of TFT structure in prior art;
Fig. 2 is the plane graph of prior art TFT structure;
Fig. 3 is the sectional view after deposited liner layer of the present invention and dielectric layer;
Fig. 4 is the sectional view after etch media layer of the present invention forms protruding figure;
Fig. 5 is the schematic diagram after deposition of amorphous silicon layers of the present invention;
Fig. 6 is after amorphous silicon layer is converted into polysilicon layer by the present invention and etches the sectional view after being formed with source region;
Fig. 7 is the schematic diagram after the present invention forms metal gate;
Fig. 8 is the comparison diagram of TFT device in the TFT device that formed of the application and prior art;
Fig. 9 is the TFT device sectional view that the application forms two protruding figures on laying;
Figure 10 is the TFT device sectional view that active region of the present invention is covered on protruding figure.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
The invention provides a kind of low temperature polycrystalline silicon TFT preparation method, Fig. 3-8 is depicted as the flow chart of a kind of low temperature polycrystalline silicon TFT of the present invention preparation method, comprises the following steps:
Step S1, first provide semi-conductive substrate 1, adopt plasma reinforced chemical vapour deposition technique to deposit a laying 2 and dielectric layer 6 from bottom to top at substrate surface, in deposition process, the temperature of deposition be 400 ~ 450 DEG C (as 400 DEG C, 420 DEG C, 450 DEG C).Wherein, laying thickness is 400 ~ 500 dusts (as 400 dusts, 430 dusts, 450 dusts, 480 dusts, 500 dusts), and dielectric layer 6 thickness is 2000 ~ 2500 dusts (as 2000 dusts, 2200 dusts, 2400 dusts, 2500 dusts).Preferably, this laying 2 material is silicon nitride layer (SiNx), and dielectric layer 6 material is SiO2, forms structure shown in Fig. 3.In the prior art, general employing SiNx, organic substance or metal as dielectric layer, but those skilled in the art find: due to SiNx and polysilicon layer lattice poor, if directly contacted with channel layer, wild effect is caused, so SiNx can not be selected as dielectric layer at contact-making surface; And organic thermal endurance is poor, once run into high-temperature condition (as CVD, PECVD) easily produce dust in subsequent technique, and then pollutes, production is impacted; And metal material due to its thermal conductivity good, after being heated, temperature rises very fast, and then follow-up ELA(ExcimerLaserAnnealing excimer laser annealing technology may be affected) processing procedure, polysilicon crystal comparatively fast may be caused to be deteriorated owing to heating up, affect electron mobility, affect device performance.Therefore, preferably, the present invention adopts SiO
2be best-of-breed technology scheme as dielectric layer 6.
Step S2, adopt photoetching process and remove part dielectric layer 6 in conjunction with dry etching, laying 2 is formed at least one protruding figure 6 ' (quantity of protruding figure sets according to process requirements).As shown in Figure 4, this protruding figure height is 400 ~ 600 dusts (as 400 dusts, 500 dusts, 550 dusts, 600 dusts etc.), the angle between both sides sidewall and laying be 40 ° ~ 60 ° (as 40 °, 50 °, 60 ° etc.).In actual application of the present invention, the reaction condition by adjusting photoetching and dry etching controls the pattern of protruding figure 6 '.
Step S3, deposit an amorphous silicon layer and cover above protruding figure 6 ' and laying 2, and the sidewall of described protruding figure 6 ' is covered.Wherein, the temperature of deposition be 400 ~ 500 DEG C (as 400 DEG C, 450 DEG C, 500 DEG C etc.), the thickness of deposition of amorphous silicon layers is 400 ~ 500 dusts (as 400 dusts, 450 dusts, 500 dusts etc.); Then carry out laser annealing technique, amorphous silicon layer is converted into polysilicon layer 7, as shown in Figure 5.
Step S4, etches polycrystalline silicon layer 7 form an active area 7 ', and active area 7 ' covers at least regional area of protruding figure 6 ' dome top surface and covers at least one sidewall of protruding figure, as shown in Figure 6.
Step S5, form an insulating barrier and a gate material layers successively in laying 2 and top, active area 7 '.Wherein, chemical vapor deposition method is adopted to deposit SiO successively from bottom to top
2layer and a SiNx layer form this insulating barrier jointly.Wherein, the temperature of deposition be 400 ~ 500 DEG C (as 400 DEG C, 450 DEG C, 500 DEG C etc.), deposition SiO
2the thickness of layer is 400 ~ 500 dusts (as 400 dusts, 450 dusts, 500 dusts etc.), and the thickness of deposition SiNx layer is 700 ~ 800 dusts (700 dusts, 730 dusts, 780 dusts, 800 dusts etc.).Formed after gate insulation layer in deposition, then adopt a material deposited by physical vapour deposition (PVD) to be the upper surface of the gate material layers covering gate insulating barrier of molybdenum, the grid material layer thickness of formation is 2000 ~ 3000 dusts (as 2000 dusts, 2500 dusts, 3000 dusts) etc.
The gate insulation layer 8 that step S6, etching insulating layer and gate material layers form a grid 9 and be positioned at below this grid; Wherein, the lamination of this grid 9 and gate insulation layer 8 at least has the stacked gate above the channel region overlapping on active area, and the one source pole district of this active area and a drain region lay respectively at the both sides (not marking in figure) of channel region simultaneously.As shown in Figure 7.The present invention, by preparing the protruding figure of a solid on laying, then forms raceway groove above it, can ensure, under the prerequisite that substrate projected area is constant, effectively to increase the width of raceway groove, and then expand the breadth length ratio of raceway groove, promote ON state current.
Fig. 8 A is the sectional view of prior art low temperature polycrystalline silicon TFT device, Fig. 8 B is the sectional view of a kind of low temperature polycrystalline silicon TFT device provided by the invention, composition graphs 8A and Fig. 8 B can obviously draw, the active area 7 ' that the present invention is formed is positioned at the dome top surface of protruding figure 6 ' and the portions of pads layer upper surface of both sides sidewall and close both sides sidewall, its channel width is obviously longer than the channel width shown in Fig. 8 A, channel length is simultaneously identical, as can be seen here, the present invention is not when increasing substrate projected area, then raceway groove is formed thereon after preparing a protruding figure 6 ', channel width can be increased, because channel width is increased, so the breadth length ratio of raceway groove also can correspondingly increase, and then improve ON state current Ion, improve driving force and the device performance of TFT device.
Embodiment one:
Present invention also offers a kind of low temperature polycrystalline silicon TFT device, as shown in Figure 7, the liner 2 that this device comprises Semiconductor substrate 1 and is positioned on this substrate 1, preferably, this laying 2 thickness is 400 ~ 500 dusts.Be formed with protruding figure 6 ' on laying 2, protruding figure 6 ' is deposition SiO
2and etching is formed.Wherein, this protruding figure 6 ' is highly 400 ~ 600 dusts (as 400 dusts, 450 dusts, 500 dusts, 550 dusts, 600 dusts etc.), the angle between both sides sidewall and laying be 40 ° ~ 60 ° (as 40 °, 50 °, 60 ° etc.);
One active area 7 ' covers at least regional area of protruding figure 6 ' dome top surface and covers at least one sidewall of protruding figure;
Simultaneously, the gate insulation layer 8 that this TFT device also comprises a grid 9 and is positioned at below this grid, the lamination of this grid 9 and gate insulation layer 8 at least has the stacked gate above the channel region overlapping on active area, and the one source pole district of active area and a drain region lay respectively at the both sides of channel region.
Below in conjunction with Fig. 8, advantage of the present invention is further elaborated, composition graphs 8A and Fig. 8 B can obviously draw, the present invention is formed with protruding figure 6 ' above laying 2, then raceway groove is formed, the active area 7 ' that the present invention is formed covers the upper surface of protruding figure 6 ' and the portions of pads layer upper surface of two sidewalls and close sidewall exposure, and active area of the prior art 3 only covers substrate 1 upper surface.Can obviously draw with reference to the accompanying drawings, the present invention (does not namely change channel length) when not increasing substrate projected area, after preparing a protruding figure 6 ', then form raceway groove thereon, can increase channel width.Because channel width is increased, so its breadth length ratio also can correspondingly increase, and then improve ON state current Ion, improve driving force and the device performance of TFT device.
Embodiment two
In actual applications, exposure imaging is carried out and after etch media layer by adopting the light shield of specific standard, multiple protruding figure is formed above laying 2, as shown in Figure 9, laying 2 is formed with two three-dimensional protruding figures 6 ', the surface of the dome top surface of protruding figure and both sides sidewall is all covered by the active area that etching is formed, and the laying upper surface exposed between the upper surface of the laying exposure near protruding figure side sidewall and adjacent two protruding figures is also covered by this active area simultaneously.Because protruding figure 6 ' has certain altitude, active area above it not only comprises the laying covering protruding figure top and part exposure, also cover the sidewall of protruding figure both sides simultaneously, so its channel width certainly will increase to some extent, channel width is added when not affecting projected area, improve the breadth length ratio of raceway groove, improve ON state current Ion, and then improve driving force and the device performance of TFT device.The protruding figure that the present invention is formed on laying can set according to process requirements, not only be confined to two protruding figures 6 ', formation one can be prepared in actual application, two or more silicon island figure all can play the effect increasing channel width-over-length ratio, not repeat them here.
Embodiment three
In another embodiment of the present invention, etching formation is carried out to polysilicon layer by controlling different etching reaction conditions there is difform active area, active area 7 ' part is made to cover the surface of protruding figure and the upper surface of laying, as shown in Figure 10, active area 7 ' be covered in protruding figure 6 ' portion top surface on put part and cover flank part on the sidewall of protruding figure side, and near the portions of pads layer upper surface of protruding figure side sidewall.And then can obtain being different from the different channel width of Fig. 7 with Fig. 9, realize different breadth length ratios, the demand of the different breadth length ratio of different device needs can be met.
In sum, owing to present invention employs above technical scheme, by depositing a laying in advance on substrate, then on this laying, preparation forms protruding figure, then prepare an active area cover at least regional area of protruding figure dome top surface and cover at least one sidewall of protruding figure, then carry out follow-up preparation technology.The present invention forms three-dimensional protruding figure by preparation on laying, then raceway groove is formed above it, while not changing projected area, effectively can increase channel width, and then increase the breadth length ratio of raceway groove, improve ON state current Ion, and then improve driving force and the device performance of TFT device.
Above preferred embodiment of the present invention is described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or being revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (21)
1. a manufacture method for low temperature polycrystalline silicon TFT device, comprises the following steps:
Step S1, provide semi-conductive substrate, deposit a laying and a dielectric layer in the surface of described Semiconductor substrate successively;
Step S2, etch described dielectric layer and form the protruding figure be positioned on described laying, etching stopping is at described laying upper surface;
Step S3, deposit an amorphous silicon layer and cover above described protruding figure and laying, and the sidewall of described protruding figure is covered, and described amorphous silicon layer is converted into polysilicon layer;
Step S4, etch described polysilicon layer and form an active area, described active area covers at least regional area of described protruding figure dome top surface and covers at least one sidewall of protruding figure;
Step S5, form an insulating barrier and a gate material layers successively in described laying and active region;
Step S6, etch the gate insulation layer that described insulating barrier and described gate material layers form a grid and be positioned at below this grid;
Wherein, the lamination of described grid and gate insulation layer at least has the stacked gate above the channel region overlapping on active area, and the one source pole district of active area and a drain region lay respectively at the both sides of channel region, and described protruding figure does not change the length of this channel region while increasing described channel region width.
2. the method for claim 1, is characterized in that, forms protruding figure described at least one in described step S2 on described laying.
3. method as claimed in claim 2, it is characterized in that, described active area covers the dome top surface of described protruding figure and the surface of both sides sidewall completely.
4. method as claimed in claim 2, is characterized in that, described active area covers described protruding figure portion of upper surface and is positioned at the surface of sidewall of this portion of upper surface homonymy.
5. the method as described in claim 3 or 4, is characterized in that, described active area covers the liner layer portion upper surface near described protruding figure at least side sidewall.
6. the method for claim 1, it is characterized in that, adopt plasma reinforced chemical vapour deposition technique to deposit respectively in step S1 and form described laying and dielectric layer, the temperature of deposition is 400 ~ 450 DEG C, described laying thickness is 400 ~ 500 dusts, and described thickness of dielectric layers is 2000 ~ 2500 dusts.
7. the method for claim 1, is characterized in that, described laying is silicon nitride layer, and described dielectric layer is silicon dioxide layer.
8. the method for claim 1, is characterized in that, the height of described protruding figure is 400 ~ 600 dusts, and the angle between described protruding figure both sides sidewall and described laying is 40 ° ~ 60 °.
9. the method for claim 1, is characterized in that, adopt chemical vapor deposition method to deposit described amorphous silicon layer, the temperature of deposition is 400 ~ 500 DEG C, and the thickness depositing described amorphous silicon layer is 400 ~ 500 dusts.
10. the method for claim 1, is characterized in that, adopts laser annealing technique that described amorphous silicon layer is converted into polysilicon layer in described step S3.
11. the method for claim 1, is characterized in that, adopt chemical vapor deposition method to deposit described insulating barrier, and described insulating barrier comprise silicon dioxide layer and is covered in the silicon nitride layer on this silicon dioxide layer.
12. the method for claim 1, is characterized in that, adopt described gate material layers deposited by physical vapour deposition (PVD), and described gate material layers material is molybdenum, and the described gate of formation is 2000 ~ 3000 dusts.
13. 1 kinds of low temperature polycrystalline silicon TFT devices, it is characterized in that, described device comprises semi-conductive substrate, and described substrate is coated with a laying, and is positioned on this laying and is formed with protruding figure,
One active area covers at least regional area of described protruding figure dome top surface and covers at least one sidewall of protruding figure;
The gate insulation layer that described TFT device also comprises a grid and is positioned at below this grid, and the one source pole district of active area and a drain region lay respectively at the both sides of channel region;
Wherein, a lamination is formed between described grid and described gate insulation layer, and this lamination at least has overlapping stacked gate on the active area, described stacked gate is positioned at the top of a channel region, and described protruding figure does not change the length of this channel region while increasing described channel region width.
14. devices as claimed in claim 13, is characterized in that, be formed with at least one protruding figure on described substrate.
15. devices as claimed in claim 13, is characterized in that, described active area covers whole upper surface of described protruding figure and the surface of both sides sidewall, and cover the upper surface of the laying exposure between adjacent protrusion figure.
16. devices as claimed in claim 13, is characterized in that, described active area covers described protruding figure portion of upper surface and is positioned at the sidewall surfaces of this portion of upper surface homonymy.
17. methods as described in claim 15 or 16, is characterized in that, described active area covers the liner layer portion upper surface near described protruding figure at least side sidewall.
18. TFT devices as claimed in claim 13, it is characterized in that, described laying is silicon nitride layer, and described silicon nitride layer thickness is 400 ~ 500 dusts.
19. TFT devices as claimed in claim 13, it is characterized in that, described protruding figure material is silicon dioxide, and described protruding figure height is 400 ~ 600 dusts, and the angle between this protruding figure both sides sidewall and described laying is 40 ° ~ 60 °.
20. TFT devices as claimed in claim 13, it is characterized in that, described gate insulation layer comprises silicon dioxide layer and silicon nitride layer from bottom to top successively, and described silicon dioxide layer thickness is 400 ~ 500 dusts, and described silicon nitride layer thickness is 700 ~ 800 dusts.
21. TFT devices as claimed in claim 13, it is characterized in that, described gate is 2000 ~ 3000 dusts, and described grid material is molybdenum.
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| CN105316453A (en) * | 2014-07-11 | 2016-02-10 | 安徽均益金属科技有限公司 | Rapid cooling device |
| CN104409510A (en) * | 2014-10-28 | 2015-03-11 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method, array substrate and preparation method, and display apparatus |
| CN104576761B (en) * | 2015-02-06 | 2018-05-08 | 合肥京东方光电科技有限公司 | Thin film transistor (TFT) and its manufacture method, display base plate and display device |
| CN104659108A (en) * | 2015-03-19 | 2015-05-27 | 京东方科技集团股份有限公司 | Thin film transistor and manufacturing method thereof as well as array substrate, display panel and display device |
| CN105097895B (en) * | 2015-06-25 | 2018-09-21 | 京东方科技集团股份有限公司 | Thin film transistor (TFT), array substrate and display device |
| CN105390534B (en) * | 2015-10-28 | 2018-07-17 | 武汉华星光电技术有限公司 | The manufacturing method of low-temperature polysilicon film transistor |
| TWI578504B (en) * | 2016-02-05 | 2017-04-11 | 友達光電股份有限公司 | Pixel structure and fabricating method thereof |
| CN105870195B (en) * | 2016-04-18 | 2017-11-07 | 京东方科技集团股份有限公司 | Semiconductor devices and preparation method thereof, array base palte, display device |
| CN106784015B (en) * | 2017-01-03 | 2019-12-03 | 京东方科技集团股份有限公司 | A kind of thin film transistor and its manufacturing method, display base plate and display device |
| CN112534578A (en) * | 2018-05-09 | 2021-03-19 | 深圳市柔宇科技股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN112071863A (en) | 2020-09-04 | 2020-12-11 | Tcl华星光电技术有限公司 | Array substrate |
| CN114361259A (en) * | 2022-01-11 | 2022-04-15 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
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