CN103824780B - A cryogenic device and method polysilicon tft - Google Patents

A cryogenic device and method polysilicon tft Download PDF

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CN103824780B
CN103824780B CN201410073494.6A CN201410073494A CN103824780B CN 103824780 B CN103824780 B CN 103824780B CN 201410073494 A CN201410073494 A CN 201410073494A CN 103824780 B CN103824780 B CN 103824780B
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赵浩然
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上海和辉光电有限公司
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Abstract

本发明公开了一种新型低温多晶硅TFT器件结构及其制造方法,本申请通过先制备一个或多个凸起图形,然后形成一有源区覆盖在所述凸起图形顶部上表面的至少局部区域及覆盖在凸起图形的至少一个侧壁上然后形成沟道区。 The present invention discloses a novel low-temperature polysilicon TFT device structure and manufacturing method of the present application or by preparing a plurality of first protrusion pattern, and then forming an active region overlying at least a partial area of ​​the pattern on the top surface of the projection and then covering the channel region is formed on at least one side wall of the protrusion pattern. 本发明通过制备一立体的凸起图形,然后在其上方形成沟道区,可在不改变衬底投影面积的前提下,有效地增加沟道宽度,进而增大了沟道的宽长比,提高了开态电流Ion,进而提升了TFT器件的驱动能力及器件性能。 The present invention is prepared by a perspective projection pattern, and then forming a channel region over which can be provided without changing the projected area of ​​the substrate, effectively increase the channel width, thereby increasing the width to length ratio of the channel, improve the on-state current Ion, thereby enhancing the drive capability and device performance of the TFT device.

Description

-种低溫多晶括TFT器件及其制造方法 - seed low-temperature polycrystalline TFT device and manufacturing method comprising

技术领域 FIELD

[0001] 本发明设及半导体制作领域,具体设置一种新型低溫多晶娃TFT器件结构及其制造方法。 [0001] The present invention is provided and the semiconductor production field, in particular provided a novel low-temperature polycrystalline baby TFT device structure and its manufacturing method.

背景技术 Background technique

[0002] 目前的显示技术朝着高分辨率、高PPI (每英寸像素)不断发展,例如手机的分辨率已经达到1080P的水准(1080X 1920),而电视的分辨率更是达到4K (4096X2160)的级别, 伴随着分辨率的不断提升,需要不断提高TFT器件的驱动能力,因此在像素区和化ive巧区动)区都要求提高Ion (开态电流)。 [0002] The current display technology towards a high-resolution, high PPI (pixels per inch) continues to develop, such as mobile phones has reached a level of resolution (1080X 1920) 1080P, but TV resolution is reached 4K (4096X2160) level, along with the continuous improvement of the resolution, the need to constantly improve the driving capability of the TFT device, and thus movable in the region of the pixel region Qiao ive) regions are required to improve the Ion (on-state current).

[0003] 提高提高Ion的方法之一是增大TFT器件沟道的宽长比(W/L),参考公式如下: [0003] One improved method is increased to improve Ion TFT device channel width to length ratio (W / L), with reference to the following formula:

Figure CN103824780BD00041

[0006] 提高宽长比有两种方法,一是增加沟道宽度(W),但是会影响开口率,降低面板设计的空间,二是减小沟道长度(L),但是范围有限,L过小有导致沟道被击穿风险。 [0006] improve the aspect ratio, there are two methods, one is to increase the channel width (W), but will affect the aperture ratio of the panel design to reduce the space, the second is to reduce the channel length (L), but the limited range, L there are too small channel leading to the breakdown of risk.

[0007] 图1所示为现有技术TFT结构的截面图,图2为现有技术TFT结构的平面图;如图1-2所示,现有的TFT结构包括衬底1,且在衬底1的上方沉积有一缓冲层2,该缓冲层2上表面形成有娃岛图形3,该娃岛图形3的表面及缓冲层2的上表面依次沉积有栅绝缘层4和栅极5。 [0007] Figure 1 is a cross-sectional view of a prior art TFT configuration of FIG. 2 is a plan view of the prior art TFT configuration; shown in Figure 1-2, the conventional structure comprises a TFT substrate 1, and the substrate 1, there is deposited over the baby island pattern 32, the buffer layer 2 is formed on a surface of a buffer layer, the surface of the baby island pattern 3 and the upper surface of the buffer layer 2 are sequentially deposited the gate insulating layer 4 and the gate 5. 根据上述提高宽长比如果想要增大宽长比,可通过增加沟道宽度W或减小沟道长度来达到增大宽长比的目的,而为了保证显示屏的分辨率,则像素区的面积要尽可能的小, 且开口率要尽可能的大,即驱动薄膜晶体管W及外围电路不能超过一定的面积,运就决定了薄膜晶体管的沟道宽度不能做的太宽,在运种情况下只有通过减小沟道长度来增大宽长比,但是薄膜晶体管沟道长度降低到一定程度会引起漏电流和沟道击穿等现象,造成薄膜晶体管无法工作。 According to the above if you want to increase the aspect ratio of width to length ratio is increased, by increasing the channel width W or channel length is reduced to achieve the purpose of increasing the width to length ratio, and in order to ensure the resolution of the display screen, the pixel region an area as small as possible, and the opening ratio as large as possible, i.e., the driving thin film transistor and a peripheral circuit W can not exceed a certain area, determines the transport channel width of the thin film transistor can not be made too wide, in operation species when only the channel length is increased by reducing the aspect ratio, but the thin film transistor channel length is reduced to a certain extent and the channel leakage current can cause a breakdown phenomenon, resulting in a thin film transistor does not work. 因此,如何在保证器件正常工作的前提下,增大沟道的宽长比,为本领域技术人员致力研究的方向。 Therefore, how to ensure proper operation under the premise of increasing the channel width to length ratio, the person skilled in the direction of research efforts.

[0008] 中国专利(CN102437196A)公开了一种低溫多晶娃薄膜晶体管及其制造方法,所述低溫多晶娃薄膜晶体管包括栅极、源极和漏极,所述源极和漏极之间有沟道隔开,所述栅极和源极、漏极之间形成有多晶娃娃岛图形,其中,所述沟道处的多晶娃娃岛图形上至少有一个凹槽从而形成立体沟道,所述凹槽的深度小于沟道的深度。 [0008] Chinese Patent (CN102437196A) discloses a low-temperature polycrystalline thin film transistor and a manufacturing method of the baby, the baby low-temperature polycrystalline thin film transistor including a gate, a source and a drain, said source and drain between the there spaced channel, the gate and the source, the polycrystalline doll formed between the drain of the island pattern, wherein the channel has at least one groove on the pattern of the polycrystalline islands to form a three-dimensional channel doll depth of the groove is less than the depth of the channel. 本发明提供的低溫多晶娃薄膜晶体管,通过衍射曝光在沟道处的多晶娃娃岛图形上形成立体沟道,有效增大沟道宽度, 从而增大薄膜晶体管的宽长比和开口率。 Low-temperature polycrystalline thin film transistor of the present invention provides a baby, the three-dimensional channel is formed by exposure on the polycrystalline diffraction doll island pattern at the channel, the effective channel width is increased, thereby increasing the aperture ratio and the aspect ratio of the thin film transistor.

[0009] 该专利是通过在衍射和干法刻蚀在娃岛图形上形成沟槽,从而增大了娃岛的表面积,从而增加沟道宽度。 [0009] This patent is a diffraction grooves are formed and dry etching pattern on the baby by the island, thereby increasing the surface area of ​​the baby island, thereby increasing the channel width. 此方法虽然可W增加沟道宽度,但是由于采用了干法刻蚀,很大程度上对化annel (沟道)表面造成损伤,必然引起V化(平带电压)的变化,从而影响Vth (临界电压)值,影响器件的性能。 Although this method can increase the channel width W, but due to the dry etching, to a large extent of Annel (channel) surface damage, inevitably lead to a change of V (flat band voltage), thus affecting Vth ( threshold voltage) value, affecting the performance of the device.

[0010] 中国专利(CN1971390A)公开了一种TFT LCD像素结构,其将环形或多边形的TFT 器件设计到栅线(GAT巧上,最重要的是将像素的过孔(VIA册L巧部分也设计到栅线上,此种设计可W在不降低开口率的情况下增加沟道的宽长比(W/L),提高开态电流(Ion),最重要的是可W对目前彩膜(〇)L0R FILTER)所采用的柱形隔垫物(P巧起到一定的限制作用。 [0010] Chinese patent (CN1971390A) discloses a TFT LCD pixel structure, which ring TFT device or polygonal design to the gate line (the GAT Qiao, the most important is the vias (VIA L volumes pixel portion is also clever design of the gate lines, this design can increase the width W of a channel length ratio (W / L), to improve the on-state current (the Ion) without reducing the aperture ratio, the most important is the current color filter W (square) L0R FILTER) employed a cylindrical spacer (P clever play a limited role.

[0011] 该专利是通过将像素的过孔部分也设计到栅线上,进而增加宽长比,提高开态电流,但是该专利的工艺步骤比较复杂,实现难度较大,因此在实际的应用中受到了一定的限制。 [0011] This patent is formed by a pixel portion is also designed to bore through the gate line, thereby increasing the width to length ratio, to improve the on-state current, this patent process step complicated, difficult to achieve, so in practical application It is subject to certain restrictions.

发明内容 SUMMARY

[0012] 本发明提供了一种低溫多晶娃TFT器件及其制造方法,在保证器件性能的前提下,有效地增加了沟道的宽长比,提高开态电流,进而提升了TFT电路的驱动能力。 [0012] The present invention provides a low-temperature polycrystalline TFT device and a method for manufacturing baby, to ensure device performance under the premise, effectively increases the width to length ratio of the channel, to improve on-state current, thereby improving the TFT circuits Drive capability.

[0013] 本发明采用的技术方案为: [0013] aspect of the present invention is used are:

[0014] 一种低溫多晶娃TFT器件的制造方法,其中,包括W下步骤: [0014] A method of manufacturing a low-temperature polycrystalline baby TFT device, wherein, W comprises the steps of:

[0015] 步骤S1、提供一半导体衬底,于所述半导体衬底的表面依次沉积一衬垫层和一介质层; [0015] In step S1, the providing a semiconductor substrate, a surface of the semiconductor substrate, sequentially depositing a liner layer and a dielectric layer;

[0016] 步骤S2、刻蚀所述介质层形成位于所述衬垫层之上的凸起图形,刻蚀停止在所述衬垫层上表面; [0016] Step S2, the projection etching the pattern dielectric layer is formed above said spacer layer, the etch stop surface on the backing layer;

[0017] 步骤S3、沉积一非晶娃层覆盖在所述凸起图形和衬垫层上方,并将所述凸起图形的侧壁予W覆盖,并将所述非晶娃层转化为多晶娃层; [0017] Step S3, the baby depositing an amorphous covering layer covering the projections to W and the backing layer over the pattern, the projection pattern and a sidewall, and the amorphous layer into a Multi-Wa baby crystal layer;

[0018] 步骤S4、刻蚀所述多晶娃层形成一有源区,所述有源区覆盖在所述凸起图形顶部上表面的至少局部区域及覆盖在凸起图形的至少一个侧壁上; [0018] step S4, baby etching the polycrystalline layer forming an active region, the active region overlying the at least one sidewall of the projection pattern at least partially in the region of the projections and the cover on top of the surface pattern on;

[0019] 步骤S5、于所述衬垫层和有源区上方依次形成一绝缘层和一栅极材料层; [0019] In step S5, and the backing layer are sequentially formed on the active region above an insulating layer and a gate material layer;

[0020] 步骤S6、刻蚀所述绝缘层和所述栅极材料层形成一栅极及位于该栅极下方的栅绝缘层; [0020] Step S6, the etching the insulating layer and the gate material and the gate layer forming a gate insulating layer located below the gate electrode;

[0021] 其中,所述栅极和栅绝缘层的叠层至少具有交叠在有源区的一沟道区上方的堆找式栅极,W及有源区的一源极区及一漏极区分别位于沟道区的两侧。 [0021] wherein, the gate insulating layer and a gate stack having at least a channel region above the overlapping region of the stack to find the active gates, W, and the active region of a source region and a drain region on each side of the channel region.

[0022] 上述的方法,其中,所述步骤S2中于所述衬垫层之上形成至少一个所述凸起图形。 [0022] The above method, wherein the step S2, the backing layer is formed over at least one of the protrusion pattern.

[0023] 上述的方法,其中,所述有源区完全覆盖所述凸起图形的顶部上表面及两侧侧壁的表面。 [0023] The above method, wherein the active region completely cover the surface of both side surfaces and on the top of the raised pattern.

[0024] 上述的方法,其中,所述有源区覆盖所述凸起图形部分上表面及位于该部分上表面同侧的侧壁的表面。 [0024] In the above method, wherein the active region to cover the convex surface of the upper surface and the pattern portion located on the sidewall portion of the surface of the same side.

[00巧]上述的方法,其中,所述有源区覆盖靠近所述凸起图形至少一侧侧壁的衬垫层部分上表面。 [Qiao 00] above method, wherein the active region covering the upper surface of the pad portion of the protrusion pattern layer adjacent to at least one side of the sidewall.

[00%] 上述的方法,其中,步骤S1中采用等离子增强化学气相沉积工艺分别沉积形成所述衬垫层及介质层,沉积的溫度为400~450°C,所述衬垫层厚度为400~500埃,所述介质层厚度为2000~2500埃。 [00%] above, wherein, in step S1, using plasma enhanced chemical vapor deposition process, depositing respectively formed in the backing layer and the dielectric layer, deposition temperature of 400 ~ 450 ° C, the backing layer having a thickness of 400 to 500 angstroms, said dielectric layer having a thickness of 2000 to 2500 angstroms.

[0027] 上述的方法,其中,所述衬垫层为氮化娃层,所述介质层为二氧化娃层。 [0027] The above method, wherein the backing layer is a nitride layer baby, the baby dioxide dielectric layer is a layer.

[0028] 上述的方法,其中,所述凸起图形的高度为400~600埃,所述凸起图两侧侧壁与所述衬垫层之间的角度为40°~60°。 [0028] The above method, wherein the height of the relief pattern of 400 to 600 Å, the angle between the sides of the raised side walls and the backing layer of FIG. 40 ° ~ 60 °.

[0029] 上述的方法,其中,采用化学气相沉积工艺沉积所述非晶娃层,沉积的溫度为400~500°C,沉积所述非晶娃层的厚度为400~500埃。 [0029] The above method, wherein the chemical vapor deposition process for depositing the amorphous layer baby, the deposition temperature is 400 ~ 500 ° C, the thickness of the deposited layer is amorphous baby 400 to 500 angstroms.

[0030] 上述的方法,其中,所述步骤S3中采用激光退火工艺将所述非晶娃层转化为多晶娃层。 [0030] The above method, wherein, in the step S3, the process of laser annealing the amorphous layer into a polycrystalline baby doll layer.

[0031] 上述的方法,其中,采用化学气相沉积工艺沉积所述绝缘层,且所述绝缘层包括二氧化娃层及覆盖于该二氧化娃层之上的氮化娃层。 [0031] The above method, wherein, using a chemical vapor deposition process of the insulating layer and the insulating layer comprises oxide layer and a baby doll dioxide overlying layer of nitride layer baby.

[0032] 上述的方法,其中,采用物理气相沉积工艺沉积所述栅极材料层,所述栅极材料层材质为钢,形成的所述栅极厚度为2000~3000埃。 [0032] The above method, wherein the physical vapor deposition process for depositing the layer of gate material, the gate material layer is made of steel, formed in a thickness of the gate 2000 to 3000 angstroms.

[0033] 一种低溫多晶娃TFT器件,其中,所述器件包括一半导体衬底,所述衬底之上覆盖有一衬垫层,W及位于该衬垫层之上形成有凸起图形, [0033] A low-temperature polycrystalline baby TFT device, wherein the device comprises a semiconductor substrate, over the substrate layer is covered with a pad, W, and located in a protrusion pattern is formed on the spacer layer,

[0034] 一有源区覆盖在所述凸起图形顶部上表面的至少局部区域及覆盖在凸起图形的至少一个侧壁上. [0034] an active region overlying the raised pattern on the top surface of the cover and at least a partial region on at least one side wall of the protrusion pattern.

[0035] 所述TFT器件还包括一栅极及位于该栅极下方的栅绝缘层,W及有源区的一源极区及一漏极区分别位于沟道区的两侧; [0035] The TFT device further comprises a gate electrode and a gate located below the gate insulating layer, a source region W and the active region and a drain region respectively located on both sides of the channel region;

[0036] 其中,所述栅极与所述栅绝缘层之间形成有一叠层,且该叠层至少具有交叠在有源区上的堆找式栅极,所述堆找式栅极位于一沟道区的上方。 [0036] wherein a laminate is formed between the gate and the gate insulating layer, and the laminate having at least on the active region overlapping stack looking gates, gates located in the stack to find above a channel region.

[0037] 上述的器件,其中,所述基底之上形成有至少一个凸起图形。 [0037] The above-described device, wherein said substrate is formed over at least one projection pattern.

[0038] 上述的器件,其中,所述有源区覆盖所述凸起图形的全部上表面及两侧侧壁的表面,W及覆盖相邻凸起图形之间的衬垫层暴露的上表面。 [0038] The above-described device, wherein said active region to cover the entire upper surface of said projection pattern and of both side surfaces, W, and covering the cushion layer between adjacent raised pattern exposed .

[0039] 上述的器件,其中,所述有源区覆盖所述凸起图形部分上表面及位于该部分上表面同侧的侧壁表面。 [0039] The above-described device, wherein said active region overlying the convex portion of the surface of the sidewall surface of the same side of the upper surface and the pattern portion located.

[0040] 上述的方法,其中,所述有源区覆盖靠近所述凸起图形至少一侧侧壁的衬垫层部分上表面。 [0040] The above method, wherein the active region covering the upper surface of the pad portion of the protrusion pattern layer adjacent to at least one side of the sidewall.

[0041] 上述的TFT器件,其中,所述衬垫层为氮化娃层,所述氮化娃层厚度为400~500 埃。 [0041] The TFT devices, wherein the backing layer is a nitride layer baby, the baby nitride layer thickness of 400 to 500 angstroms.

[0042] 上述的TFT器件,其中,所述凸起图形材质为二氧化娃,所述凸起图形高度为400~600埃,且该凸起图两侧侧壁与所述衬垫层之间的角度为40°~60°。 [0042] The TFT devices, wherein the relief pattern is made of baby dioxide, the height of the relief pattern of 400 to 600 angstroms, between the two sides of the sidewall of FIG projection and the liner layer an angle of 40 ° ~ 60 °.

[0043] 上述的TFT器件,其中,所述栅绝缘层自下而上依次包括二氧化娃层和氮化娃层, 所述二氧化娃层厚度为400~500埃,所述氮化娃层厚度为700~800埃。 [0043] The TFT devices, wherein the gate insulating layer includes, in order from bottom to top baby dioxide layer and a nitride layer baby, baby dioxide layer thickness of 400 to 500 angstroms, the nitride layer baby a thickness of 700 to 800 angstroms.

[0044] 上述的TFT器件,其中,所述栅极厚度为2000~3000埃,所述栅极材质为钢。 [0044] The TFT devices, wherein the gate electrode 2000 to a thickness of 3000 angstroms, the gate electrode is made of steel.

[0045] 由于本发明采用了W上技术方案,通过在衬垫层上方制备至少一个立体的凸起图形,然后继续进行后续的制备工艺形成沟道和金属栅极。 [0045] Since the present invention adopts the technical scheme W, through a perspective projection pattern at least over the cushion layer was prepared, and then proceed with the subsequent process of forming the prepared channel and metal gate. 在不增加投影面积的前提下,有效的增加了沟道的宽度,进而增大了沟道的宽长比,提升了TFT驱动电路的开态电流,进而有利于提升器件的性能。 Without increasing the projected area of ​​the premise, effectively increasing the width of the channel, and thus increases the width to length ratio of the channel to enhance the on-state current of the TFT driving circuit, and further boost the performance of the device.

附图说明 BRIEF DESCRIPTION

[0046] 通过阅读参照W下附图对非限制性实施例所作的详细描述,本发明及其特征、外形和优点将会变得更明显。 [0046] W by reading the detailed description with reference to non-limiting embodiments of the present invention and its features, shape, and advantages will become more apparent. 在全部附图中相同的标记指示相同的部分。 The same numerals indicate like parts throughout the drawings. 并未刻意按照比例绘制附图,重点在于示出本发明的主旨。 The drawings are deliberately not to scale, emphasis being placed upon illustrating the gist of the present invention.

[0047] 图1为现有技术中TFT结构的截面图; W4引图2为为现有技术TFT结构的平面图; [0047] FIG. 1 is a sectional view of a prior art TFT structure; W4 of the lead 2 is a plan view of the prior art TFT structure;

[0049] 图3为本发明沉积衬垫层和介质层后的截面图; [0049] FIG. 3 is deposited liner layer and the dielectric layer is a cross-sectional view of the present invention;

[0050] 图4为本发明刻蚀介质层形成凸起图形后的截面图; [0050] FIG 4 is etched dielectric layer is formed a cross-sectional view of the projection pattern of the present invention;

[0051] 图5为本发明沉积非晶娃层后的示意图; [0051] FIG. 5 is a schematic rear baby amorphous layer deposition of the present invention;

[0052] 图6为本发明将非晶娃层转化为多晶娃层后并刻蚀形成有源区后的截面图; [0052] FIG. 6 of the present invention, an amorphous layer into a polycrystalline baby doll rear layer and a cross-sectional view of the etched to form an active region;

[0053] 图7为本发明形成金属栅后的示意图; [0053] FIG. 7 is a schematic view of the present invention, a metal gate is formed;

[0054] 图8为本申请形成的TFT器件与现有技术中TFT器件的对比图; 阳化5] 图9为本申请在衬垫层上形成两个凸起图形的TFT器件截面图; [0054] FIG. 8 of the present application is formed of TFT devices in comparison with the prior art device of FIG TFT; yang 5] FIG. 9 is a sectional view of the TFT device to apply two convex pattern formed on the backing layer;

[0056] 图10为本发明的有源区部分覆盖于凸起图形之上的TFT器件截面图。 [0056] FIG active region portion 10 of the present invention covers the TFT device on top sectional view of the projection pattern.

具体实施方式 Detailed ways

[0057] 下面结合附图对本发明的具体实施方式作进一步的说明: [0057] DETAILED DESCRIPTION OF THE DRAWINGS Embodiment of the present invention will be further described:

[0058] 本发明提供了一种低溫多晶娃TFT制备方法,图3-8所示为本发明一种低溫多晶娃TFT制备方法的流程图,包括W下步骤: [0058] The present invention provides a method of preparing low-temperature, low-temperature polycrystalline baby flowchart of a method of manufacturing a TFT of the present invention is shown in FIG. 3-8 polycrystalline TFT baby, W comprising the steps of:

[0059] 步骤S1、首先提供一半导体衬底1,采用等离子增强化学气相沉积工艺在衬底表面自下而上沉积一衬垫层2和介质层6,在沉积过程中,沉积的溫度为400~450°C巧曰400°C,420°C,450°C )。 [0059] step S1, a first providing a semiconductor substrate 1 by plasma enhanced chemical vapor deposition process on the substrate surface is deposited a bottom-up backing layer 2 and the dielectric layer 6, in the deposition process, the deposition temperature is 400 said coincidence ~ 450 ° C 400 ° C, 420 ° C, 450 ° C). 其中,衬垫层厚度为400~500埃巧日400埃,430埃,450埃,480埃, 500埃),介质层6厚度为2000~2500埃(如2000埃,2200埃,2400埃,2500埃)。 Wherein the liner layer having a thickness of 500 Å - 400 Å 400 days Qiao, 430 Å, 450 Å, 480 Å, 500 Å), the thickness of the dielectric layer 6 of 2000 to 2500 angstroms (e.g., 2000 Å, 2200 Å, 2400 Å, 2500 Egypt). 优选的, 该衬垫层2材质为氮化娃层(Si化),介质层6材质为Si02,形成图3所示结构。 Preferably, the backing layer 2 is made of a nitride layer Wa (Si based), a dielectric layer 6 made of Si02, 3 form the structure shown in FIG. 在现有技术中,一般采用Si化、有机物或金属作为介质层,但是本领域技术人员发现:由于Si化与多晶娃层晶格匹配性差,如果与沟道层直接接触,在接触面引起不稳定现象,所W不能选用Si化作为介质层;而有机物的耐热性较差,在后续工艺中一旦遇到高溫情况巧日CVD、PECVD)容易产生粉尘,进而造成污染,对生产造成影响;而金属材料由于其导热性好,受热后溫度上升较快,进而可能会影响后续的ELA (Excimer Laser Annealing准分子雷射退火技术)制程,可能由于升溫较快导致多晶娃结晶性变差,影响电子迁移率,影响器件性能。 In the prior art, generally employed of Si, metal, or as an organic dielectric layer, those skilled in the art will find: Due to poor lattice matching of the Si polycrystalline layer baby, if the direct contact with the channel layer, causing the contact surface instability, W can not use the Si of a dielectric layer; the organics poor heat resistance, high temperature event of coincidence date CVD, PECVD) prone to dust in a subsequent process, and cause pollution, impact on production ; and a metal material because of its good thermal conductivity, the temperature rises rapidly heated, and thus may affect subsequent ELA (excimer Laser annealing excimer laser annealing) process, since heating may result in rapid deterioration of the crystalline polymorph baby affect electron mobility, affect device performance. 因此,优选的,本发明采用Si化作为介质层6为最佳技术方案。 Thus, preferably, the present invention is employed as the dielectric layer 6 of Si is the best technical solution.

[0060] 步骤S2、采用光刻工艺并结合干法刻蚀去除部分介质层6,在衬垫层2上形成至少一个凸起图形6'(凸起图形的数量根据工艺需求而设定)。 [0060] Step S2, the combined use of a photolithography process and dry etching removing portions of dielectric layer 6, a projection pattern formed of at least 6 '(the number of convex pattern set in accordance with process requirements) on the backing layer 2. 如图4所示,该凸起图形高度为400~600埃巧日400埃,500埃,550埃,600埃等),两侧侧壁与衬垫层之间的角度为40。 4, the height of the projection pattern 400 to 600 angstroms 400 angstroms Qiao day, 500 Å, 550 Å, 600 Å, etc.), and the angle between the sides of the sidewall spacer layer 40. ~ 60°巧日40°,50°,60°等)。 Qiao days ~ 60 ° 40 °, 50 °, 60 °, etc.). 在本发明的实际应用过程中,可通过调整光刻及干法刻蚀的反应条件来控制凸起图形6'的形貌。 In practical application process of the present invention, a protrusion pattern may be controlled morphology 6 'by adjusting the reaction conditions photolithography and dry etching.

[0061] 步骤S3、沉积一非晶娃层覆盖在凸起图形6'和衬垫层2上方,并将所述凸起图形6'的侧壁予W覆盖。 [0061] Step S3, the baby depositing an amorphous layer overlying the convex pattern 6 'and the upper backing layer 2, and the protrusion pattern 6' to W sidewall coverage. 其中,沉积的溫度为400~500°C巧日400°C,45(rC,50(rC等),沉积非晶娃层的厚度为400~500埃巧日400埃,450埃,500埃等);然后进行激光退火工艺,将非晶娃层转化为多晶娃层7,如图5所示。 Wherein the deposition temperature is 400 ~ 500 ° C Qiao day 400 ° C, 45 (rC, 50 (rC, etc.), the thickness of the baby depositing an amorphous layer is 400 to 500 angstroms 400 angstroms Qiao day, 450 Å, 500 Å, etc. ); followed by a laser annealing process, an amorphous layer into a baby doll polycrystalline layer 7, as shown in FIG.

[0062] 步骤S4、刻蚀多晶娃层7形成一有源区7',有源区7'覆盖在凸起图形6'顶部上表面的至少局部区域及覆盖在凸起图形的至少一个侧壁上,如图6所示。 [0062] Step S4, the baby etching the polycrystalline layer 7 is formed an active region 7 ', the active region 7' ​​cover at least one side protrusion pattern 6 'is at least partially covers the upper region and the top surface of the protrusion pattern walls, as shown in FIG.

[0063] 步骤S5、于衬垫层2和有源区7'上方依次形成一绝缘层和一栅极材料层。 [0063] step S5, on the backing layer 2 and the active region 7 'are sequentially formed over an insulating layer and a gate material layer. 其中, 采用化学气相沉积工艺自下而上依次沉积Si化层和一Si化层共同构成该绝缘层。 Wherein, using a chemical vapor deposition process from bottom to top Si layer and a deposited Si layer together constituting the insulating layer. 其中,沉积的溫度为400~500°C巧日400°C,450°C,500°C等),沉积Si〇2层的厚度为400~500埃(如400埃,450埃,500埃等),沉积Si化层的厚度为700~800埃(700埃,730埃,780埃, 800埃等)。 Wherein the deposition temperature is 400 ~ 500 ° C Qiao day 400 ° C, 450 ° C, 500 ° C, etc.), the thickness of the deposited layer Si〇2 400 to 500 angstroms (e.g., 400 Å, 450 Å, 500 Å, etc. ), the thickness of the deposited Si layer 700 to 800 Å (700 angstroms, 730 angstroms, 780 angstroms, 800 angstroms and the like). 在沉积形成栅绝缘层后,再采用物理气相沉积工艺沉积一材质为钢的栅极材料层覆盖栅绝缘层的上表面,形成的栅极材料层厚度为2000~3000埃设日2000埃,2500埃, 3000埃)等。 After deposition of the gate insulating layer is formed, and then a physical vapor deposition process using a material for the gate electrode material layer on the surface of steel to cover the gate insulating layer, the gate material layer formed in a thickness of 2000 Angstroms to 3000 Angstroms disposed Day 2000, 2500 angstrom, 3000 angstrom) and so on.

[0064] 步骤S6、刻蚀绝缘层和栅极材料层形成一栅极9及位于该栅极下方的栅绝缘层8 ; 其中,该栅极9和栅绝缘层8的叠层至少具有交叠在有源区的一沟道区上方的堆找式栅极, 同时该有源区的一源极区及一漏极区分别位于沟道区的两侧(图中未标出)。 [0064] Step S6, the gate electrode 9 and a gate insulating layer located below the gate electrode 8 and the gate insulating layer etching the material layer; wherein the laminated gate electrode 9 and the gate insulating layer overlapping with at least 8 Get gates in a stack over the channel region of the active region, while a source region of the active region and a drain region respectively located on both sides of the channel region (not shown in the figure). 如图7所示。 As shown in FIG. 本发明通过在衬垫层上制备一立体的凸起图形,然后在其上方形成沟道,可在保证衬底投影面积不变的前提下,有效增加沟道的宽度,进而扩大沟道的宽长比,提升开态电流。 The present invention is prepared by a broad perspective projection pattern on the backing layer, then a channel is formed above it, it can be guaranteed in the projected area of ​​the substrate without changing the effective width of the channel increases, thereby expanding the channel longer than, enhance on-state current. W65] 图8A为现有技术低溫多晶娃TFT器件的截面图,图8B为本发明提供的一种低溫多晶娃TFT器件的截面图,结合图8A和图8B可显而易见得出,本发明形成的有源区7'是位于凸起图形6'的顶部上表面和两侧侧壁及靠近两侧侧壁的部分衬垫层上表面,其沟道宽度明显长于图8A所示的沟道宽度,同时两者的沟道长度相同,由此可见,本发明在不增加衬底投影面积的情况下,通过制备一凸起图形6'后然后在其上形成沟道,可增大沟道宽度,由于沟道宽度得W增加,所W沟道的宽长比也会相应增大,进而提升了开态电流Ion,提高了TFT器件的驱动能力及器件性能。 W65] FIG. 8A is a prior art sectional view of a low-temperature polycrystalline baby TFT device, FIG. 8B a cross-sectional view of a low-temperature polycrystalline baby TFT device provided by the present invention in conjunction with FIGS. 8A and 8B may be derived apparent, the present invention forming an active region 7 'is located in a protrusion pattern 6' and the upper surface and both side wall portions of the liner layer adjacent the top surface of the lateral walls, which is significantly longer than the channel width of the channel as shown in FIG. 8A width, the same length of the channel between the two, we can see, in the present invention without increasing the projected area of ​​the substrate, by preparing a rear projection pattern 6 'is then formed on a channel, the channel can be increased width, obtained due to the increased channel width W, W is a channel width to length ratio will increase accordingly, and thus enhance the on-state current Ion, and to improve the driving capability of the device performance of the TFT device.

[0066] 实施例一: [0066] Example a:

[0067] 本发明还提供了一种低溫多晶娃TFT器件,如图7所示,该器件包括半导体衬底1和位于该衬底1之上的衬垫2,优选的,该衬垫层2厚度为400~500埃。 [0067] The present invention also provides a low-temperature polycrystalline baby TFT device, shown in Figure 7, the device includes a semiconductor substrate 1 and positioned above the substrate pad 1 2, preferably, the liner layer 2 having a thickness of 400 to 500 angstroms. 衬垫层2之上形成有凸起图形6',凸起图形6'为沉积Si〇2并刻蚀形成。 The backing layer 2 is formed on a protrusion pattern 6 ', the projection pattern 6' is deposited and etched to form Si〇2. 其中,该凸起图形6'高度为400~600埃巧日400埃,450埃,500埃,550埃,600埃等),两侧侧壁与衬垫层之间的角度为40° ~60。 Wherein the projection pattern 6 'height is 400 to 600 angstroms 400 angstroms day Qiao,), and the angle between the sides of the sidewall spacer layer 450 angstroms, 500 angstroms, 550 angstroms, 600 angstroms and the like is 40 ° ~ 60 . (如40。,50°,60° 等); (E.g., 40., 50 °, 60 °, etc.);

[0068] 一有源区7'覆盖在凸起图形6'顶部上表面的至少局部区域及覆盖在凸起图形的至少一个侧壁上. [0068] an active region 7 'cover the convex pattern 6' is at least partially covers the upper region and a top surface on at least one side wall of the protrusion pattern.

[0069] 同时,该TFT器件还包括一栅极9及位于该栅极下方的栅绝缘层8,该栅极9和栅绝缘层8的叠层至少具有交叠在有源区的一沟道区上方的堆找式栅极,W及有源区的一源极区及一漏极区分别位于沟道区的两侧。 [0069] Meanwhile, the TFT device further comprises a gate electrode 9 and the gate insulating layer located below the gate electrode 8, the gate stack insulating layer 8 and the gate 9 having at least a region overlapping the active channel the region above the stack looking gates, W, and a source region and a drain region of the active region located on both sides of the channel region.

[0070] 下面结合图8来对本发明的优点进行进一步阐述,结合图8A和图8B可显而易见得出,本发明在衬垫层2上方形成有凸起图形6',然后形成沟道,本发明形成的有源区7' 覆盖凸起图形6'的上表面及两个侧壁和靠近侧壁暴露的部分衬垫层上表面,而现有技术中的有源区3仅仅覆盖在衬底1上表面。 [0070] below with reference to FIG. 8 to further illustrate the merits of the present invention, in conjunction with FIGS. 8A and 8B may be derived apparent, the present invention is formed over the liner layer 2 with a protrusion pattern 6 ', then a channel is formed, the present invention forming an active region 7 'of the cover protrusion pattern 6' on the upper surface and two side walls and side wall portions of the liner layer adjacent the exposed surfaces, but the prior art only covers the active region 3 in the substrate 1 on the surface. 根据附图可显而易见得出,本发明在不增加衬底投影面积的情况下(即不改变沟道长度),通过制备一凸起图形6'后然后在其上形成沟道, 可增大沟道宽度。 The drawings will be apparent drawn, in the present invention without increasing the projected area of ​​the substrate (i.e., without changing the channel length), prepared by a protrusion pattern 6 'Then a channel is formed thereon, the groove can be increased track width. 由于沟道宽度得W增加,所W其宽长比也会相应增大,进而提升了开态电流Ion,提高了TFT器件的驱动能力及器件性能。 Obtained due to the increased channel width W, which is the width to length ratio W increases accordingly, thereby improving the on-state current Ion, and to improve the driving capability of the device performance of the TFT device. 阳0川实施例二 Second Embodiment River male 0

[0072] 在实际应用中,通过采用特定规格的遮光罩进行曝光显影并刻蚀介质层后,在衬垫层2上方形成多个凸起图形,如图9所示,衬垫层2上形成有两个立体的凸起图形6 ',刻蚀形成的有源区将凸起图形的顶部上表面及两侧侧壁的表面全部予W覆盖,同时该有源区还将靠近凸起图形一侧侧壁的衬垫层暴露的上表面及相邻两个凸起图形之间暴露的衬垫层上表面予W覆盖。 [0072] In practical applications, after exposure and development by using a particular hood specification and etched dielectric layer, a plurality of projections are formed over the pad layer pattern 2, as shown in FIG, 29 is formed on the liner layer two perspective projection pattern 6 ', formed by etching the active region surface and a convex surface on the top of both side W to cover the entire pattern, while the active area also near a protrusion pattern side side wall of the backing layer and the exposed upper surface of two adjacent projections on the liner layer to the exposed surface of the pattern between W covered. 由于凸起图形6'具有一定高度,其上方的有源区不仅包括覆盖凸起图形顶部及部分暴露的衬垫层,同时还覆盖凸起图形两侧的侧壁,所W其沟道宽度势必有所增加,在不影响投影面积的情况下而增加了沟道宽度,提升了沟道的宽长比,提高了开态电流Ion,进而提高了TFT器件的驱动能力和器件性能。 Since the protrusion pattern 6 'having a height, above the active region which includes not only the top cover protrusion pattern layer and the exposed portions of the pad, and also covers the sidewalls of the raised pattern on both sides of, the channel width W which is bound increased, without affecting the projected area increases the channel width, the channel width to length ratio improved to improve the on-state current Ion, thereby improving the driving capability of the TFT device and device performance. 本发明在衬垫层上形成的凸起图形可根据工艺需求而设定,不仅仅局限于两个凸起图形6',在实际应用过程中可制备形成一个、两个或者两个W上的娃岛图形都可起到增加沟道宽长比的效果,在此不再寶述。 The present invention is a protrusion pattern formed on the liner layer may be set according to process requirements, not limited to two convex pattern 6 ', may be prepared in the practical application process is formed on one, two or two of W baby island pattern may serve to increase the effect of channel width to length ratio, which is not described treasure. 阳〇7引实施例S Yang cited 〇7 Example S

[0074] 在本发明的又一实施例中,通过控制不同的刻蚀反应条件对多晶娃层进行刻蚀形成具有不同形状的有源区,使有源区7'部分覆盖凸起图形的表面及衬垫层的上表面,如图10所示,有源区7'覆盖于凸起图形6'部分顶面的上置部分和覆盖在凸起图形一侧侧壁上的侧翼部分,W及靠近凸起图形一侧侧壁的部分衬垫层上表面。 [0074] In a further embodiment of the present invention, it is formed by etching the active region having different shapes of baby polycrystalline layer by controlling the etching of different reaction conditions, the active region 7 'of the portion covering the protrusion pattern surface of the upper surface and the spacer layer 10, the active region 7 'cover the convex pattern 6' on the opposite face of the top portion and the cover portion on the side wall side of the side wing portion protrusion pattern, W and upper portions of the pad protrusion pattern layer near the side surface of the sidewall. 进而可得到区别于图7 和图9不同的沟道宽度,实现不同的宽长比,可满足不同的器件需要不同的宽长比的需求。 FIGS. 7 and obtained further distinguished from 9 different channel widths to achieve different width to length ratio, the device may need to meet different needs of different width to length ratio. [00巧]综上所述,由于本发明采用了W上技术方案,通过在衬底上预先沉积一衬垫层,然后在该衬垫层上制备形成凸起图形,然后制备一有源区覆盖在凸起图形顶部上表面的至少局部区域及覆盖在凸起图形的至少一个侧壁上,然后进行后续的制备工艺。 [Qiao 00] As described above, since the present invention adopts the technical scheme W, previously deposited on the substrate by a backing layer, then the projection pattern is formed on the prepared backing layer, an active region is then prepared and a cover at least partially covering a surface area of ​​at least one sidewall of the projection pattern, and then subsequent manufacturing process on top of the protrusion pattern. 本发明通过在衬垫层上制备形成立体的凸起图形,然后在其上方形成沟道,在不改变投影面积的同时,可有效增加沟道宽度,进而增大了沟道的宽长比,提高了开态电流Ion,进而提升了TFT器件的驱动能力及器件性能。 The present invention is prepared by a perspective projection pattern formed on the backing layer, then a channel is formed above it, without changing the projected area at the same time, can effectively increase the channel width, thereby increasing the width to length ratio of the channel, improve the on-state current Ion, thereby enhancing the drive capability and device performance of the TFT device.

[0076] W上对本发明的较佳实施例进行了描述。 [0076] W of the preferred embodiments of the invention have been described. 需要理解的是,本发明并不局限于上述特定实施方式,其中未尽详细描述的设备和结构应该理解为用本领域中的普通方式予W实施;任何熟悉本领域的技术人员,在不脱离本发明技术方案范围情况下,都可利用上述掲示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰,或修改为等同变化的等效实施例,运并不影响本发明的实质内容。 Is to be understood that the present invention is not limited to the specific embodiments, wherein the unfinished device and the structure should be understood that the detailed description of the embodiment with the W to those skilled in the normal way; any skilled in the art, without departing from the under the technical scope of the present invention, it can be shown using the methods and techniques kei content that many possible variations and modifications to the technical solutions of the present invention, the equivalent changes or modifications to equivalent embodiments, not affect the substance of the operation of the present invention . 因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对W上实施例所做的任何简单修改、等同变化及修饰,均仍属于本发明技术方案保护的范围内。 Thus, all without departing from the technical solutions of the present invention, any simple modification based on the technical essence of the present invention is made to Example W, equivalent variations and modifications, provided they fall within the scope of protection of the present invention.

Claims (21)

1. 一种低温多晶硅TFT器件的制造方法,包括以下步骤: 步骤S1、提供一半导体衬底,于所述半导体衬底的表面依次沉积一衬垫层和一介质层; 步骤S2、刻蚀所述介质层形成位于所述衬垫层之上的凸起图形,刻蚀停止在所述衬垫层上表面; 步骤S3、沉积一非晶硅层覆盖在所述凸起图形和衬垫层上方,并将所述凸起图形的侧壁予以覆盖,并将所述非晶硅层转化为多晶硅层; 步骤S4、刻蚀所述多晶硅层形成一有源区,所述有源区覆盖在所述凸起图形顶部上表面的至少局部区域及覆盖在凸起图形的至少一个侧壁上; 步骤S5、于所述衬垫层和有源区上方依次形成一绝缘层和一栅极材料层; 步骤S6、刻蚀所述绝缘层和所述栅极材料层形成一栅极及位于该栅极下方的栅绝缘层; 其中,所述栅极和栅绝缘层的叠层至少具有交叠在有源区的一沟道区上方的堆栈式栅极 1. A method for producing a low temperature polysilicon TFT device, comprising the steps of: step S1, the providing a semiconductor substrate, the surface of the semiconductor substrate, sequentially depositing a liner layer and a dielectric layer; step S2, the etching said dielectric layer is formed above said liner protrusion pattern layer, etch stop surface on the backing layer; step S3, the depositing an amorphous silicon layer overlying the backing layer and the upper protrusion pattern and the relief pattern of the side wall to be covered, and the amorphous silicon layer into a polysilicon layer; step S4, etching the polysilicon layer forming an active region, the active region being covered on top of said projection pattern at least partially covering the surface region and at least one side wall of the protrusion pattern; step S5, in the upper region of the pad and the active layer are sequentially formed an insulating layer and a gate material layer; step S6, the etching the insulating layer and the gate material and the gate layer forming a gate insulating layer located below the gate electrode; wherein said gate insulating layer and a gate stack having at least overlap with a the gate stacked above the channel region of a source region ,以及有源区的一源极区及一漏极区分别位于沟道区的两侧,且所述凸起图形增大所述沟道区宽度的同时不改变该沟道区的长度。 And a source region and a drain region of the active region located on both sides of the channel region, and said projection pattern width of the channel region is increased without changing the length of the channel region.
2. 如权利要求1所述的方法,其特征在于,所述步骤S2中于所述衬垫层之上形成至少一个所述凸起图形。 2. The method according to claim 1, wherein the step S2 above the backing layer is formed of at least one of the protrusion pattern.
3. 如权利要求2所述的方法,其特征在于,所述有源区完全覆盖所述凸起图形的顶部上表面及两侧侧壁的表面。 The method according to claim 2, wherein said active region completely cover the surface of both side surfaces and on top of the protrusion pattern.
4. 如权利要求2所述的方法,其特征在于,所述有源区覆盖所述凸起图形部分上表面及位于该部分上表面同侧的侧壁的表面。 4. The method according to claim 2, wherein said active region covering the upper surface of the sidewall portion of the surface on the same side of the convex surface and the pattern portion located.
5. 如权利要求3或4所述的方法,其特征在于,所述有源区覆盖靠近所述凸起图形至少一侧侧壁的衬垫层部分上表面。 5. A method as claimed in claim 3 or claim 4, wherein said active region covering the upper surface of the pad portion of the protrusion pattern layer adjacent to at least one side of the sidewall.
6. 如权利要求1所述的方法,其特征在于,步骤S1中采用等离子增强化学气相沉积工艺分别沉积形成所述衬垫层及介质层,沉积的温度为400~450°C,所述衬垫层厚度为400~500埃,所述介质层厚度为2000~2500埃。 6. The method according to claim 1, wherein, in step S1, using plasma enhanced chemical vapor deposition process, depositing respectively formed in the backing layer and the dielectric layer, deposition temperature of 400 ~ 450 ° C, the backing cushion thickness of 400 to 500 angstroms, said dielectric layer having a thickness of 2000 to 2500 angstroms.
7. 如权利要求1所述的方法,其特征在于,所述衬垫层为氮化硅层,所述介质层为二氧化娃层。 7. The method according to claim 1, wherein said spacer layer is a silicon nitride layer, said dielectric layer is a baby dioxide layer.
8. 如权利要求1所述的方法,其特征在于,所述凸起图形的高度为400~600埃,所述凸起图两侧侧壁与所述衬垫层之间的角度为40°~60°。 8. The method according to claim 1, characterized in that the height of the protrusion pattern is 400 to 600 angstroms, the projection angle between the two sides of the sidewall spacer layer in FIG. 40 ° ~ 60 °.
9. 如权利要求1所述的方法,其特征在于,采用化学气相沉积工艺沉积所述非晶硅层, 沉积的温度为400~500 °C,沉积所述非晶硅层的厚度为400~500埃。 9. The method according to claim 1, characterized by the deposition of the amorphous silicon layer chemical vapor deposition process, the deposition temperature is 400 ~ 500 ° C, the thickness of the deposited amorphous silicon layer is 400 to 500 angstroms.
10. 如权利要求1所述的方法,其特征在于,所述步骤S3中采用激光退火工艺将所述非晶娃层转化为多晶娃层。 10. The method according to claim 1, wherein said step S3, the laser annealing process using an amorphous layer into a polycrystalline baby doll layer.
11. 如权利要求1所述的方法,其特征在于,采用化学气相沉积工艺沉积所述绝缘层, 且所述绝缘层包括二氧化硅层及覆盖于该二氧化硅层之上的氮化硅层。 11. The method according to claim 1, wherein the chemical vapor deposition process of the insulating layer and the insulating layer comprises silicon dioxide layer and a silicon dioxide layer overlying the silicon nitride Floor.
12. 如权利要求1所述的方法,其特征在于,采用物理气相沉积工艺沉积所述栅极材料层,所述栅极材料层材质为钼,形成的所述栅极厚度为2000~3000埃。 12. The method according to claim 1, wherein said gate material layer using a physical vapor deposition process, the gate material layer is made of molybdenum, the gate electrode formed in a thickness of 2000 to 3000 Angstroms .
13. -种低温多晶硅TFT器件,其特征在于,所述器件包括一半导体衬底,所述衬底之上覆盖有一衬垫层,以及位于该衬垫层之上形成有凸起图形, 一有源区覆盖在所述凸起图形顶部上表面的至少局部区域及覆盖在凸起图形的至少一个侧壁上; 所述TFT器件还包括一栅极及位于该栅极下方的栅绝缘层,以及有源区的一源极区及一漏极区分别位于沟道区的两侧; 其中,所述栅极与所述栅绝缘层之间形成有一叠层,且该叠层至少具有交叠在有源区上的堆栈式栅极,所述堆栈式栅极位于一沟道区的上方,且所述凸起图形增大所述沟道区宽度的同时不改变该沟道区的长度。 13. - kind of low-temperature polysilicon TFT device, wherein the device comprises a semiconductor substrate, the substrate is covered with a top liner layer, and forming a spacer layer located above the projection pattern, there is a a source region in said projection covering the top surface of the pattern region and at least partially covered on at least one side wall of the protrusion pattern; the TFT device further comprises a gate electrode and the gate insulating layer located below the gate electrode, and a source region and a drain region of the active region located on both sides of the channel region respectively; wherein a laminate is formed between the gate and the gate insulating layer, and the laminate having at least overlap stacked gate electrode on the active region, the stacked gate is positioned above a channel region, and said projection pattern width of the channel region is increased without changing the length of the channel region.
14. 如权利要求13所述的器件,其特征在于,所述基底之上形成有至少一个凸起图形。 14. The device according to claim 13, wherein said substrate is formed over at least one projection pattern.
15. 如权利要求13所述的器件,其特征在于,所述有源区覆盖所述凸起图形的全部上表面及两侧侧壁的表面,以及覆盖相邻凸起图形之间的衬垫层暴露的上表面。 15. The device according to claim 13, wherein said active region and sidewalls covering surfaces on all sides of the projection pattern, and a cover gasket between adjacent raised pattern exposed on the surface layer.
16. 如权利要求13所述的器件,其特征在于,所述有源区覆盖所述凸起图形部分上表面及位于该部分上表面同侧的侧壁表面。 16. The device according to claim 13, wherein said active region covering the sidewall surface of the upper portion of the convex surface and a pattern of the portion located on the same side surface.
17. 如权利要求15或16所述的方法,其特征在于,所述有源区覆盖靠近所述凸起图形至少一侧侧壁的衬垫层部分上表面。 17. The method of claim 15 or claim 16, wherein said active region covering the upper surface of the pad portion of the protrusion pattern layer adjacent to at least one side of the sidewall.
18. 如权利要求13所述的TFT器件,其特征在于,所述衬垫层为氮化硅层,所述氮化硅层厚度为400~500埃。 18. The TFT device according to claim 13, wherein said spacer layer is a silicon nitride layer, the silicon nitride layer having a thickness of 400 to 500 angstroms.
19. 如权利要求13所述的TFT器件,其特征在于,所述凸起图形材质为二氧化硅,所述凸起图形高度为400~600埃,且该凸起图两侧侧壁与所述衬垫层之间的角度为40°~ 60。 19. The TFT device according to claim 13, wherein the relief pattern is made of silica, the height of the projection pattern 400 to 600 angstroms, and the projection and the side wall on both sides of FIG. the angle between said liner layer is 40 ° ~ 60. .
20. 如权利要求13所述的TFT器件,其特征在于,所述栅绝缘层自下而上依次包括二氧化硅层和氮化硅层,所述二氧化硅层厚度为400~500埃,所述氮化硅层厚度为700~800 埃。 20. The TFT device according to claim 13, wherein said gate insulating layer comprises silicon dioxide layer in this order from the silicon nitride layer and the silica layer thickness of 400 to 500 angstroms, the silicon nitride layer having a thickness of 700 to 800 angstroms.
21. 如权利要求13所述的TFT器件,其特征在于,所述栅极厚度为2000~3000埃,所述栅极材质为钼。 21. The TFT device according to claim 13, wherein the gate electrode 2000 to a thickness of 3000 angstroms, the gate electrode made of molybdenum.
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