CN209641657U - A kind of TFT self-tolerant touch-control array substrate - Google Patents
A kind of TFT self-tolerant touch-control array substrate Download PDFInfo
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- CN209641657U CN209641657U CN201920327771.XU CN201920327771U CN209641657U CN 209641657 U CN209641657 U CN 209641657U CN 201920327771 U CN201920327771 U CN 201920327771U CN 209641657 U CN209641657 U CN 209641657U
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Abstract
The utility model relates to field of display technology, more particularly to a kind of TFT self-tolerant touch-control array substrate, the first metal layer is arranged to first grid and touch-control routing region by the TFT self-tolerant touch-control array substrate, the first metal layer of transistor is multiplexed as touch-control cabling, and the corresponding position of the vertical direction in the interlayer insulating film, the first passivation layer, the second passivation layer and flatness layer is provided with via hole, the touch-control cabling of touch control electrode and the first metal layer is overlapped by via hole mode, realizes self-tolerant touch-control.It is arranged by above structure, enormously simplifies the structure of tft array substrate, and can simplify production process in process of production, substantially reduces production cost.
Description
Technical field
The utility model relates to field of display technology more particularly to a kind of TFT self-tolerant touch-control array substrates.
Background technique
IGZO is a kind of amorphous oxides containing indium, gallium and zinc, and carrier mobility is 20-30 times of amorphous silicon, can
To greatly improve TFT to the charge-discharge velocity of pixel electrode, the response speed of pixel is improved, has faster panel refresh frequency
Rate is, it can be achieved that ultrahigh resolution TFT-LCD.
Since IGZO TFT device relative low temperature multi-crystal TFT possesses more superior Ioff, picture element TFT only needs single grid
It can suppress electrical leakage problems, low-power consumption purpose can be reached using lower driving frequency.And LTPS TFT is compared with IGZO TFT
Possess higher mobility (about 3-10 times big), peripheral driving circuit can design smaller, with the obvious advantage in narrow frame.Cause
This can use NMOS/PMOS the and Oxide semiconductor N MOS device construction display of poly-Si in existing LTPO technology
Circuit realizes device miniaturization, narrow frame by the high mobility characteristic of LTPS technology, while utilizing oxide semiconductor device
The low drain stream of part and the electrical stability of bending, reach the characteristics such as narrow frame, flexibility, low frequency.
Existing LTPO technology is using the source-drain electrode metal layer M2 of LTPS TFT as the grid of oxide semiconductor TFT2；TP
Cabling is arranged using the CM above OC, final to realize touch control electrode and touch-control cabling to carry out film layer, the design above OC
Overlap joint, structure is complicated for array substrate, makes relatively complicated, and production cost is high.
Summary of the invention
For this reason, it may be necessary to provide a kind of TFT self-tolerant touch-control array substrate, to solve tft array substrate in the prior art
Structure is complicated, makes relatively complicated, the higher problem of production cost.
To achieve the above object, a kind of TFT self-tolerant touch-control array substrate, the tft array substrate are inventor provided
Including substrate and the gate insulating layer being set in turn on the substrate, the first metal layer, interlayer insulating film, the second metal
Layer, the first passivation layer, active layer, third metal layer, the second passivation layer, flatness layer, touch control electrode and pixel electrode；
The first metal layer includes first grid and touch-control routing region；
The second metal layer includes the first source drain region and second grid, and first source drain region forms source electrode
Drain；
The third metal layer includes the second source drain region, and second source drain region forms source electrode and drain electrode, institute
Stating the active layer between source electrode and drain electrode is channel region；
The pixel electrode and the second source drain region overlap；
The interlayer insulating film, the first passivation layer, the second passivation layer and flatness layer are all provided in the corresponding position of vertical direction
It is equipped with via hole, the touch control electrode is overlapped by the touch-control routing region of the via hole and the first metal layer.
As a kind of preferred structure of the utility model, the tft array substrate further includes semiconductor layer, the semiconductor
For layer between substrate and gate insulating layer, the semiconductor layer includes PMOS semiconductor layer and NMOS semiconductor layer.
As a kind of preferred structure of the utility model, the tft array substrate further includes buffer layer, the buffer layer position
Between substrate and semiconductor layer.
As a kind of preferred structure of the utility model, the tft array substrate further includes third passivation layer, the third
Passivation layer is covered in the top of flatness layer and touch control electrode, and the pixel electrode is located on third passivation layer.
As a kind of preferred structure of the utility model, the tft array substrate further includes etch stop layer, the etching
Barrier layer be located at active layer and third metal layer between.
As a kind of preferred structure of the utility model, the active layer is oxide semiconductor layer.
As a kind of preferred structure of the utility model, the oxide semiconductor layer by indium, gallium and zinc amorphous oxide
Object (IGZO) thin-film material is formed.
As a kind of preferred structure of the utility model, the material of the gate insulating layer and interlayer insulating film can be oxygen
One of SiClx, silicon nitride, silicon oxynitride, aluminium oxide.
It is different from the prior art, above-mentioned technical proposal has the advantages that a kind of TFT self-tolerant touch-control battle array of the utility model
The first metal layer is arranged to first grid and touch-control routing region by column substrate, is multiplexed the gate metal layer M1 conduct of transistor
Touch-control cabling, and the correspondence position of the vertical direction in the interlayer insulating film, the first passivation layer, the second passivation layer and flatness layer
It installs and is equipped with via hole, the touch-control cabling of touch control electrode and the first metal layer is overlapped by via hole mode, realizes self-tolerant touch-control.
It is arranged by above structure, enormously simplifies the structure of tft array substrate, and can simplify production stream in process of production
Journey substantially reduces production cost.
Detailed description of the invention
Fig. 1 is that a kind of sectional structure of main view of one embodiment of TFT self-tolerant touch-control array substrate of the utility model is illustrated
Figure；
Fig. 2 is that a kind of sectional structure of the main view of another embodiment of TFT self-tolerant touch-control array substrate of the utility model shows
It is intended to；
Fig. 3 is a kind of TFT self-tolerant touch-control array substrate part processing procedure schematic diagram of the utility model.
Description of symbols:
1, substrate；
2, gate insulating layer；
31, first grid；32, touch-control routing region；
4, interlayer insulating film；
51, the first source drain region；52, second grid；
6, the first passivation layer；
7, active layer；
81, the second source drain region；
9, the second passivation layer；
10, flatness layer；
11, touch control electrode；
12, pixel electrode；
131, PMOS semiconductor layer；132, NMOS semiconductor layer；
14, buffer layer；
15, third passivation layer；
16, etch stop layer.
Specific embodiment
Technology contents, construction feature, the objects and the effects for detailed description technical solution, below in conjunction with specific reality
It applies example and attached drawing is cooperated to be explained in detail.
1 to Fig. 3 is please referred to, the utility model discloses a kind of TFT self-tolerant touch-control array substrate, the tft array
Substrate includes substrate 1 and the gate insulating layer 2 being set in turn on the substrate 1, the first metal layer, interlayer insulating film
(ILD) 4, second metal layer, the first passivation layer (PV) 6, active layer (SE) 7, third metal layer, the second passivation layer (PV2) 9, flat
Smooth layer (OC) 10, touch control electrode (BC) 11 and pixel electrode (PE) 12；
The first metal layer includes first grid (GE) 31 and touch-control routing region (M1) 32；
The second metal layer includes the first source drain region (SD) 51 and second grid (GE) 52, first source-drain electrode
The drain of the formation of region (SD) 51 source electrode；
The third metal layer includes the second source drain region (SD) 81, and second source drain region (SD) 81 forms source
Pole and drain electrode, the active layer (SE) 7 between the source electrode and drain electrode are channel region；
The pixel electrode (PE) 12 and the second source drain region (SD) 81 overlap；
6, second passivation layer of the 4, first passivation layer of interlayer insulating film (ILD) (PV) (PV2) 9 and flatness layer (OC) 10 exist
The corresponding position of vertical direction is provided with via hole, the touching that the touch control electrode (BC) 11 passes through the via hole and the first metal layer
Routing region (M1) 32 is controlled to overlap.
Main structure of the substrate 1 as TFT device, to deposit different film layers on substrate 1, by making accordingly
TFT device is ultimately formed as technique.In the present embodiment, the first metal layer a part therein is used as first grid (GE)
31, another part makes it possible to the first metal layer conduct that multiplexing is exclusively used in gate metal layer originally as TP touch-control cabling
Touch-control cabling simplifies and walks line process in the additional setting touch-control of flatness layer (OC) 10.The second metal layer includes the first source
Drain region (SD) 51 and second grid (GE) 52, first mountain and region, the first source drain region (SD) 51 are
The component part of one transistor (TFT1), the second source drain region (SD) 81 in second grid (GE) 52, third metal layer with
And active layer (SE) 7 is the component part of second transistor (TFT2).In addition, being located at touch-control routing region (M1) 32 and touch-control
Interlayer insulating film 4, the 6, second passivation layer of the first passivation layer (PV) (PV2) 9 and flatness layer (OC) between electrode (BC) 11 (BC)
The corresponding position of 10 vertical direction is provided with via hole, by via hole mode by the touching of touch control electrode (BC) 11 and the first metal layer
Cabling overlap joint is controlled, realizes self-tolerant touch-control.It is arranged by above structure, enormously simplifies the structure of tft array substrate, and can
Simplify film layer, the design in array substrate above flatness layer (OC) 10, dispenses CM, VA processing procedure, reduce twice light shield
Laying, be effectively simplified production process in process of production, substantially reduce production cost.
Fig. 1 and Fig. 2 are please referred to, as a kind of preferred embodiment of the utility model, the tft array substrate further includes half
Conductor layer, for the semiconductor layer between substrate 1 and gate insulating layer 2, the semiconductor layer includes PMOS semiconductor layer 131
With NMOS semiconductor layer 132.31 He of the PMOS semiconductor layer 131, the NMOS semiconductor layer 132 and first grid (GE)
First source drain region (SD) 51 forms cmos circuit structure.
In embodiment as depicted in figs. 1 and 2, the tft array substrate further includes buffer layer 14, the buffer layer 14
Between substrate 1 and semiconductor layer.The setting of the buffer layer 14 can directly can be contacted with underlay substrate 1 to avoid semiconductor layer
Characteristic is caused to be deteriorated.
Referring to Fig. 1, the tft array substrate further includes third passivation layer (CH) 15 in preferred embodiment, described
Three passivation layers (CH) 15 are covered in the top of flatness layer (OC) 10 Yu touch control electrode (BC) 11, and the pixel electrode (PE) 12 is located at
On third passivation layer (CH) 15.
Referring to Fig. 2, a kind of preferred embodiment as the utility model, the tft array substrate further includes etching resistance
Barrier (ES) 16, the etch stop layer (ES) 16 be located at active layer (SE) 7 and third metal layer between.The etching stops
The design of layer (ES) 16 can reduce oxide and report that mention active layer (SE) 7 is influenced by water oxygen, play protection active layer (SE's) 7
Effect, can extend the service life of thin-walled transistor to a certain extent.
In certain specific embodiments, the active layer (SE) 7 is oxide semiconductor layer.Active layer (SE) 7 is by grid
Pole tension control generates inversion layer, as conducting channel.In the present invention, the second source-drain electrode metal layer is formed
Source electrode and drain are connected in series therebetween as conducting channel by active layer (SE) 7, are moved with carrying out the high speed of electronics
It moves.Preferably, the oxide semiconductor layer is formed by amorphous oxides (IGZO) thin-film material of indium, gallium and zinc.IGZO has
The carrier mobility of active layer (SE) 7 is 20-30 times of amorphous silicon, can greatly improve TFT filling to pixel electrode (PE) 12
Discharge rate improves the response speed of pixel, can greatly improve the resolution ratio of display screen.
The material of embodiment in specific embodiment, the gate insulating layer 2 and interlayer insulating film 4 can be silica
One of SiOx, silicon nitride SiNx, silicon oxynitride SiON, aluminium oxide Al 2O3.The insulation that is made with above-mentioned material and
Pressure-resistant performance is all very good, may be suitable for the production of the insulating layer in tft array substrate.
As shown in figure 3, in the particular embodiment, in order to make it easy to understand, also disclosing TFT self-tolerant in the utility model
Touch control electrode (BC) 11 (BC) and touch-control routing region (M1) 32 (M1) in touch-control array substrate, pixel electrode (PE) 12 (PE) with
Second source drain region (SD) 81 (SD) overlaps production process:
Step 1: the first metal layer, the first source drain region (SD) 51 (SD) and active layer (SE) 7 are formed on substrate 1
(SE) pattern；
Step 2: forming the second source drain region (SD) 81 (SD) on step 1 treated substrate 1；
Step 3: forming the second passivation layer (PV2) 9 on step 2 treated substrate 1, and in the second passivation layer (PV2) 9
Upper via hole；
Step 4: forming flatness layer (OC) 10 on step 3 treated substrate 1, and touched on flatness layer (OC) 10
Control via hole and pixel via hole；
Step 5: forming touch control electrode (BC) 11 (BC) on step 4 treated substrate 1, and by touch control electrode (BC) 11
(BC) it is overlapped with the touch-control routing region (M1) 32 (M1) in the first metal layer；
Step 6: third passivation layer (CH) 15 is formed on step 5 treated substrate 1, and in third passivation layer (CH) 15
Upper via hole.
Step 7: forming pixel electrode (PE) 12 (PE) pattern on step 6 treated substrate 1, and by pixel electrode
(PE) 12 (PE) are overlapped with the second source drain region (SD) 81 (SD).
The utility model is undisclosed compared with LTPO technical matters, and this will not be repeated here, saves CM and VA in this section of processing procedure
Processing procedure reduces the laying of twice light shield, is effectively simplified production process in process of production, substantially reduces production cost.
It should be noted that being not intended to limit although the various embodiments described above have been described herein
The scope of patent protection of the utility model.Therefore, based on the innovative idea of the utility model, embodiment described herein is carried out
Change and modification or equivalent structure or equivalent flow shift made based on the specification and figures of the utility model, directly
Or above technical scheme is used in other related technical areas indirectly, it is included in the protection model of the utility model patent
Within enclosing.
Claims (8)
1. a kind of TFT self-tolerant touch-control array substrate, which is characterized in that the tft array substrate includes substrate and successively sets
It is placed in gate insulating layer on the substrate, the first metal layer, interlayer insulating film, second metal layer, the first passivation layer, active
Layer, third metal layer, the second passivation layer, flatness layer, touch control electrode and pixel electrode；
The first metal layer includes first grid and touch-control routing region；
The second metal layer includes the first source drain region and second grid, and first source drain region forms the leakage of source electrode
Grade；
The third metal layer includes the second source drain region, and second source drain region forms source electrode and drain electrode, the source
Active layer between pole and drain electrode is channel region；
The pixel electrode and the second source drain region overlap；
The interlayer insulating film, the first passivation layer, the second passivation layer and flatness layer are provided in the corresponding position of vertical direction
Via hole, the touch control electrode are overlapped by the touch-control routing region of the via hole and the first metal layer.
2. TFT self-tolerant touch-control array substrate according to claim 1, which is characterized in that the tft array substrate also wraps
Semiconductor layer is included, for the semiconductor layer between substrate and gate insulating layer, the semiconductor layer includes PMOS semiconductor layer
With NMOS semiconductor layer.
3. TFT self-tolerant touch-control array substrate according to claim 2, which is characterized in that the tft array substrate also wraps
Buffer layer is included, the buffer layer is between substrate and semiconductor layer.
4. TFT self-tolerant touch-control array substrate according to claim 1, which is characterized in that the tft array substrate also wraps
Third passivation layer is included, the third passivation layer is covered in the top of flatness layer and touch control electrode, and the pixel electrode is located at third
On passivation layer.
5. TFT self-tolerant touch-control array substrate according to claim 1, which is characterized in that the tft array substrate also wraps
Include etch stop layer, the etch stop layer be located at active layer and third metal layer between.
6. TFT self-tolerant touch-control array substrate according to claim 1, which is characterized in that the active layer is oxide
Semiconductor layer.
7. TFT self-tolerant touch-control array substrate according to claim 6, which is characterized in that the oxide semiconductor layer
It is formed by the amorphous oxide thin film material of indium, gallium and zinc.
8. TFT self-tolerant touch-control array substrate according to claim 1, which is characterized in that the gate insulating layer and layer
Between the material of insulating layer can be one of silica, silicon nitride, silicon oxynitride, aluminium oxide.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201920327771.XU CN209641657U (en) | 2019-03-15 | 2019-03-15 | A kind of TFT self-tolerant touch-control array substrate |
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| CN201920327771.XU CN209641657U (en) | 2019-03-15 | 2019-03-15 | A kind of TFT self-tolerant touch-control array substrate |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111367436A (en) * | 2020-03-30 | 2020-07-03 | 福建华佳彩有限公司 | Touch display structure |
| CN113296631A (en) * | 2021-05-19 | 2021-08-24 | 武汉华星光电半导体显示技术有限公司 | Touch display panel and electronic equipment |
| CN113296631B (en) * | 2021-05-19 | 2024-04-23 | 武汉华星光电半导体显示技术有限公司 | Touch display panel and electronic equipment |
-
2019
- 2019-03-15 CN CN201920327771.XU patent/CN209641657U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111367436A (en) * | 2020-03-30 | 2020-07-03 | 福建华佳彩有限公司 | Touch display structure |
| CN113296631A (en) * | 2021-05-19 | 2021-08-24 | 武汉华星光电半导体显示技术有限公司 | Touch display panel and electronic equipment |
| CN113296631B (en) * | 2021-05-19 | 2024-04-23 | 武汉华星光电半导体显示技术有限公司 | Touch display panel and electronic equipment |
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