CN100585831C - Semiconductor element, display unit, electrooptical device and above-mentioned manufacture method - Google Patents
Semiconductor element, display unit, electrooptical device and above-mentioned manufacture method Download PDFInfo
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- CN100585831C CN100585831C CN200810144230A CN200810144230A CN100585831C CN 100585831 C CN100585831 C CN 100585831C CN 200810144230 A CN200810144230 A CN 200810144230A CN 200810144230 A CN200810144230 A CN 200810144230A CN 100585831 C CN100585831 C CN 100585831C
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Abstract
The invention provides a kind of semiconductor element, display unit, electrooptical device and above-mentioned manufacture method, wherein, manufacture method is included in and forms a P-type mos element and a N type metal oxide semiconductor element on the substrate.Wherein, the P-type mos element comprises that the first island polysilicon, is covered in gate insulation layer and on the first island polysilicon and is positioned at first grid on the gate insulation layer.In addition, the manufacture method of P-type mos element comprises: the first island polysilicon is carried out P type ion inject, to form a plurality of P type heavily doped regions and a plurality of P type light doping section, wherein the distance of channel region is in fact less than 3 microns, and one of them person's of P type light doping section distance be essentially channel region distance 10% to 80%.P type light doping section improves the short-channel effect of P-type mos element.
Description
Technical field
The invention relates to a kind of semiconductor element, display unit, electrooptical device and above-mentioned manufacture method, and particularly relevant for a kind of CMOS (Complementary Metal Oxide Semiconductor) (Complementary MetalOxide Semiconductor, CMOS) element and manufacture method thereof.
Background technology
Along with showing being showing improvement or progress day by day of science and technology, people can make life convenient more by the auxiliary of display unit, for asking light, the thin characteristic of display, so flat-panel screens (Flat Panel Display FPD) becomes present main flow.
In general, the semiconductor element in the viewing area of flat-panel screens can be divided into low temperature polycrystalline silicon (Low Temperature Poly-Silicon, LTPS) metal-oxide semiconductor (MOS) and amorphous silicon (Amorphous Silicon, a-Si) thin-film transistor.Because the electron mobility (Mobility) of low temperature polycrystalline silicon metal-oxide semiconductor (MOS) can reach 200cm
2More than/the V-sec, thus the size of low temperature polycrystalline silicon metal-oxide semiconductor (MOS) can design ground littler, and then promote simultaneously flat-panel screens aperture opening ratio (Aperture Ratio, AR) and reduce power consumption.
Yet when the size decreases of low temperature polycrystalline silicon metal-oxide semiconductor (MOS), the channel region length of low temperature polycrystalline silicon metal-oxide semiconductor (MOS) also diminishes thereupon.If when driving this low temperature polycrystalline silicon metal-oxide semiconductor (MOS) with general design parameter, then can produce the situation of the electron energy rising of channel region and drain electrode joint, make the phenomenon of leakage current even more serious, this is short-channel effect (Short Channel Effect), and then makes the electrical deterioration of low temperature polycrystalline silicon metal-oxide semiconductor (MOS).
Fig. 1 illustrates the part sectioned view of known a kind of low temperature polycrystalline silicon metal oxide semiconductor device.Please refer to Fig. 1, low temperature polycrystalline silicon metal oxide semiconductor device 100 comprises a P-type mos element 110 and a N type metal oxide semiconductor element 120.Wherein, P-type mos element 110 comprises that one first island polysilicon (poly-silicon island) 112, is covered in gate insulation layer 114 and on the first island polysilicon 112 and is positioned at first grid 116 on the gate insulation layer 114, and N type metal oxide semiconductor element 120 comprises that one second island polysilicon 122 and is positioned at the second grid 126 on the gate insulation layer 114.
As shown in Figure 1, P-type mos element 110 has the structure of a plurality of P type heavily doped region 112a.And the second island polysilicon 122 of N type metal oxide semiconductor element 120 has a plurality of N type heavily doped region 122a and a plurality of lightly doped drain LDDN '.Generally speaking, N type metal oxide semiconductor element 120 solves the problem of short-channel effect usually by N type lightly doped drain LDDN ', but the situation of its electrical deterioration that short-channel effect causes of P-type mos element 110 is faced less than aquatic foods, even think that P-type mos element 110 can't need less raceway groove to improve the characteristic of element, and otherwise improve, for example: the crystallite size of the first island polysilicon 112 of P-type mos element 110 is near the crystallite size of the second island polysilicon 122 of N type metal oxide semiconductor element 120.
Summary of the invention
The invention provides a kind of semiconductor element and manufacture method thereof, to produce the semiconductor element that is made of P-type mos element and N type metal oxide semiconductor element, wherein P-type mos element and N type metal oxide semiconductor element all have lightly doped drain (LDD).
The present invention provides a kind of manufacture method of display unit in addition, to produce the display unit with above-mentioned semiconductor element.
The present invention provides a kind of manufacture method of electrooptical device again, to produce the electrooptical device with above-mentioned semiconductor element.
The present invention proposes a kind of manufacture method of semiconductor element, its method comprises: form a P-type mos element and a N type metal oxide semiconductor element on a substrate, wherein the P-type mos element comprises that one first island polysilicon, is covered in gate insulation layer and on the first island polysilicon and is positioned at first grid on the gate insulation layer, and first grid is positioned at first island polysilicon top.In addition, the manufacture method of P-type mos element comprises: at first, form one first patterning photoresist layer on gate insulation layer and first grid, and the first patterning photoresist layer has a plurality of first openings.Then, be photomask with the first patterning photoresist layer, the first island polysilicon is carried out P type ion inject, in the part first island polysilicon of first opening below, to form a plurality of P type heavily doped regions.Then, remove the first patterning photoresist layer of part, forming second a patterning photoresist layer with a plurality of second openings, and the size of each second opening is in fact greater than the size of each first opening.Afterwards, with the first grid and the second patterning photoresist layer is photomask, the first island polysilicon is carried out P type ion to be injected, in another part first island polysilicon of second opening below, to form a plurality of P type light doping sections, the first island polysilicon that is positioned at the first grid below then is used as a channel region, so that channel region is between P type light doping section, wherein the length of channel region is in fact less than 3 microns, and one of them person's of P type light doping section length be essentially channel region length 10% to 80%.
The present invention proposes a kind of manufacture method of display unit in addition, and the manufacture method of this display unit comprises the manufacture method as above-mentioned semiconductor element.
The present invention proposes a kind of manufacture method of electrooptical device again, and the manufacture method of this electrooptical device comprises the manufacture method as above-mentioned semiconductor element.
The invention provides another semiconductor element, it comprises a substrate, at least one P-type mos element and at least one N type metal oxide semiconductor element.The P-type mos arrangements of components is on substrate, and the P-type mos element comprises that one first island polysilicon, is covered in gate insulation layer and on the first island polysilicon and is positioned at first grid on the gate insulation layer.First grid is positioned at first island polysilicon top, and has a plurality of P type heavily doped regions, the channel region of a plurality of P type light doping section and between P type light doping section in the first island polysilicon.Wherein, the length of channel region is in fact less than 3 microns, and one of them person's of P type light doping section length be essentially channel region length 10% to 80%.N type metal oxide semiconductor arrangements of components is on substrate, and N type metal oxide semiconductor element comprises that one second island polysilicon, is covered in gate insulation layer and on the second island polysilicon and is positioned at second grid on the gate insulation layer.Second grid is positioned at second island polysilicon top, and has a plurality of N type heavily doped regions, the channel region of a plurality of N type light doping section and between N type light doping section in the second island polysilicon.
The present invention proposes a kind of display unit in addition, and this display unit comprises as above-mentioned semiconductor element.
The present invention proposes a kind of electrooptical device again, and this electrooptical device comprises as above-mentioned semiconductor element.
Semiconductor element of the present invention is made of P-type mos element and N type metal oxide semiconductor element, and wherein P-type mos element and N type metal oxide semiconductor element all have lightly doped drain (P type lightly doped drain and N type lightly doped drain).Therefore, the short-channel effect of P-type mos element and N type metal oxide semiconductor element all can be improved.In addition, P type lightly doped drain there is no the doubt that increases cost on making.
Description of drawings
Fig. 1 illustrates the part sectioned view of known a kind of low temperature polycrystalline silicon metal oxide semiconductor device.
Fig. 2 A illustrates the part sectioned view of the semiconductor element of one embodiment of the invention.
Fig. 2 B illustrates the manufacture method flow chart of the P-type mos element of one embodiment of the invention.
Fig. 3 A～3E illustrates the manufacturing process profile of the P-type mos element of one embodiment of the invention.
Fig. 3 F and Fig. 3 G be known P-type mos element when different condition, its drain current and gate voltage curve.
Fig. 3 H and 3I be the P-type mos of one embodiment of the invention when different operating voltage, its drain current and gate voltage curve.
Fig. 3 J is the starting voltage of P-type mos element of one embodiment of the invention and the starting voltage and the light doping section length comparison diagram of known P-type mos element.
Fig. 4 illustrates the part sectioned view of the N type metal oxide semiconductor element of one embodiment of the invention.
Fig. 4 A illustrates the partial cutaway schematic of the N type doped region of a kind of embodiment.
Fig. 4 B and Fig. 4 B ' illustrate the partial cutaway schematic of the N type doped region of another kind of embodiment.
Fig. 4 C illustrates the partial cutaway schematic of the N type doped region of another embodiment.
Fig. 5 A～Fig. 5 E illustrates the manufacturing process profile of the semiconductor element of one embodiment of the invention.
Fig. 6 A illustrates the schematic diagram of the display unit of one embodiment of the invention.
Fig. 6 B illustrates the schematic diagram of the electrooptical device of one embodiment of the invention.
Drawing reference numeral:
100: the low temperature polycrystalline silicon metal oxide semiconductor device
102: curve
110:P type metal oxide semiconductor element
112: the first island polysilicons
112a:P type heavily doped region
114: gate insulation layer
116: first grid
120:N type metal oxide semiconductor element
122: the second island polysilicons
122a:N type heavily doped region
126: second grid
LDDN ': N type lightly doped drain
200: semiconductor element
202: substrate
204: resilient coating
210:P type metal oxide semiconductor element
212: the first island polysilicons
212a, 212a ': P type heavily doped region
212c: channel region
214: gate insulation layer
216: first grid
220:N type metal oxide semiconductor element
222: the second island polysilicons
222a, LDDN:N type doped region
226: second grid
302: curve
510: interlayer dielectric layer
520: the contact conductor
530: the patterning flatness layer
540: conductive layer
600: electrooptical device
602: display unit
604: electronic component
612: display floater
622: image element array substrates
632: another substrate
632a: transparency electrode
642: display medium
A1, A1 ', A2, A2 ': zone
D1, D2, D2 ', D3:N type ion implantation technology
H1: first opening
H2: second opening
L: channel region length
LDDP:P type lightly doped drain
PR1: the first patterning photoresist layer
PR2: the second patterning photoresist layer
S201, S203, S205, S207: step
S203 ', S207 ': P type ion implantation technology
W1: first contact window
W2: second contact window
Embodiment
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Fig. 2 A illustrates the part sectioned view of the semiconductor element of one embodiment of the invention.Please refer to Fig. 2 A, the manufacture method of the semiconductor element 200 of present embodiment is included on the substrate 202 and forms a P-type mos element 210 and a N type metal oxide semiconductor element 220, and wherein P-type mos element 210 comprises that one first island polysilicon (poly-silicon island) 212, is covered in gate insulation layer 214 and on the first island polysilicon 212 and is positioned at first grid 216 on the gate insulation layer 214.Shown in Fig. 2 A, first grid 216 is positioned at the first island polysilicon, 212 tops.The manufacture method of P-type mos element 210 below is described, shown in Fig. 2 B.
Fig. 2 B illustrates the manufacture method flow chart of the P-type mos element of one embodiment of the invention, and wherein this manufacture method comprises four steps at least.Fig. 3 A～3E illustrates the manufacturing process profile of the P-type mos element of one embodiment of the invention.Please at first, in step S201, on gate insulation layer 214 and first grid 216, form one first patterning photoresist layer PR1, and the first patterning photoresist layer PR1 have a plurality of first opening H1 simultaneously with reference to Fig. 2 B and Fig. 3 A.In the present embodiment, before forming the first patterning photoresist layer PR1, optionally on substrate 202, form a resilient coating 204 earlier.Then, on resilient coating 204, form one first island polysilicon 212.
Hold above-mentionedly, the formation method of the first island polysilicon 212 of present embodiment is as follows.At first, on substrate 202, form an amorphous silicon layer.Then, amorphous silicon layer is carried out a thermal anneal process, amorphous silicon layer is converted to a polysilicon layer, wherein thermal anneal process for example is a LASER HEAT annealing process (laserannealing process).Afterwards, the patterned polysilicon layer is to form the first island polysilicon 212, and wherein the method for patterned polysilicon layer can adopt processing steps such as photoetching process and etching technics.Yet the present invention does not limit the formation method of the first island polysilicon 212, is familiar with this area person skilled when adopting other modes to make the first island polysilicon 212 on substrate 202.In addition, present embodiment also can directly be bought the substrate 202 with first island polysilicon 212 and carries out follow-up technology or make the first island polysilicon 212 with ink-jet method, screen painting method, coating and photoetching development method, deposition and photoetching development method or other suitable manner.
As shown in Figure 3A, then on the first island polysilicon 212, form gate insulation layer 214, first grid 216 and the first patterning photoresist layer PR1 in regular turn.It should be noted that, the formation method of the first patterning photoresist layer PR1 for example is to utilize one masking process to form first a patterning photoresist layer PR1 with a plurality of first opening H1 on substrate 202, so that the first patterning photoresist layer PR1 covers first grid 216, gate insulation layer 214 and the first island polysilicon 212, but be not limited thereto, the first patterning photoresist layer PR1 also can use ink-jet method, screen painting method or other suitable manner to make the first patterning photoresist layer PR1.
Then, please be simultaneously with reference to Fig. 2 B and Fig. 3 B.In step S203, with the first patterning photoresist layer PR1 is photomask, the first island polysilicon 212 is carried out P type ion implantation technology S203 ', in the part first island polysilicon 212 of first opening H1 below, to form a plurality of P type heavily doped region 212a '.In detail, the method that forms a plurality of P type heavily doped region 212a ' for example is to inject the subregion A1 of mode below the first opening H1 and the first island polysilicon, the 212 formation P type ions of A1 ' of (ionimplantation) by ion, to finish the making of P type heavily doped region 212a '.
Then, please be simultaneously with reference to Fig. 2 B and Fig. 3 C.In step S205, remove the first patterning photoresist layer PR1 of part, forming second a patterning photoresist layer PR2 with a plurality of second opening H2, and the size of each second opening H2 is in fact greater than the size of each first opening H1.Shown in Fig. 3 B and Fig. 3 C, the method that removes the first patterning photoresist layer PR1 of part for example is an ashing (Ashing) technology, it can utilize gaseous plasma, for example: oxygen gas plasma, hydrogen gas plasma, nitrogen gas plasma or other suitable gaseous plasma or above-mentioned combination, the first patterning photoresist layer PR1 is carried out a non-grade form the second patterning photoresist layer PR2 to etching technics.
Because cineration technics is that non-grade is to etching technics, so the thicknesses of layers of the first patterning photoresist layer PR1 is understood attenuation and formed the second patterning photoresist layer PR2.From another perspective, the meeting of the first opening H1 enlarges and forms the second opening H2.In other words, the size of the second opening H2 is in fact greater than the size of the first opening H1, and the thickness of the second patterning photoresist layer PR2 is in fact less than the thickness of the first patterning photoresist layer PR1.
Shown in Fig. 3 C, in the present embodiment, the edge of the second patterning photoresist layer PR2 can trim the edge of first grid 216.In other embodiments, the edge of the second patterning photoresist layer PR2 can in contract to the edge of first grid 216.In other words, after finishing above-mentioned cineration technics, the edge of the second patterning photoresist layer PR2 is a principle with the edge that does not exceed first grid 216.
Afterwards, please be simultaneously with reference to Fig. 2 B and Fig. 3 D.In step S207, with the first grid 216 and the second patterning photoresist layer PR2 is photomask, the first island polysilicon 212 is carried out P type ion implantation technology S207 ', with a plurality of P type lightly doped drain LDDP of 212 formation in the first island polysilicon of regional A2 of another part of second opening H2 below and A2 ', and P type lightly doped drain LDDP also can be described as P type light doping section.In addition, 212 of the first island polysilicons that are positioned at first grid 216 belows are used as a channel region 212c.That is channel region 212c is between each P type heavily doped region 212a, also between each P type lightly doped drain LDDP.
The distance of channel region 212c, for example: length (L), in fact less than 3 microns (micron).Yet,, need the problem of considering that short-channel effect spreads out and stretches out usually when the length L of the channel region 212c of P-type mos element 210 during less than 3 microns.Therefore, the P-type mos element 210 of present embodiment adopts P type lightly doped drain LDDP to improve short-channel effect, and described a plurality of P type lightly doped drain LDDP wherein at least one distance be essentially this channel region 212c distance (for example length L) 10%～80%.Preferably, described a plurality of one of them person's of P type light doping section distance is essentially 20% to 60% of this channel region.Moreover, be the effect of balanced each P type lightly doped drain LDDP, preferably, each P type is gently mixed offset and is equated from the real matter that goes up, but is not limited thereto.In other embodiment, each P type is gently mixed offset from can be unequal.
In addition, present embodiment utilizes the second patterning photoresist layer PR2 on first grid 216 and/or the first grid 216 to come the first island polysilicon 212 is carried out P type ion implantation technology S207 ' as photomask, to form P type lightly doped drain LDDP.So far above-mentioned, P-type mos element 210 roughly completes.
Shown in Fig. 3 D, the first island polysilicon 212, gate insulation layer 214 and first grid 216 can constitute P-type mos element 210, and wherein the first island polysilicon 212 comprises channel region 212c, P type heavily doped region 212a and P type lightly doped drain LDDP.After the second patterning photoresist layer PR2 in removing Fig. 3 D, just can obtain P-type mos element 210, shown in Fig. 3 E.
Fig. 3 F and Fig. 3 G be the conventional P type metal oxide semiconductor when different operating voltage, its drain current and gate voltage curve, that wherein transverse axis is represented is grid voltage (VG), and the longitudinal axis represented be drain current (Id).The electrical curve chart of the conventional P type metal oxide semiconductor described in Fig. 3 F, the length of its channel region is more than or equal to 3 microns, and when not having light doping section (LDD), no matter among Fig. 3 F in the operating voltage absolute value of each point representative (| Vd|), as: the A point is represented 0.1 volt (V), the B point is represented 1 volt (V), the C point is represented 2 volts (V), the D point is represented 4 volts (V), on behalf of 6 volts (V) and F point, the E point represent 8 volts (V) and is cooperated grid voltage (VG), for example :-10V～+ 10V, then operating voltage change how, its electrical curve chart is that example is when working as standard with 1E-9 in drain current, the pairing grid voltage of the part of drain current rapid drawdown (VG) and be defined as starting voltage (Vt) still for the convergence, be 0 volt of convergence (V), meaning is that element is not subjected to the influence of channel length and does not need light doping section (LDD).
The electrical figure of the described conventional P type metal oxide semiconductor of Fig. 3 G, for the length of its channel region is less than 3 microns, for example 1.5 microns, and when not having light doping section (LDD), can find, as the operating voltage absolute value of difference as described in Fig. 3 F (| Vd|) and cooperate initial grid voltage (VG), for example :-10V～+ 10V, its electrical curve chart is that example is when working as standard with 1E-9 in drain current (Id), at the pairing grid voltage of the part of drain current rapid drawdown (VG) and be defined as starting voltage (Vt) for dispersing, meaning is the operating voltage of difference, can obtain different starting voltage (Vt) and starting voltage (Vt) also increases progressively along with operating voltage and increases progressively from directions X, and causing the degrees of offset of element characteristic too serious, meaning is that element is subjected to the influence of short-channel effect (short channel effect) very serious.
Fig. 3 H and Fig. 3 I are that the P-type mos element of one embodiment of the invention is when different operating voltage, its drain current (Id) and grid voltage (VG) curve, that wherein transverse axis is represented is grid voltage (VG), and the longitudinal axis represented be drain current (Id).The channel region length of the P-type mos element 210 among Fig. 3 H and Fig. 3 I is less than 3 microns, with 1.5 microns is example, but the value of being not limited thereto, so long as channel region length greater than 0 micron and less than 3 microns then applicable it, and the length of P type lightly doped drain LDDP be respectively with about 0.4 micron with about 0.8 micron be that example illustrates, but the value of being not limited thereto, so long as with described a plurality of P type lightly doped drain LDDP of foregoing invention wherein at least one distance (for example length) be essentially this channel region 212c distance 10%～80%.Preferably, described a plurality of one of them person's of P type light doping section distance is essentially 20% to 60% of this channel region.By Fig. 3 H and Fig. 3 I as can be known, and in as Fig. 3 F the above the different operating absolute value of voltage (| Vd|) down and cooperate starting voltage (Vt), for example :-10V～+ 10V, its electrical curve chart is that example is when working as standard with 1E-9 in drain current (Id), at the pairing grid voltage of the part of drain current rapid drawdown (VG) and be defined as starting voltage (Vt) tendency consistency, promptly present the convergence phenomenon, (channel region is less than 3 microns compared to the P-type mos element shown in known Fig. 3 G, and do not have P type lightly doped drain) described a plurality of curves, at the pairing grid voltage (VG) that part corresponded to of drain current rapid drawdown and be defined as starting voltage (Vt) and can present the phenomenon of dispersing (divergence).Therefore, the element characteristic of known P-type mos element has serious side-play amount, and the P type lightly doped drain LDDP of the P-type mos element 210 of present embodiment can significantly improve the degrees of offset of element characteristic.
Fig. 3 J is the starting voltage (threshold voltage) and light doping section (LDD) length comparison diagram of the P-type mos element and the known P-type mos element of one embodiment of the invention, and light doping section (LDD) also is called P type lightly doped drain (LDDP).Wherein curve 102 is that the indicatrix of P-type mos element 210 under the different condition is represented starting voltage degree of divergence or side-play amount, and the starting voltage value that on behalf of actual quantities, curve 302 measure for the indicatrix of P-type mos element under the different condition.Specifically, the condition of the each point on the indicatrix 102 be aforesaid different operating absolute value of voltage (| Vd|) and cooperate grid voltage (VG), for example :-10V～+ 10V, its electrical curve chart is example pairing grid voltage (VG) and be defined as starting voltage (Vt) when working as standard with 1E-9 in drain current, absolute difference with maximum starting voltage and minimum value starting voltage, and the condition of the P-type mos element of each point is as follows: a ' point is traditional element, and its channel region length is less than 3 microns, for example: 1.5 microns, there is no light doping section (LDD), b ' is an element of the present invention, and channel region length is less than 3 microns, for example: 1.5 microns, and have light doping section (LDD) and with light doping section length in fact 0.4 micron be example, c ' is an element of the present invention, and channel region length is less than 3 microns, for example: 1.5 microns, and have light doping section (LDD) and with light doping section length in fact 0.6 micron be that example and d ' they are element of the present invention, and channel region length is less than 3 microns, for example: 1.5 microns, and have light doping section (LDD) and with light doping section length in fact 0.8 micron be example.Can know that the condition of a ' point has very big starting voltage side-play amount.But b ' of the present invention does not have too big difference to d ' some condition, and convergence is 0V, represents very little of its starting voltage side-play amount.Indicatrix 302 all conditions are same as indicatrix 102, though, each point starting voltage value on the indicatrix 302 does not have too big difference, but because of the starting voltage side-play amount on the indicatrix 102, and know that Design Mode of the present invention can effectively suppress the starting voltage side-play amount, be short-channel effect, and have stable element characteristic.In addition, described channel length of each point and LDD length are to be example among Fig. 3 J, non-for being limited to this value, the distance of this channel region that only will meet this P-type mos element of the present invention is in fact less than 3 microns, and described a plurality of one of them person's of P type light doping section distance is essentially 10% to 80% of this channel region.Preferably, described a plurality of one of them person's of P type light doping section distance is essentially 20% to 60% of this channel region.
Fig. 4 illustrates the part sectioned view of the N type metal oxide semiconductor element of one embodiment of the invention.Please refer to Fig. 4, the N type metal oxide semiconductor element 220 of present embodiment comprises that one second island polysilicon 222 and is positioned at the second grid 226 on the gate insulation layer 214, and wherein second grid 226 is positioned at the second island polysilicon, 222 tops.And the manufacture method of N type metal oxide semiconductor element 220 comprises that the part second island polysilicon 222 is carried out N type ion to be injected, to form a plurality of N type doped region 222a and LDDN.In the present embodiment, N type doped region 222a for example is a N type heavily doped region, and N type doped region LDDN for example is a N type light doping section.
Need to prove that the present invention does not limit the step that forms N type doped region 222a and LDDN.Fig. 4 A, Fig. 4 B, Fig. 4 B ' and Fig. 4 C illustrate the partial cutaway schematic of the N type doped region of three kinds of embodiment.Please refer to Fig. 4 A, in the present embodiment, after the making of finishing the second island polysilicon 222, promptly the part second island polysilicon 222 is carried out the N type ion implantation technology D1 of various dose, to form N type doped region 222a and LDDN.
In another embodiment, for asking the convenience of technology, the manufacture method of N type doped region 222a and LDDN can be similar to the manufacture method of P type heavily doped region 212a and P type lightly doped drain LDDP respectively.At first, please refer to Fig. 4 B, finish the making of gate insulation layer 214 in the second island polysilicon, 222 tops after, again the part second island polysilicon 222 is carried out N type ion implantation technology D2, to form N type doped region 222a.Then, please refer to Fig. 4 B ', finish the making of second grid 226 in gate insulation layer 214 tops after, again the part second island polysilicon 222 is carried out N type ion implantation technology D2 ', to form N type doped region LDDN.
Please refer to Fig. 4 C, in another embodiment, finish the making of second grid 226 in gate insulation layer 214 tops after, again the part second island polysilicon 222 is carried out the N type ion implantation technology D3 of various dose, to form N type doped region 222a and LDDN.
It should be noted that above-mentioned N type doped region 222a and LDDN there is no absolute succession in making.In addition, N type doped region 222a, gate insulation layer 214 and second grid 226 do not have absolute succession in making, and N type doped region LDDN, gate insulation layer 214 and second grid 226 do not have absolute succession in making yet.That is the present invention does not limit the manufacture method that forms N type doped region 222a and LDDN.
Please refer to Fig. 4, Fig. 4 A, Fig. 4 B, Fig. 4 B ' or Fig. 4 C.Yet the manufacture method that forms N type doped region 222a and LDDN also can have a lot of kenels.For example use the twice masking process to define N type doped region 222a and LDDN, or only finish the making of N type doped region 222a and LDDN with one masking process other processes (for example cineration technics) of arranging in pairs or groups.Or, any process that can form N type doped region 222a and LDDN.That is the manufacture method of N type metal oxide semiconductor element 220 of the present invention and formation step are not limited to above-mentioned explanation.
After forming P-type mos element 210 and N type metal oxide semiconductor element 220, just can finish other making steps of semiconductor element 200 in regular turn.Fig. 3 A～Fig. 3 E, Fig. 4, Fig. 4 A, Fig. 4 B, Fig. 4 B ', 4C and Fig. 5 A～Fig. 5 E illustrate the manufacturing process profile of the semiconductor element of one embodiment of the invention.Wherein the manufacturing process of P-type mos element 210 can be with reference to figure 3A～3E, and the manufacturing process of N type metal oxide semiconductor element 210 can with reference to Fig. 4, Fig. 4 A, Fig. 4 B, explanation that Fig. 4 B ', 4C are relevant.Yet P-type mos element 210 of the present invention there is no absolute succession with N type metal oxide semiconductor element 220 on making.
After finishing P-type mos element 210 and N type metal oxide semiconductor element 220, the follow-up making step of semiconductor element 200 is please directly with reference to Fig. 5 A.At first, on first grid 216, second grid 226 and gate insulation layer 214, form an interlayer dielectric layer 510.That is to say, interlayer dielectric layer 510 is formed at the top of P-type mos element 210 and N type metal oxide semiconductor element 220, wherein P-type mos element 210 has P type lightly doped drain LDDP, and N type metal oxide semiconductor element 220 has N type doped region LDDN (N type lightly doped drain).
Then, please refer to Fig. 5 B, patterning interlayer dielectric layer 510 and gate insulation layer 214 are to form a plurality of first contact window W1 corresponding to N type doped region 222a and P type heavily doped region 212a in interlayer dielectric layer 510 and gate insulation layer 214.Wherein, in the present embodiment, the N type doped region 222a that corresponds to the first contact window W1 for example is a N type heavily doped region.
Then, please refer to Fig. 5 C, what form a plurality of and N type doped region 222a and P type heavily doped region 212a electrical connection in the first contact window W1 contacts conductor 520.
Afterwards, please refer to Fig. 5 D, in interlayer dielectric layer 510 with contact conductor 520 on selectivity form a patterning flatness layer 530, and have a plurality of second contact window W2 (Fig. 5 D only illustrate for example) in the patterning flatness layer 530.
Then, shown in Fig. 5 E, on patterning flatness layer 530, form a conductive layer 540, be electrically connected so that conductive layer 540 contacts conductor 520 by the second contact window W2 with part.In other words, dielectric layer 510 forms a conductive layer 540 with a plurality of contact of part on the conductor 520, be electrically connected so that conductive layer 540 contacts conductor 520 with part.So far above-mentioned, semiconductor element 200 roughly completes.
Must it should be noted that N type metal oxide semiconductor element 220 has the condition of N type doped region LDDN can the condition that have P type doped region LDDP in P-type mos element 220 of the present invention inequality.Yet preferably, the condition that N type metal oxide semiconductor element 220 has N type doped region LDDN is same as the condition that has P type doped region LDDP in P-type mos element 220 of the present invention.
Above-mentioned semiconductor element 200 structures and its manufacture method also can be applicable on display unit and the manufacture method thereof, and semiconductor element 200 can apply in pixel region (not illustrating), peripheral driving circuit district (not illustrating) and other outer members (not illustrating) of display unit wherein at least one.Preferably, semiconductor element 200 can apply to the pixel region (not illustrating) of display unit, but is not limited thereto.If, apply to the pixel region (not illustrating) of display unit, then conductive layer 540 can be described as pixel electrode.Wherein the framework of display unit as shown in Figure 6A.Fig. 6 A illustrates the schematic diagram of the display unit of one embodiment of the invention.Please refer to Fig. 6 A, the display unit 602 of present embodiment comprises at least one display floater 612, and the finished product of display floater 612 comprises an image element array substrates 622 at least, another substrate 632 and one with respect to this image element array substrates 622 is arranged at the display medium 642 between image element array substrates 622 and another substrate 632.Wherein image element array substrates 622 has above-mentioned semiconductor element 200, and another substrate 632 selectivity have a transparency electrode 632a.In addition, when display medium 642 is liquid crystal material, display unit 602 is called display panels (as: penetrating type display floater, the semi penetration type display floater, reflective display panel, colored filter display floater of (color filter on array) on active layers, active layers display floater of (array on color filter) on colored filter, vertical orientation type (VA) display floater, horizontal switch type (IPS) display floater, multi-domain perpendicular alignment-type (MVA) display floater, twisted nematic (TN) display floater, super-twist nematic (STN) display floater, pattern vertical orientation type (PVA) display floater, super pattern vertical orientation type (S-PVA) display floater, the advanced person is type (ASV) display floater with great visual angle, fringe field switch type (FFS) display floater, continuous fireworks shape arrange type (CPA) display floater, axial symmetry is arranged micella type (ASM) display floater, optical compensation curved arrange type (OCB) display floater, super horizontal switch type (S-IPS) display floater, advanced super horizontal switch type (AS-IPS) display floater, extreme edge electric field switch type (UFFS) display floater, stabilizing polymer alignment-type display floater, double vision angle type (dual-view) display floater, three visual angle type (triple-view) display floaters, 3 d display (three-dimensional) or other profile plate, or above-mentioned combination), also be called non-light-emitting display panel.If display medium 642 is the electroluminescence material, 602 of display unit are called electric exciting light emitting display panel (as: phosphorescence electric exciting light emitting display panel, fluorescence electric exciting light emitting display panel or above-mentioned combination), also be called light-emitting display panel, and its electroluminescence material can be organic material, organic material, inorganic material or above-mentioned combination, moreover the molecular size of above-mentioned material comprises micromolecule, macromolecule or above-mentioned combination.If display medium 642 comprises liquid crystal material and electroluminescence material simultaneously, then display unit 602 is called hybrid (hybrid) display floater or half self-luminescent display floater.
Yet the structure of above-mentioned semiconductor element 200 and manufacture method thereof also can be used on the structure and manufacture method thereof of electrooptical device, and wherein the framework of electrooptical device is shown in Fig. 6 B.Fig. 6 B illustrates the schematic diagram of the electrooptical device of one embodiment of the invention.Please refer to Fig. 6 B, the electrooptical device 600 of present embodiment comprises a display unit 602 and the electronic component 604 that is electrically connected of display unit 602 therewith.The electronic component 604 of present embodiment comprises as control element, executive component, treatment element, input element, memory element, driving element, light-emitting component, protection component, sensing element, detecting element or other function element or aforesaid combination.And the type of electrooptical device 600 comprises the panel in portable product (as mobile phone, video camera, camera, notebook computer, game machine, wrist-watch, music player, electronic mail transceiver, map navigator, digital photo or similar products like), video and audio product (as audio-visual projector or similar products like), screen, TV, billboard, the projector etc.
The manufacture method of semiconductor element of the present invention can be produced the semiconductor element that is made of P-type mos element and N type metal oxide semiconductor element, and wherein P-type mos element and N type metal oxide semiconductor element all have lightly doped drain.Therefore, the short-channel effect of P-type mos element and N type metal oxide semiconductor element all can be improved simultaneously.
In addition, the present invention obtains the lightly doped drain of P-type mos element, the problem of contingent mask bit errors in the time of so can avoiding making lightly doped drain need not carry out effect that the mask contraposition just can reach self-aligned.In brief, the manufacture method of semiconductor element of the present invention not only has preferable technology yields, also can save the cost of making mask.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any this area related personnel, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking appending claims.
Claims (18)
1, a kind of manufacture method of semiconductor element is characterized in that, described method comprises:
On a substrate, form a P-type mos element and a N type metal oxide semiconductor element, wherein said P-type mos element comprises that one first island polysilicon, is covered in gate insulation layer and on the described first island polysilicon and is positioned at first grid on the described gate insulation layer, and described first grid is positioned at described first island polysilicon top, and the manufacture method of described P-type mos element comprises:
On described gate insulation layer and described first grid, form one first patterning photoresist layer, and the described first patterning photoresist layer have a plurality of first openings;
With the described first patterning photoresist layer is photomask, the described first island polysilicon is carried out P type ion inject, to form a plurality of P type heavily doped regions in the described first island polysilicon of part of described a plurality of first openings below;
Remove the described first patterning photoresist layer of part, forming second a patterning photoresist layer with a plurality of second openings, and the size of each described second opening is greater than the size of each described first opening; And
With described first grid and the described second patterning photoresist layer is photomask, the described first island polysilicon is carried out P type ion to be injected, in the described first island polysilicon of another part of described a plurality of second openings below, to form a plurality of P type light doping sections, the described first island polysilicon that is positioned at described first grid below then is used as a channel region, so that described channel region is between described a plurality of P type light doping sections, the length of wherein said channel region is less than 3 microns, and described a plurality of one of them person's of P type light doping section length is 10% to 80% of described channel region.
2, the manufacture method of semiconductor element as claimed in claim 1 is characterized in that, the formation method of the described first island polysilicon comprises:
On described substrate, form an amorphous silicon layer;
Described amorphous silicon layer is carried out a thermal anneal process, so that described amorphous silicon layer is converted to a polysilicon layer; And
The described polysilicon layer of patterning is to form the described first island polysilicon.
3, the manufacture method of semiconductor element as claimed in claim 2 is characterized in that, described thermal anneal process comprises a LASER HEAT annealing process.
4, the manufacture method of semiconductor element as claimed in claim 1 is characterized in that, the method that removes the described first patterning photoresist layer of part comprises ashing.
5, the manufacture method of semiconductor element as claimed in claim 1 is characterized in that, also comprises removing the described second patterning photoresist layer.
6, the manufacture method of semiconductor element as claimed in claim 1, it is characterized in that, described N type metal oxide semiconductor element comprises one second an island polysilicon and a second grid that is positioned on the described gate insulation layer, wherein said second grid is positioned at described second island polysilicon top, and the manufacture method of described N type metal oxide semiconductor element comprises that the described second island polysilicon of part is carried out N type ion to be injected, to form a plurality of N type doped regions.
7, the manufacture method of semiconductor element as claimed in claim 6 is characterized in that, described a plurality of N type doped regions comprise a plurality of N type light doping sections and a plurality of N type heavily doped region.
8, the manufacture method of semiconductor element as claimed in claim 6 is characterized in that, also comprises:
On described first grid, described second grid and described gate insulation layer, form an interlayer dielectric layer;
Described interlayer dielectric layer of patterning and described gate insulation layer are to form a plurality of first contact windows corresponding to described N type doped region and described a plurality of P type heavily doped regions in described interlayer dielectric layer and described gate insulation layer; And
In described a plurality of first contact windows, form the conductor that contacts of a plurality of and described a plurality of N type doped region and described a plurality of P type heavily doped region electrical connections.
9, the manufacture method of semiconductor element as claimed in claim 8 is characterized in that, also comprises:
Form a patterning flatness layer in described interlayer dielectric layer on the conductor with described a plurality of the contact, and have a plurality of second contact windows in the described patterning flatness layer; And
On described patterning flatness layer, form a conductive layer, so that described conductive layer is electrically connected by the described a plurality of conductors that contact of described second contact window and part.
10, the manufacture method of semiconductor element as claimed in claim 8 is characterized in that, also comprises:
Form a conductive layer on the conductor in a plurality of contact of described interlayer dielectric layer and part, so that described conductive layer is electrically connected with the described a plurality of conductors that contact of part.
11, a kind of manufacture method of display unit is characterized in that, comprises manufacture method as claimed in claim 1.
12, a kind of manufacture method of electrooptical device is characterized in that, comprises manufacture method as claimed in claim 1.
13, a kind of semiconductor element is characterized in that, comprising:
One substrate;
At least one P-type mos element, be disposed on the described substrate, and described P-type mos element comprises one first island polysilicon, one is covered in gate insulation layer and on the described first island polysilicon is positioned at first grid on the described gate insulation layer, and described first grid is positioned at described first island polysilicon top, and have a plurality of P type heavily doped regions in the described first island polysilicon, the channel region of a plurality of P type light doping sections and between described a plurality of P type light doping sections, wherein, the length of described channel region is less than 3 microns, and described a plurality of one of them person's of P type light doping section length is 10% to 80% of described channel region; And
At least one N type metal oxide semiconductor element, be disposed on the described substrate, and described N type metal oxide semiconductor element comprises that one second island polysilicon, the described gate insulation layer and that is covered on the described second island polysilicon are positioned at the second grid on the described gate insulation layer, and described second grid is positioned at described second island polysilicon top, and has a plurality of N type heavily doped regions, the channel region of a plurality of N type light doping section and between described a plurality of N type light doping sections in described the two or the two island polysilicon.
14, semiconductor element as claimed in claim 13 is characterized in that, also comprises:
On described first grid, described second grid and described gate insulation layer, form an interlayer dielectric layer, and have a plurality of first contact windows in described interlayer dielectric layer and the described gate insulation layer corresponding to described N type doped region and described a plurality of P type heavily doped regions; And
In described a plurality of first contact windows, form the conductor that contacts of a plurality of and described a plurality of N type doped region and described a plurality of P type heavily doped region electrical connections.
15, semiconductor element as claimed in claim 13 is characterized in that, also comprises:
Form a patterning flatness layer in described interlayer dielectric layer on the conductor with described a plurality of the contact, and have a plurality of second contact windows in the described patterning flatness layer; And
On described patterning flatness layer, form a conductive layer, so that described conductive layer is electrically connected by the described a plurality of conductors that contact of described second contact window and part.
16, semiconductor element as claimed in claim 13 is characterized in that, also comprises:
Form a conductive layer on the conductor in a plurality of contact of described interlayer dielectric layer and part, so that described conductive layer is electrically connected with the described a plurality of conductors that contact of part.
17, a kind of display unit is characterized in that, comprises semiconductor element as claimed in claim 13.
18, a kind of electrooptical device is characterized in that, comprises semiconductor element as claimed in claim 13.
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| CN103165529B (en) | 2013-02-20 | 2015-04-29 | 京东方科技集团股份有限公司 | Preparation method of array baseplate |
| CN103996656A (en) * | 2014-04-30 | 2014-08-20 | 京东方科技集团股份有限公司 | Manufacturing method of display substrate and display substrate |
| US20160284913A1 (en) | 2015-03-27 | 2016-09-29 | Staffan WESTERBERG | Solar cell emitter region fabrication using substrate-level ion implantation |
| CN105161496A (en) | 2015-07-30 | 2015-12-16 | 京东方科技集团股份有限公司 | Thin film transistor array substrate and manufacturing method thereof, and display device |
| CN107946196B (en) * | 2017-11-28 | 2021-12-28 | 合肥鑫晟光电科技有限公司 | Oxide thin film transistor, preparation method thereof, array substrate and display device |
| CN109618953A (en) * | 2019-01-25 | 2019-04-16 | 胡晋玮 | A kind of herding fence and herding method based on wearable device |
| CN110137182A (en) * | 2019-04-04 | 2019-08-16 | 惠科股份有限公司 | A kind of array substrate and its manufacturing method and display panel |
| CN110112099A (en) * | 2019-04-08 | 2019-08-09 | 深圳市华星光电技术有限公司 | The method for making LTPS TFT substrate |
| CN114927532B (en) * | 2022-04-27 | 2023-04-21 | 惠科股份有限公司 | Array substrate, manufacturing method thereof and display panel |
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