CN105489499A - Manufacturing method for LTPS (low temperature poly-silicon) thin film transistor - Google Patents
Manufacturing method for LTPS (low temperature poly-silicon) thin film transistor Download PDFInfo
- Publication number
- CN105489499A CN105489499A CN201510974854.4A CN201510974854A CN105489499A CN 105489499 A CN105489499 A CN 105489499A CN 201510974854 A CN201510974854 A CN 201510974854A CN 105489499 A CN105489499 A CN 105489499A
- Authority
- CN
- China
- Prior art keywords
- layer
- photoresist layer
- insulating barrier
- forms
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 64
- 238000000034 method Methods 0.000 claims abstract description 30
- 150000002500 ions Chemical class 0.000 claims abstract description 28
- 238000000059 patterning Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000004888 barrier function Effects 0.000 claims description 38
- 229920005591 polysilicon Polymers 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 16
- 239000011248 coating agent Substances 0.000 claims description 15
- 238000000576 coating method Methods 0.000 claims description 15
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 238000002425 crystallisation Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 230000008025 crystallization Effects 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- -1 phosphonium ion Chemical class 0.000 claims description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 239000004411 aluminium Substances 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052804 chromium Inorganic materials 0.000 claims description 2
- 239000011651 chromium Substances 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 238000004380 ashing Methods 0.000 abstract 1
- 230000003139 buffering effect Effects 0.000 abstract 1
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a manufacturing method for an LTPS (low temperature poly-silicon) thin film transistor. The manufacturing method comprises the steps of providing a substrate; forming a buffer layer and a poly-silicon layer on the substrate; forming a first photoresist layer on a middle region of the poly-silicon layer by patterning; injecting first ions to first doping regions of the poly-silicon layer; performing patterning on the first photoresist layer through an ashing process to enable the overall area of the first photoresist layer to be reduced to form a second photoresist layer, wherein the partial middle region is covered with the second photoresist layer, so that second doping regions are formed between the middle region and the two first doping regions; injecting second ions to the two second doping regions; forming a first insulating layer on the poly-silicon layer and the uncovered buffering layer; forming a grid electrode on the first insulating layer; forming a second insulating layer on the grid electrode; and forming a source and a drain connected with the first doping regions on the second insulating layer. The overall process of the manufacturing method applies five times of a photomask technology, so that the processing processes and steps are simplified.
Description
Technical field
The present invention relates to the manufacture field of thin-film transistor, particularly relate to a kind of LTPS method for fabricating thin film transistor.
Background technology
Low temperature polycrystalline silicon (lowtemperaturepoly-silicon, referred to as LTPS) Thin Film Transistor-LCD is different from traditional amorphous silicon thin film transistor-liquid crystal display, its electron mobility can reach more than 200cm2/V-sec, the area of film transistor device can be effectively reduced, thus reach raising aperture opening ratio, and overall power consumption can also be reduced while promoting display brightness.In addition, higher electron mobility can be on the glass substrate integrated by section driving circuit, decreases drive IC, significantly can also promote the reliability of display panels, thus the manufacturing cost of panel is significantly reduced.Therefore, LTPS Thin Film Transistor-LCD progressively becomes the focus of research.
But at present due in the making of LTPS thin-film transistor, because semiconductor regions is shorter and shorter, short-channel effect is more obvious.Short-channel effect causes NTFT characteristic abnormal, and as bigger than normal in Vth, offcurrent is higher, and in order to avoid this type of is abnormal, General N TFT makes all can increase and decrease one section of lightly doped region N-(LDD) between N+ and raceway groove.
Making in whole technological process at traditional LTPS thin-film transistor, need to utilize photoresist to be completed by twice light shield when injecting N+, N-ion, and the whole manufacturing process of LTPS thin-film transistor needing 6 road light shields altogether, so increases manufacturing cost.
Summary of the invention
The invention provides a kind of LTPS method for fabricating thin film transistor, can simplified manufacturing technique, reduce costs.
LTPS method for fabricating thin film transistor of the present invention comprises, and provides a substrate, and forms resilient coating on the substrate;
On described resilient coating, patterning forms polysilicon layer;
The zone line of described polysilicon layer forms the first photoresist layer by patterning, and polysilicon layer is divided into zone line and is positioned at the first doped region of the relative both sides of zone line; The cross section of wherein said first photoresist layer is isosceles trapezoid, and its surface contacted with described zone line is trapezoidal bottom surface;
The first ion is injected two described first doped regions;
By cineration technics, patterning is carried out to described first photoresist layer, make described first photoresist layer entire area reduce formation second photoresist layer; Wherein, zone line described in described second photoresist layer cover part, makes to form the second doped region between described zone line and two described first doped regions;
The second ion is injected two described second doped regions;
Described polysilicon layer and exposed resilient coating form the first insulating barrier;
Described first insulating barrier forms the first metal layer and patterned first metal layer formation grid,
Described grid is formed and the first exposed insulating barrier forms the second insulating barrier;
Via hole is formed by being patterned on described first insulating barrier and the second insulating barrier; Described via hole is relative with two described first doped regions,
Form source electrode and drain electrode by being patterned on described second insulating barrier, wherein, source electrode is connected with described first doped region by described via hole with drain electrode.
Wherein, the step of described " patterning forms polysilicon layer on described resilient coating " comprises deposition of amorphous silicon layers on the buffer layer, realizes crystallization and form polysilicon layer to amorphous silicon layer by radium-shine crystallisation, and the step to polysilicon layer pattern.
Wherein, described " by cineration technics, patterning being carried out to described first photoresist layer; make described first photoresist layer entire area reduce formation second photoresist layer; " step in, described first photoresist layer entire area reduces to refer to that the surrounding of the first photoresist layer and top are all removed a part by light shield and etching, and forms the second photoresist layer of small volume.
Wherein, the step of described " forming via hole by being patterned on described first insulating barrier and the second insulating barrier " comprises,
The photoresist layer being formed patterning by light shield on described second insulating barrier forms via hole position;
Remove described photoresist layer by etching and first, second insulating barrier corresponding to described via hole position is carried out to etching and form described via hole; Described via hole correspondence position is described first doped region.
Wherein, described first ion and the second ion are N-type ion, and the concentration of described first ion is greater than the concentration of the second ion.
Wherein, described N-type ion is phosphonium ion.
Wherein, the material of described resilient coating is selected from silicon oxide layer, silicon nitride layer, one of them of silicon oxynitride layer and combination thereof.
Wherein, the material of described the first metal layer be selected from copper, tungsten, chromium, aluminium and combination thereof one of them.
Wherein, step " forms source electrode and drain electrode by being patterned on described second insulating barrier " and comprises and forms metal level over the second dielectric, wherein metal level fills up described via hole, forms the described source electrode corresponding with via hole and drain electrode by arranging photoresist layer patterned metal layer.
Method for fabricating thin film transistor of the present invention is reduced by its volume by cineration technics the first photoresist layer of definition first doped region and re-uses and define the second doped region, lessly once remove the first photoresist layer and lay the operation of the second photoresist layer, save one light shield, simplify the processing technology step of thin-film transistor, reduce the cost of manufacture of thin-film transistor.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the flow chart of the manufacture method of the LTPS thin-film transistor of better embodiment of the present invention.
Fig. 2 to Fig. 8 is the profile of thin-film transistor in each manufacturing process of the LTPS thin-film transistor of better embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Refer to Fig. 1, shown in figure is the flow chart of the LTPS method for fabricating thin film transistor of better embodiment of the present invention, and LTPS method for fabricating thin film transistor of the present invention comprises the steps,
Refer to Fig. 2, step S1, a substrate 10 is provided, and form resilient coating 11 by depositional mode on the substrate.In the present embodiment, described substrate 10 is glassy layer.
In the present embodiment, the material of described resilient coating 11 is selected from silicon oxide layer, silicon nitride layer, one of them of silicon oxynitride layer and combination thereof.
Refer to Fig. 3, step S2, on described resilient coating 11, patterning forms polysilicon layer 12, and described polysilicon layer 12 forms the active layer of LTPS thin-film transistor of the present invention, particularly carries out etching the active layer that development forms LTPS thin-film transistor to polysilicon layer 12 by first light shield.
This step is specially, 11 deposition of amorphous silicon layers on described resilient coating, to amorphous silicon layer by the crystallization of radium-shine crystallisation realization to amorphous silicon layer, and the amorphous silicon layer pattern to crystallization, the polysilicon layer 12 described in final formation.Wherein, the amorphous silicon layer of patterning crystallization refers to and adopts the mode processing mode such as light shield, etching development; And described light shield is the first light shield used in this method.This masking techniques is this area common technology, does not again repeat.
Refer to Fig. 4, step S3, the zone line of described polysilicon layer 12 forms the first photoresist layer 13 by patterning, thus polysilicon layer 12 is divided into zone line 121 and is positioned at the first doped region 122 of the relative both sides of zone line 121.In the present embodiment, the cross section of described first photoresist layer 13 is isosceles trapezoid, and its surface contacted with described zone line 121 is trapezoidal bottom surface.Described first photoresist layer 13 is formed by Other substrate materials, specifically adopts the mode such as light shield, etching by the photoresist formed with on described polysilicon layer 12 is processed into the first described photoresist layer 13.Wherein said light shield is the second light shield used in this method.
Refer to Fig. 5, step S4, inject the first ion two described first doped regions 122.In the present embodiment, described first ion is N-type ion.In the present embodiment, described N-type ion is phosphonium ion.
Refer to Fig. 6, step S5, by cineration technics, patterning is carried out to described first photoresist layer 13, make described first photoresist layer 13 entire area reduce formation second photoresist layer 14; Wherein, zone line 121 described in described second photoresist layer 14 cover part, makes to form the second doped region 123 between described zone line 121 and two described first doped regions 122.
Concrete, described first photoresist layer 13 entire area reduces to refer to that the surrounding of the first photoresist layer and top are all removed a part by light shield and etching, and forms the second photoresist layer of small volume.That is the leakage of described first photoresist layer 13 is all removed channel floor in the position of outside and reduces to the first photoresist layer center position.Etching mode in described cineration technics adopts dry ecthing.This cineration technics is this area common technology, does not again repeat.
Refer to Fig. 7, step S6, inject the second ion two described second doped regions 123.In the present embodiment, described first ion is N-type ion.The concentration of described first ion is greater than the concentration of the second ion.
Above-described first photoresist layer and the second photoresist layer are all removed after injection ion.
Refer to Fig. 8, step S7, described polysilicon layer 12 and exposed resilient coating 11 form the first insulating barrier 15.
Step S8, described first insulating barrier 15 forms the first metal layer and patterned first metal layer forms grid 16.Described grid 16 is formed and the first exposed insulating barrier 15 forms the second insulating barrier 17.Patterned first metal layer in this step refers to and adopts the mode processing mode such as light shield, etching development; And described light shield is the 3rd road light shield used in this method.First insulating barrier 15 and the second insulating barrier 17 described in the present embodiment adopt silica (SiOx), silicon nitride (SiNx) to make with the one in silicon oxynitride (SiNxOy).
Step S9, forms via hole by being patterned on described first insulating barrier 15 and the second insulating barrier 17; Described via hole is relative with two described first doped regions 122.Concrete is that the photoresist layer that S901 forms patterning by light shield on described second insulating barrier forms via hole position;
S902, removes described photoresist layer by etching and first, second insulating barrier corresponding to described via hole position is carried out to the described via hole of etching formation; Described via hole correspondence position is described first doped region.
Patterning first insulating barrier 15 in this step and the second insulating barrier 17 refer to and adopt the mode processing mode such as light shield, etching development to form described via hole; And described light shield is the 4th road light shield used in this method.
Step S10, form source electrode 18 and drain electrode 19 by being patterned on described second insulating barrier 17, wherein, source electrode 18 is connected with described first doped region 122 by described via hole with drain electrode 19.In this step, patterning refers to mode processing modes such as adopting light shield etching development.Described light shield is the 5th road light shield used in this method.This step is included on the second insulating barrier 17 and forms metal level, and wherein metal level fills up described via hole, forms the described source electrode 18 corresponding with via hole and drain electrode 19 by arranging photoresist layer patterned metal layer.
Method for fabricating thin film transistor of the present invention is reduced by its volume by cineration technics the first photoresist layer of definition first doped region 122 and re-uses and define the second doped region, lessly once remove the first photoresist layer and lay the operation of the second photoresist layer, save one light shield, the employing five road light shield of integrated artistic, forming two photoresist layers by twice light shield and define the mode that two are mixed district respectively compared to prior art, save light shield number of times, simplify the processing technology step of thin-film transistor, reduce the cost of manufacture of thin-film transistor.
By the display device that the manufacture method of embodiment of the present invention thin-film transistor is formed, Ke Yiwei: liquid crystal panel, LCD TV, liquid crystal display, oled panel, OLED TV, Electronic Paper, DPF, mobile phone etc.
Above disclosedly be only a kind of preferred embodiment of the present invention, certainly the interest field of the present invention can not be limited with this, one of ordinary skill in the art will appreciate that all or part of flow process realizing above-described embodiment, and according to the equivalent variations that the claims in the present invention are done, still belong to the scope that invention is contained.
Claims (10)
1. a LTPS method for fabricating thin film transistor, is characterized in that, described method comprises, and provides a substrate, and forms resilient coating on the substrate;
On described resilient coating, patterning forms polysilicon layer;
The centre position of described polysilicon layer forms the first photoresist layer by patterning, and polysilicon layer is divided into zone line and is positioned at the first doped region of the relative both sides of zone line by the first photoresist layer;
The first ion is injected two described first doped regions;
By cineration technics, patterning is carried out to described first photoresist layer, make described first photoresist layer entire area reduce formation second photoresist layer; Wherein, zone line described in described second photoresist layer cover part, makes to form the second doped region between described zone line and two described first doped regions;
The second ion is injected two described second doped regions;
Described polysilicon layer and exposed resilient coating form the first insulating barrier;
Described first insulating barrier forms the first metal layer and patterned first metal layer formation grid; And formed on described grid and the first exposed insulating barrier forms the second insulating barrier;
Via hole is formed by being patterned on described first insulating barrier and the second insulating barrier; Described via hole is relative with two described first doped regions;
Form source electrode and drain electrode by being patterned on described second insulating barrier, wherein, source electrode is connected with described first doped region by described via hole with drain electrode.
2. LTPS method for fabricating thin film transistor as claimed in claim 1, it is characterized in that, the cross section of described first photoresist layer is isosceles trapezoid, and the surface that described first photoresist layer contacts with described zone line is trapezoidal bottom surface.
3. LTPS method for fabricating thin film transistor as claimed in claim 1 or 2, it is characterized in that, the step of described " patterning forms polysilicon layer on described resilient coating " comprises deposition of amorphous silicon layers on the buffer layer, to the crystallization that amorphous silicon layer realizes amorphous silicon layer by radium-shine crystallisation, and the step of amorphous silicon layer pattern to crystallization.
4. LTPS method for fabricating thin film transistor as claimed in claim 3, it is characterized in that, described " by cineration technics, patterning being carried out to described first photoresist layer; make described first photoresist layer entire area reduce formation second photoresist layer; " step in, described first photoresist layer entire area reduces to refer to that the surrounding of the first photoresist layer and top are all removed a part by light shield and etching, and forms the second photoresist layer of small volume.
5. LTPS method for fabricating thin film transistor as claimed in claim 1 or 2, it is characterized in that, the step of described " forming via hole by being patterned on described first insulating barrier and the second insulating barrier " comprises,
The photoresist layer being formed patterning by light shield on described second insulating barrier forms via hole position;
Remove described photoresist layer by etching and first, second insulating barrier corresponding to described via hole position is carried out to etching and form described via hole; Described via hole correspondence position is described first doped region.
6. LTPS method for fabricating thin film transistor as claimed in claim 1 or 2, it is characterized in that, described first ion and the second ion are N-type ion, and the concentration of described first ion is greater than the concentration of the second ion.
7. LTPS method for fabricating thin film transistor as claimed in claim 6, it is characterized in that, described N-type ion is phosphonium ion.
8. manufacturing method of array base plate as claimed in claim 1, it is characterized in that, the material of described resilient coating is selected from silicon oxide layer, silicon nitride layer, one of them of silicon oxynitride layer and combination thereof.
9. manufacturing method of array base plate as claimed in claim 1, is characterized in that, the material of described the first metal layer be selected from copper, tungsten, chromium, aluminium and combination thereof one of them.
10. manufacturing method of array base plate as claimed in claim 1, it is characterized in that, step " forms source electrode and drain electrode by being patterned on described second insulating barrier " and comprises and forms metal level over the second dielectric, wherein metal level fills up described via hole, forms the described source electrode corresponding with via hole and drain electrode by arranging photoresist layer patterned metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510974854.4A CN105489499B (en) | 2015-12-21 | 2015-12-21 | LTPS method for fabricating thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510974854.4A CN105489499B (en) | 2015-12-21 | 2015-12-21 | LTPS method for fabricating thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105489499A true CN105489499A (en) | 2016-04-13 |
| CN105489499B CN105489499B (en) | 2018-12-07 |
Family
ID=55676406
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510974854.4A Active CN105489499B (en) | 2015-12-21 | 2015-12-21 | LTPS method for fabricating thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105489499B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11908949B2 (en) | 2018-02-28 | 2024-02-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002033273A (en) * | 2000-05-12 | 2002-01-31 | Semiconductor Energy Lab Co Ltd | Manufacturing method of semiconductor device |
| TW480728B (en) * | 2001-02-02 | 2002-03-21 | Hannstar Display Corp | Polysilicon thin film transistor structure and the manufacturing method thereof |
| CN1375113A (en) * | 1999-09-16 | 2002-10-16 | 松下电器产业株式会社 | Thin-film transistor and method for producing the same |
| KR100534581B1 (en) * | 2003-05-16 | 2005-12-07 | 삼성에스디아이 주식회사 | Method of fabricating a thin film transister having a GOLD structure |
| US20050272186A1 (en) * | 2004-06-08 | 2005-12-08 | Te-Ming Chu | Method for forming a lightly doped drain in a thin film transistor |
| CN104779168A (en) * | 2015-04-13 | 2015-07-15 | 武汉华星光电技术有限公司 | Method for producing thin-film transistor |
| CN105161459A (en) * | 2015-09-07 | 2015-12-16 | 武汉华星光电技术有限公司 | Low temperature poly-silicon array substrate and manufacturing method therefor |
-
2015
- 2015-12-21 CN CN201510974854.4A patent/CN105489499B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1375113A (en) * | 1999-09-16 | 2002-10-16 | 松下电器产业株式会社 | Thin-film transistor and method for producing the same |
| JP2002033273A (en) * | 2000-05-12 | 2002-01-31 | Semiconductor Energy Lab Co Ltd | Manufacturing method of semiconductor device |
| TW480728B (en) * | 2001-02-02 | 2002-03-21 | Hannstar Display Corp | Polysilicon thin film transistor structure and the manufacturing method thereof |
| KR100534581B1 (en) * | 2003-05-16 | 2005-12-07 | 삼성에스디아이 주식회사 | Method of fabricating a thin film transister having a GOLD structure |
| US20050272186A1 (en) * | 2004-06-08 | 2005-12-08 | Te-Ming Chu | Method for forming a lightly doped drain in a thin film transistor |
| CN104779168A (en) * | 2015-04-13 | 2015-07-15 | 武汉华星光电技术有限公司 | Method for producing thin-film transistor |
| CN105161459A (en) * | 2015-09-07 | 2015-12-16 | 武汉华星光电技术有限公司 | Low temperature poly-silicon array substrate and manufacturing method therefor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11908949B2 (en) | 2018-02-28 | 2024-02-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| JP7493567B2 (en) | 2018-02-28 | 2024-05-31 | 株式会社半導体エネルギー研究所 | Method for manufacturing a semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105489499B (en) | 2018-12-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5650879B2 (en) | Display having thin film transistor device having different electrical characteristics of pixel and driving region, and manufacturing method thereof | |
| US7344931B2 (en) | Semiconductor device, method of manufacturing the same, and electro-optical device | |
| KR101226974B1 (en) | Array substrate for liquid crystal display device and method of fabricating the same | |
| KR102080732B1 (en) | Low-temperature polycrystalline silicon thin-film transistor based on dual-gate structure and manufacturing method therefor | |
| WO2016101719A1 (en) | Array substrate, manufacturing method thereof and display device | |
| WO2017020358A1 (en) | Low-temperature polycrystalline silicon thin film transistor and manufacture method thereof | |
| JP2010003910A (en) | Display element | |
| CN101656233B (en) | Method for manufacturing thin film transistor substrate | |
| US10409115B2 (en) | Liquid crystal display panel, array substrate and manufacturing method thereof | |
| US10978495B2 (en) | Array substrate and method of manufacturing the same, and display device | |
| CN105470267A (en) | Array substrate and fabrication method thereof | |
| CN102651403A (en) | Thin film transistor, array substrate and manufacturing method of array substrate and display panel | |
| CN110634804A (en) | Array substrate, preparation method thereof and touch display panel | |
| WO2016157313A1 (en) | Thin-film transistor and display panel | |
| CN110620119A (en) | Array substrate and preparation method thereof | |
| US11152490B2 (en) | Array substrate and method for manufacturing same | |
| CN108447822A (en) | The production method of LTPS TFT substrates | |
| CN108565247B (en) | Manufacturing method of LTPS TFT substrate and LTPS TFT substrate | |
| US10957721B1 (en) | Manufacturing method for CMOS LTPS TFT substrate | |
| US10340365B2 (en) | Method of manufacturing a thin film transistor | |
| US20130077012A1 (en) | Semiconductor device and method for manufacturing the same, and liquid crystal display device | |
| CN105489499A (en) | Manufacturing method for LTPS (low temperature poly-silicon) thin film transistor | |
| CN113871483B (en) | Thin film transistor, display substrate and display device | |
| CN102222644A (en) | Method for manufacturing active matrix organic light-emitting diode (AMOLED) apparatus | |
| US10749037B2 (en) | Low temperature poly-silicon TFT substrate and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |