CN105489499B - LTPS method for fabricating thin film transistor - Google Patents
LTPS method for fabricating thin film transistor Download PDFInfo
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- CN105489499B CN105489499B CN201510974854.4A CN201510974854A CN105489499B CN 105489499 B CN105489499 B CN 105489499B CN 201510974854 A CN201510974854 A CN 201510974854A CN 105489499 B CN105489499 B CN 105489499B
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- 239000010409 thin film Substances 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 64
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 229920005591 polysilicon Polymers 0.000 claims abstract description 24
- 238000000059 patterning Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 6
- 150000002500 ions Chemical class 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 13
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 11
- 238000002425 crystallisation Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 230000008025 crystallization Effects 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- -1 phosphonium ion Chemical class 0.000 claims description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 239000004411 aluminium Substances 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052804 chromium Inorganic materials 0.000 claims description 2
- 239000011651 chromium Substances 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 description 12
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 238000011161 development Methods 0.000 description 4
- 230000018109 developmental process Effects 0.000 description 4
- 238000003672 processing method Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention provides LTPS method for fabricating thin film transistor, including, one substrate is provided, and forms buffer layer, polysilicon layer on the substrate, pass through patterning the first photoresist layer of formation on the intermediate region of the polysilicon layer, and inject the first ion in the first doped region of polysilicon layer；First photoresist layer is patterned by cineration technics, the first photoresist layer entire area is made to reduce to form the second photoresist layer；Wherein, intermediate region described in the second photoresist layer covering part makes to constitute the second doped region between the intermediate region and two first doped regions；The second ion is injected in two second doped regions；The first insulating layer is formed on the polysilicon layer and exposed buffer layer；Grid is formed on the first insulating layer；Second insulating layer is formed on the grid；It is formed on the second insulating layer and connect source electrode and drain electrode with first doped region.Five light shield of use of integrated artistic simplifies processing technology step.
Description
Technical field
The present invention relates to the manufacturing field of thin film transistor (TFT) more particularly to a kind of LTPS method for fabricating thin film transistor.
Background technique
Low temperature polycrystalline silicon (low temperature poly-silicon, referred to as LTPS) thin film transistor liquid crystal display
Device is different from traditional amorphous silicon thin film transistor-liquid crystal display, electron mobility can achieve 200cm2/V-sec with
On, the area of film transistor device can be effectively reduced, to reach raising aperture opening ratio, and is promoting the same of display brightness
When can also reduce whole power consumption.In addition, section driving circuit can be integrated in glass substrate by higher electron mobility
On, reduce driving IC, the reliability of liquid crystal display panel can also be substantially improved, so that the manufacturing cost of panel is substantially
It reduces.Therefore, LTPS Thin Film Transistor-LCD gradually has become a hot topic of research.
But at present since in the production of LTPS thin film transistor (TFT), because semiconductor regions are shorter and shorter, short-channel effect is more
Obviously.Short-channel effect causes NTFT characteristic abnormal, such as Vth is bigger than normal, off current is higher, in order to avoid such exception,
General N TFT production can increase and decrease one section of lightly doped region N- (LDD) between N+ and channel.
It is made in entire process flow in traditional LTPS thin film transistor (TFT), needs to utilize light when injecting N+, N- ion
Photoresist is completed by twice light shield, and the entire manufacturing process of LTPS thin film transistor (TFT) needs 6 light shields altogether, so increase manufacture at
This.
Summary of the invention
The present invention provides a kind of LTPS method for fabricating thin film transistor, can simplify manufacturing process, reduce cost.
LTPS method for fabricating thin film transistor of the present invention includes providing a substrate, and formed on the substrate slow
Rush layer；
Patterning forms polysilicon layer on the buffer layer；
The first photoresist layer is formed by patterning on the intermediate region of the polysilicon layer, and polysilicon layer is divided into
Between region and the first doped region positioned at intermediate region opposite sides；Wherein the section of first photoresist layer is isosceles trapezoid,
Its surface contacted with the intermediate region is trapezoidal bottom surface；
The first ion is injected in two first doped regions；
First photoresist layer is patterned by cineration technics, the first photoresist layer entire area is made to reduce shape
At the second photoresist layer；Wherein, intermediate region described in the second photoresist layer covering part makes described in the intermediate region and two
The second doped region is constituted between first doped region；
The second ion is injected in two second doped regions；
The first insulating layer is formed on the polysilicon layer and exposed buffer layer；
The first metal layer is formed on the first insulating layer and patterned first metal layer forms grid,
Second insulating layer is formed on formation and the first exposed insulating layer on the grid；
Via hole is formed by being patterned in first insulating layer and second insulating layer；The via hole and two described
One doped region is opposite,
Source electrode and drain electrode are formed on the second insulating layer by patterning, wherein source electrode and drain electrode pass through the mistake
Hole is connect with first doped region.
Wherein, the step of described " forming polysilicon layer in patterning on the buffer layer ", is non-including depositing on the buffer layer
Crystal silicon layer realizes that crystallization forms polysilicon layer by radium-shine crystallisation to amorphous silicon layer, and to the step of polysilicon layer pattern
Suddenly.
Wherein, described " first photoresist layer to be patterned by cineration technics, keeps first photoresist layer whole
Area reduces to form the second photoresist layer, " the step of in, the first photoresist layer entire area reduces the week for referring to the first photoresist layer
It encloses and top passes through light shield and etching is removed a part, and form the second photoresist layer of small volume.
Wherein, the step of described " forming via hole by being patterned in first insulating layer and second insulating layer ", wraps
It includes,
It forms patterned photoresist layer on the second insulating layer by light shield and formed hole location；
The photoresist layer is removed by etching and shape is etched to the first, second insulating layer corresponding to the hole location excessively
At the via hole；The via hole corresponding position is first doped region.
Wherein, first ion and the second ion are N-type ion, and the concentration of first ion is greater than the second ion
Concentration.
Wherein, the N-type ion is phosphonium ion.
Wherein, the material of the buffer layer be selected from silicon oxide layer, silicon nitride layer, silicon oxynitride layer and combinations thereof wherein it
One.
Wherein, the material of the first metal layer is selected from one of copper, tungsten, chromium, aluminium and combinations thereof.
Wherein, step " forming source electrode and drain electrode on the second insulating layer by patterning " is included in second insulating layer
Upper formation metal layer, wherein metal layer fills up the via hole, is formed by setting photoresist layer patterned metal layer corresponding with via hole
The source electrode and drain electrode.
Method for fabricating thin film transistor of the invention is to pass through cineration technics to the first photoresist layer for defining the first doped region
Its volume is reduced and is re-used to define the second doped region, the first photoresist layer of less primary removal and be laid with the second photoresist layer
Process, save one of light shield, simplify the processing technology step of thin film transistor (TFT), reduce the cost of manufacture of thin film transistor (TFT).
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is the flow chart of the manufacturing method of the LTPS thin film transistor (TFT) of better embodiment of the present invention.
Fig. 2 to Fig. 8 is film crystal in each manufacturing process of the LTPS thin film transistor (TFT) of better embodiment of the present invention
The sectional view of pipe.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Referring to Fig. 1, shown in figure is the stream of the LTPS method for fabricating thin film transistor of better embodiment of the present invention
Cheng Tu, LTPS method for fabricating thin film transistor of the invention include the following steps,
Referring to Fig. 2, step S1, provides a substrate 10, and buffer layer 11 is formed by depositional mode on the substrate.
In the present embodiment, the substrate 10 is glassy layer.
In the present embodiment, the material of the buffer layer 11 is selected from silicon oxide layer, silicon nitride layer, silicon oxynitride layer and combinations thereof
One of.
Referring to Fig. 3, step S2, patterning forms polysilicon layer 12, the polysilicon layer 12 on the buffer layer 11
The active layer of LTPS thin film transistor (TFT) of the present invention is constituted, particularly polysilicon layer 12 is lost by first of light shield
Carve the active layer that development forms LTPS thin film transistor (TFT).
This step specifically, on the buffer layer 11 deposition of amorphous silicon layers, it is real by radium-shine crystallisation to amorphous silicon layer
Now to the crystallization of amorphous silicon layer, and to the amorphous silicon layer pattern of crystallization, the polysilicon layer 12 is ultimately formed.Wherein, scheme
The amorphous silicon layer of caseization crystallization refers to using modes processing methods such as light shield, etching developments；And the light shield is in this method
First of the light shield used.The masking techniques are technology commonly used in the art, are not repeated them here again.
Referring to Fig. 4, step S3, forms the first photoresist layer by patterning on the intermediate region of the polysilicon layer 12
13, so that polysilicon layer 12 is divided into intermediate region 121 and positioned at the first doped region 122 of 121 opposite sides of intermediate region.This
In embodiment, the section of first photoresist layer 13 is isosceles trapezoid, and the surface contacted with the intermediate region 121 is trapezoidal
Bottom surface.First photoresist layer 13 is formed by Other substrate materials, and specifically being passed through using the modes such as light shield, etching will form and institute
It states the photoresist on polysilicon layer 12 and is processed into first photoresist layer 13.Wherein the light shield is the used in this method
Two light shields.
Referring to Fig. 5, step S4, injects the first ion in two first doped regions 122.It is described in the present embodiment
First ion is N-type ion.In the present embodiment, the N-type ion is phosphonium ion.
Referring to Fig. 6, step S5, patterns first photoresist layer 13 by cineration technics, makes described first
13 entire area of photoresist layer reduces to form the second photoresist layer 14；Wherein, middle area described in 14 covering part of the second photoresist layer
Domain 121 makes to constitute the second doped region 123 between the intermediate region 121 and two first doped regions 122.
Specifically, 13 entire area of the first photoresist layer reduction refers to around the first photoresist layer and top passes through light
Cover and etching are removed a part, and form the second photoresist layer of small volume.That is the leakage of first photoresist layer 13
It is whole to the reduction of the first photoresist layer center position that part is removed in external position.Etching mode in the cineration technics
Using dry ecthing.The cineration technics is technology commonly used in the art, is not repeated them here again.
Referring to Fig. 7, step S6, injects the second ion in two second doped regions 123.It is described in the present embodiment
First ion is N-type ion.The concentration of first ion is greater than the concentration of the second ion.
Above-described first photoresist layer and the second photoresist layer remove after injecting ion.
Referring to Fig. 8, step S7, forms the first insulating layer 15 on the polysilicon layer 12 and exposed buffer layer 11.
Step S8, forms the first metal layer on first insulating layer 15 and patterned first metal layer forms grid
16.Second insulating layer 17 is formed on formation and the first exposed insulating layer 15 on the grid 16.Patterning in this step
The first metal layer refers to using modes processing methods such as light shield, etching developments；And the light shield is the used in this method
Three light shields.First insulating layer 15 described in the present embodiment uses silica (SiOx), silicon nitride with second insulating layer 17
(SiNx) it is made with one of silicon oxynitride (SiNxOy).
Step S9 forms via hole by being patterned in first insulating layer 15 and second insulating layer 17；The via hole
It is opposite with two first doped regions 122.It is specifically that S901 forms patterning by light shield on the second insulating layer
Photoresist layer formed hole location；
S902 removes the photoresist layer by etching and crosses the progress of the first, second insulating layer corresponding to hole location to described
Etching forms the via hole；The via hole corresponding position is first doped region.
The first insulating layer of patterning 15 and second insulating layer 17 in this step refer to using modes such as light shield, etching developments
Processing method forms the via hole；And the light shield is the 4th light shield used in this method.
Step S10 forms source electrode 18 and drain electrode 19 by being patterned in the second insulating layer 17, wherein source electrode 18
It is connect by the via hole with first doped region 122 with drain electrode 19.Patterning refers to aobvious using light shield etching in this step
The modes processing method such as shadow.The light shield is the 5th light shield used in this method.This step is included in second insulating layer 17
Upper formation metal layer, wherein metal layer fills up the via hole, is formed by setting photoresist layer patterned metal layer corresponding with via hole
The source electrode 18 and drain electrode 19.
Method for fabricating thin film transistor of the invention is to pass through grey chemical industry to the first photoresist layer for defining the first doped region 122
Its volume is reduced and is re-used to define the second doped region by skill, the first photoresist layer of less primary removal and be laid with the second photoresist
The process of layer, saves one of light shield, five light shield of use of integrated artistic, compared to the prior art pass through light shield shape twice
It defines two modes for mixing area respectively at two photoresist layers, saves light shield number, simplify the processing work of thin film transistor (TFT)
Skill step reduces the cost of manufacture of thin film transistor (TFT).
The display device that the manufacturing method of thin film transistor (TFT) is formed through the embodiment of the present invention, can be with are as follows: liquid crystal display panel, liquid
Brilliant TV, liquid crystal display, oled panel, OLED TV, Electronic Paper, Digital Frame, mobile phone etc..
Above disclosed is only a preferred embodiment of the present invention, cannot limit the power of the present invention with this certainly
Sharp range, those skilled in the art can understand all or part of the processes for realizing the above embodiment, and weighs according to the present invention
Benefit requires made equivalent variations, still belongs to the scope covered by the invention.
Claims (9)
1. a kind of LTPS method for fabricating thin film transistor, which is characterized in that the method includes providing a substrate, and described
Buffer layer is formed on substrate；
Patterning forms polysilicon layer on the buffer layer；
The first photoresist layer is formed by patterning on the middle position of the polysilicon layer, the first photoresist layer divides polysilicon layer
At intermediate region and positioned at the first doped region of intermediate region opposite sides；The section of first photoresist layer is isosceles trapezoid,
The surface that first photoresist layer is contacted with the intermediate region is trapezoidal bottom surface；
The first ion is injected in two first doped regions；
First photoresist layer is patterned by cineration technics, the first photoresist layer entire area is made to reduce to form
Two photoresist layers；Wherein, intermediate region described in the second photoresist layer covering part, makes the intermediate region and two described first
The second doped region is constituted between doped region；
The second ion is injected in two second doped regions；
The first insulating layer is formed on the polysilicon layer and exposed buffer layer；
The first metal layer is formed on the first insulating layer and patterned first metal layer forms grid；And on the grid
Second insulating layer is formed on formation and the first exposed insulating layer；
Via hole is formed by being patterned in first insulating layer and second insulating layer；The via hole is mixed with two described first
Miscellaneous area is opposite；
Pass through patterning and form source electrode and drain electrode on the second insulating layer, wherein source electrode and drain electrode by the via hole with
The first doped region connection.
2. LTPS method for fabricating thin film transistor as described in claim 1, which is characterized in that described " on the buffer layer
Patterning forms polysilicon layer " the step of include deposition of amorphous silicon layers on the buffer layer, radium-shine crystallisation is passed through to amorphous silicon layer
Realize the crystallization to amorphous silicon layer, and the step of to the amorphous silicon layer pattern of crystallization.
3. LTPS method for fabricating thin film transistor as claimed in claim 2, which is characterized in that described " to pass through cineration technics pair
First photoresist layer is patterned, and the first photoresist layer entire area is made to reduce to form the second photoresist layer, " the step of
In, the first photoresist layer entire area reduction refers to around the first photoresist layer and top passes through light shield and etching is removed
A part, and form the second photoresist layer of small volume.
4. LTPS method for fabricating thin film transistor as described in claim 1, which is characterized in that described " by being patterned in
State and form via hole in the first insulating layer and second insulating layer " the step of include,
It forms patterned photoresist layer on the second insulating layer by light shield and formed hole location；
The photoresist layer is removed by etching and the first, second insulating layer corresponding to the hole location excessively is etched to form institute
State via hole；The via hole corresponding position is first doped region.
5. LTPS method for fabricating thin film transistor as described in claim 1, which is characterized in that first ion and second from
Son is N-type ion, and the concentration of first ion is greater than the concentration of the second ion.
6. LTPS method for fabricating thin film transistor as claimed in claim 5, which is characterized in that the N-type ion is phosphonium ion.
7. LTPS method for fabricating thin film transistor as described in claim 1, which is characterized in that the material of the buffer layer is selected from
Silicon oxide layer, silicon nitride layer, one of silicon oxynitride layer and combinations thereof.
8. LTPS method for fabricating thin film transistor as described in claim 1, which is characterized in that the material of the first metal layer
Selected from one of copper, tungsten, chromium, aluminium and combinations thereof.
9. LTPS method for fabricating thin film transistor as described in claim 1, which is characterized in that step is " by being patterned in
State and form source electrode and drain electrode in second insulating layer " it include forming metal layer over the second dielectric, wherein metal layer fills up described
Via hole forms the source electrode corresponding with via hole and drain electrode by setting photoresist layer patterned metal layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW480728B (en) * | 2001-02-02 | 2002-03-21 | Hannstar Display Corp | Polysilicon thin film transistor structure and the manufacturing method thereof |
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| CN1375113A (en) * | 1999-09-16 | 2002-10-16 | 松下电器产业株式会社 | Thin-film transistor and method for producing the same |
| JP4651851B2 (en) * | 2000-05-12 | 2011-03-16 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| KR100534581B1 (en) * | 2003-05-16 | 2005-12-07 | 삼성에스디아이 주식회사 | Method of fabricating a thin film transister having a GOLD structure |
| US7163868B2 (en) * | 2004-06-08 | 2007-01-16 | Chunghwa Picture Tubes, Ltd. | Method for forming a lightly doped drain in a thin film transistor |
| CN104779168B (en) * | 2015-04-13 | 2018-01-12 | 武汉华星光电技术有限公司 | Method for making thin film transistor (TFT) |
| CN105161459B (en) * | 2015-09-07 | 2019-01-29 | 武汉华星光电技术有限公司 | Low temperature polycrystalline silicon array substrate and preparation method thereof |
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