CN111584521B - Array substrate, manufacturing method thereof and display panel - Google Patents

Array substrate, manufacturing method thereof and display panel Download PDF

Info

Publication number
CN111584521B
CN111584521B CN202010447754.7A CN202010447754A CN111584521B CN 111584521 B CN111584521 B CN 111584521B CN 202010447754 A CN202010447754 A CN 202010447754A CN 111584521 B CN111584521 B CN 111584521B
Authority
CN
China
Prior art keywords
layer
source electrode
metal oxide
substrate
oxide pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010447754.7A
Other languages
Chinese (zh)
Other versions
CN111584521A (en
Inventor
黄学勇
赵亚雄
李广圣
蒋雷
李向峰
朱成顺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chengdu BOE Display Technology Co Ltd
Original Assignee
Chengdu BOE Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chengdu BOE Display Technology Co Ltd filed Critical Chengdu BOE Display Technology Co Ltd
Priority to CN202010447754.7A priority Critical patent/CN111584521B/en
Publication of CN111584521A publication Critical patent/CN111584521A/en
Application granted granted Critical
Publication of CN111584521B publication Critical patent/CN111584521B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Abstract

The invention provides an array substrate, a manufacturing method thereof and a display panel. The array substrate comprises a substrate and a thin film transistor arranged on the substrate, wherein the thin film transistor comprises a grid electrode, a grid insulating layer, a source electrode and a metal oxide pattern, the source electrode and the metal oxide pattern are arranged on the same layer, a part which is overlapped with each other is arranged between the metal oxide pattern and the source electrode, and the grid insulating layer is arranged between the grid electrode and the source electrode in the stacking direction of the array substrate; the metal oxide pattern includes a first portion located in the middle region and a second portion located at both sides of the first portion, the source electrode is in contact with the second portion, the first portion is semiconducting to form an active layer, and the second portion serves as a pixel electrode. The thin film transistor in the array substrate provided by the invention has the advantages of better performance, simpler production process and lower production cost.

Description

Array substrate, manufacturing method thereof and display panel
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to an array substrate, a manufacturing method thereof and a display panel.
Background
With the development of display technology, flat panel display devices such as liquid crystal displays (Liquid Crystal Display, abbreviated as LCDs) have been widely used in various consumer electronic products such as mobile phones, televisions, personal digital assistants, and notebook computers, and have become the mainstream of display devices, because of their advantages such as high image quality, power saving, thin body, and no radiation.
The liquid crystal display panel is generally composed of an array substrate, a color film substrate and a liquid crystal layer which is arranged oppositely and is clamped between the array substrate and the color film substrate, and the liquid crystal molecules can be controlled to rotate by applying a driving voltage between the array substrate and the color film substrate, so that light rays of the backlight module are refracted out to generate a picture. The array substrate generally comprises a glass substrate and a thin film transistor arranged on the glass substrate, wherein the thin film transistor comprises a grid electrode, a source electrode, a drain electrode, a semiconductor layer and a pixel electrode; the source electrode, the drain electrode and the semiconductor layer are usually positioned in the same layer, the source electrode and the drain electrode are positioned at two sides of the semiconductor layer, the source electrode and the drain electrode are connected through the semiconductor layer, and an active island pattern is formed by the source electrode, the drain electrode and the semiconductor layer; the grid electrode and the active island pattern are arranged on different layers, and a gap is reserved between the layer where the grid electrode is arranged and the layer where the active island pattern is arranged through a grid insulating layer; the pixel electrode may be disposed on the same layer as the active island pattern or on a different layer, and the pixel electrode is connected to the drain electrode.
However, in the array substrate in the prior art, metal ions in the source electrode may diffuse into the semiconductor layer, and may affect the semiconductor layer, thereby affecting the characteristics of the thin film transistor.
Disclosure of Invention
The invention provides an array substrate, a manufacturing method thereof and a display panel, wherein the performance of a thin film transistor in the array substrate is better, the production process of the array substrate is simpler, and the production cost is lower.
In a first aspect, the present invention provides an array substrate, the array substrate including a substrate and a thin film transistor disposed on the substrate, the thin film transistor including a gate electrode, a gate insulating layer, a source electrode, and a metal oxide pattern, the source electrode and the metal oxide pattern being disposed on the same layer, and a portion between the metal oxide pattern and the source electrode overlapping each other, the gate insulating layer being disposed between the gate electrode and the source electrode in a lamination direction of the array substrate; the metal oxide pattern comprises a first part and second parts, wherein the first part is positioned in the middle area and opposite to the grid electrode, the second parts are positioned at two sides of the first part, the first part is semiconductorized to form an active layer, a part which is overlapped with each other is arranged between the source electrode and the second part which is close to the source electrode, and the second part which is far away from the source electrode is used as a pixel electrode.
In one possible embodiment, the gate electrode is disposed on the substrate, the gate insulating layer covers the substrate and the gate electrode, and the source electrode and the metal oxide pattern are disposed on the gate insulating layer.
In one possible embodiment, the semiconductor device further includes a passivation layer disposed on the gate insulating layer, the passivation layer covering the source electrode and the metal oxide pattern; the passivation layer comprises a first passivation layer and a second passivation layer which are sequentially laminated on the gate insulating layer, wherein the first passivation layer is a silicon oxide layer, and the second passivation layer is a silicon nitride layer.
In one possible embodiment, the source electrode and the metal oxide pattern are disposed on the substrate, the gate insulating layer covers the substrate and the source electrode and the metal oxide pattern, and the gate electrode is disposed on the gate insulating layer.
In one possible embodiment, the array substrate further includes an insulating substrate layer disposed between the substrate and the gate insulating layer, the source electrode and the metal oxide pattern being disposed on the insulating substrate layer; the insulating substrate layer comprises a first insulating substrate layer and a second insulating substrate layer which are sequentially laminated on the substrate, wherein the first insulating substrate layer is a silicon nitride layer, and the second insulating substrate layer is a silicon oxide layer.
In one possible embodiment, the array substrate further includes a drain electrode, the second portion of the metal oxide pattern away from the source electrode includes a first segment connected to the first portion and a second segment with a space therebetween, the drain electrode is connected between the first segment and the second segment, and the second segment serves as a pixel electrode.
In a second aspect, the present invention provides a method for manufacturing an array substrate, including the steps of:
forming a gate electrode on a substrate;
forming a gate insulating layer on the substrate, the gate insulating layer covering the gate electrode;
forming a source electrode and a metal oxide pattern on the gate insulating layer; the metal oxide pattern comprises a first part positioned in the middle area and second parts positioned at two sides of the first part, wherein a part which is overlapped with each other is arranged between the source electrode and the second parts which are close to the source electrode, and the second parts which are far away from the source electrode are used as pixel electrodes;
semiconducting a first portion of the metal oxide pattern to form an active layer;
a passivation layer is formed on the gate insulating layer, the passivation layer covering the source electrode and the metal oxide pattern.
In a third aspect, the present invention provides a method for manufacturing an array substrate, including the steps of:
forming an insulating substrate layer on a substrate;
forming a source electrode and a metal oxide pattern on the insulating substrate layer; the metal oxide pattern comprises a first part positioned in the middle area and second parts positioned at two sides of the first part, wherein a part which is overlapped with each other is arranged between the source electrode and the second parts which are close to the source electrode, and the second parts which are far away from the source electrode are used as pixel electrodes;
Semiconducting a first portion of the metal oxide pattern to form an active layer;
forming a gate insulating layer on the insulating substrate layer, the gate insulating layer covering the source electrode and the metal oxide pattern;
a gate electrode is formed on the gate insulating layer.
In one possible embodiment, forming the source electrode and the metal oxide pattern specifically includes:
depositing a source metal layer on the gate insulating layer or the insulating substrate layer;
performing a photoetching process on the source metal layer to form a source;
depositing a metal oxide layer on the gate insulating layer or the insulating substrate layer, wherein the metal oxide layer covers the source electrode;
performing a photoetching process on the metal oxide layer to form a metal oxide pattern; the metal oxide pattern comprises a first part positioned in the middle area and a second part positioned at two sides of the first part, and a part which is overlapped with each other is arranged between the source electrode and the second part which is close to the source electrode.
In one possible embodiment, forming the source electrode and the metal oxide pattern specifically includes:
depositing a source drain metal layer on the gate insulating layer or the insulating substrate layer;
performing a photoetching process on the source drain metal layer to form a source and a drain; wherein, there is interval between drain electrode and the source electrode;
Depositing a metal oxide layer on the gate insulating layer or the insulating substrate layer, wherein the metal oxide layer covers the source electrode and the drain electrode;
performing a photoetching process on the metal oxide layer to form a metal oxide pattern; the metal oxide pattern comprises a first part positioned in the middle area and second parts positioned at two sides of the first part, a part which is overlapped with each other is arranged between the source electrode and the second part which is close to the source electrode, the second part which is far away from the source electrode comprises a first section and a second section, the first section is connected with the first part, a space is arranged between the second section and the first section, and the drain electrode is connected between the first section and the second section.
In a fourth aspect, the present invention provides a display panel comprising an array substrate as described above.
The invention provides an array substrate, a manufacturing method thereof and a display panel, wherein a source electrode and a metal oxide pattern are arranged in the same structural layer of the array substrate, and a part which is overlapped with each other is arranged between the metal oxide pattern and the source electrode, wherein the metal oxide pattern comprises a first part and a second part, the first part is positioned in the middle area of the metal oxide pattern, the second part is positioned at two sides of the first part, and the source electrode is contacted with the second part corresponding to the first part; by taking the second part of the metal oxide pattern as the pixel electrode and performing the semi-conductor treatment on the first part of the metal oxide pattern and taking the first part as the active layer, the source electrode can transmit an electric signal to the pixel electrode through the active layer; meanwhile, as the two sides of the active layer are both the second parts, namely the second parts separate the source electrode from the active layer, metal ions in the source electrode cannot diffuse into the active layer, the semiconductor characteristic of the active layer cannot be influenced, and the performance of the thin film transistor can be improved; in addition, the production process of the array substrate is simpler, and the production cost is lower.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are some embodiments of the invention and that other drawings can be obtained from them without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of an array substrate according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram of a second array substrate according to a first embodiment of the present invention;
fig. 3 is a schematic structural diagram of a third array substrate according to a first embodiment of the present invention;
fig. 4 is a schematic structural diagram of a fourth array substrate according to a first embodiment of the present invention;
fig. 5 is a flow chart of a method for manufacturing an array substrate according to a second embodiment of the present invention;
fig. 6 is a schematic structural diagram of forming a gate on a substrate according to a second embodiment of the present invention;
fig. 7 is a schematic structural diagram of forming a gate insulating layer on a gate electrode according to a second embodiment of the present invention;
fig. 8 is a schematic structural diagram of forming source electrode and metal oxide patterns on a gate insulating layer according to a second embodiment of the present invention;
Fig. 9 is a schematic structural diagram of forming a passivation layer on a source electrode and a metal oxide pattern according to a second embodiment of the present invention;
fig. 10 is a flow chart of another method for manufacturing an array substrate according to the third embodiment of the present invention;
fig. 11 is a schematic structural diagram of forming an insulating substrate layer on a substrate according to a third embodiment of the present invention;
fig. 12 is a schematic structural diagram of forming source and metal oxide patterns on an insulating substrate layer according to a third embodiment of the present invention;
fig. 13 is a schematic structural diagram of a gate insulating layer formed on a source electrode and a metal oxide pattern according to a third embodiment of the present invention;
fig. 14 is a schematic structural diagram of forming a gate on a gate insulating layer according to a third embodiment of the present invention;
FIG. 15 is a flow chart of forming source and metal oxide patterns according to a fourth embodiment of the present invention;
fig. 16 is a flowchart of another method for forming source and metal oxide patterns according to a fourth embodiment of the present invention.
Reference numerals illustrate:
100-an array substrate; 110-a substrate; 120-grid electrode; 130-a gate insulating layer; 131-a first gate insulating layer; 132-a second gate insulating layer; 140-source electrode; 150-metal oxide pattern; 151-a first part; 151 a-an active layer; 152-a second portion; 152 a-pixel electrodes; 1521-a first section; 1522-a second section; 160-a passivation layer; 161-a first passivation layer; 162-a second passivation layer; 170-an insulating substrate layer; 171-a first insulating substrate layer; 172-a second insulating substrate layer; 180-drain electrode; a-a first metal layer; b-a second metal layer.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
Fig. 1 is a schematic structural diagram of an array substrate according to a first embodiment of the present invention; fig. 2 is a schematic structural diagram of a second array substrate according to a first embodiment of the present invention; fig. 3 is a schematic structural diagram of a third array substrate according to a first embodiment of the present invention; fig. 4 is a schematic structural diagram of a fourth array substrate according to an embodiment of the present invention.
As shown in fig. 1 to 4, the present embodiment provides an array substrate 100, the array substrate 100 including a substrate 110 and a thin film transistor disposed on the substrate 110, the thin film transistor including a gate electrode 120, a gate insulating layer 130, a source electrode 140 and a metal oxide pattern 150, the source electrode 140 and the metal oxide pattern 150 being disposed in the same layer, and the metal oxide pattern 150 and the source electrode 140 having a portion overlapping each other, the gate insulating layer 130 being disposed between the gate electrode 120 and the source electrode 140 in a lamination direction of the array substrate 100; the metal oxide pattern 150 includes a first portion 151 located in the middle region opposite to the gate electrode 120 and second portions 152 located at both sides of the first portion 151, the first portion 151 is semiconducting to form an active layer 151a, and the source electrode 140 and the second portion 152 adjacent to the source electrode 140 have a portion overlapping each other, and the second portion 152 distant from the source electrode 140 serves as a pixel electrode 152a.
As shown in fig. 1 to 4, the array substrate 100 includes a substrate 110, the substrate 110 is used as a basic carrier structure of the array substrate 100, and the rest of the hierarchical structure of the array substrate 100 is formed on the substrate 110, wherein the substrate 110 may be a quartz or glass substrate.
In this embodiment, it should be understood that, for the array substrate 100 applied in the liquid crystal display panel, a plurality of data lines and scan lines are generally disposed in the pixel region of the array substrate 100, and the plurality of data lines and the plurality of scan lines divide the pixel region into a plurality of sub-pixels, and at least one thin film transistor is disposed in each sub-pixel.
Specifically, the data lines are arranged in parallel at intervals, the scanning lines are arranged in parallel at intervals, and the data lines and the scanning lines are arranged in a staggered manner in space. Taking the shape of the array substrate 100 as a rectangle as an example, the data lines may extend along the width direction of the array substrate 100, the scan lines may extend along the length direction of the array substrate 100, and a plurality of sub-pixels arranged in a matrix form are formed on the array substrate 100 by the mutual staggering of the data lines and the scan lines.
The driving mode of the data line and the scanning line to the thin film transistor may be a conventional driving mode such as progressive scanning, and will not be described herein.
As shown in fig. 1 to 4, in the array substrate 100 provided in this embodiment, a thin film transistor (TFT device) is disposed on a substrate 110, and the thin film transistor includes a gate electrode 120, a gate insulating layer 130, a source electrode 140, and a metal oxide pattern 150. The metal oxide pattern 150 includes a pixel electrode 152a and an active layer 151a.
Specifically, the source electrode 140 and the metal oxide pattern 150 are disposed in the same layer, and the gate electrode 120 is disposed in a different structural layer from the source electrode 140 and the metal oxide pattern 150 with a gap between the source electrode 140 and the gate electrode 120, wherein the gate insulating layer 130 is disposed between the source electrode 140 and the gate electrode 120, so that the gate electrode 120 and the source electrode 140 are insulated from each other.
In practical applications, for each sub-pixel, the source 140 may be disposed corresponding to the data line, that is, the source 140 and the data line are disposed in the same layer, the source 140 may be a branch connected to the data line, and each sub-pixel has the source 140 therein; similarly, the gate 120 may be disposed corresponding to the scan line, that is, the gate 120 and the scan line are disposed on the same layer, and the gate 120 may be a branch connected to the scan line, and each sub-pixel has the gate 120 therein.
It can be understood that after the scan line is energized to generate an electrical signal, the electrical signal is transferred to the gate electrode 120, and the gate electrode 120 is energized to electrically conductive the active layer 151a disposed at intervals from the gate insulating layer 130, so that the active layer 151a can transfer the electrical signal on the source electrode 140 to the pixel electrode 152a; while the active layer 151a maintains its semiconductor characteristics when the scan line is not energized.
In this embodiment, the metal oxide pattern 150 and the source electrode 140 have overlapping portions, i.e., opposite sides of the metal oxide pattern 150 and the source electrode 140 overlap each other, so that the source electrode 140 can transmit an electrical signal to the metal oxide pattern 150. The metal oxide pattern 150 includes a first portion 151 and a second portion 152, where the first portion 151 is correspondingly located in a middle area of the metal oxide pattern 150, and two sides of the first portion 151 are both the second portion 152 of the metal oxide pattern 150.
Specifically, the second portion 152 of the metal oxide pattern 150 opposite to the source electrode 140 is in contact with the source electrode 140, the second portion 152 of the metal oxide pattern 150 distant from the source electrode 140 may serve as a pixel electrode 152a, and the first portion 151 located in the middle region of the metal oxide pattern 150 forms an active layer 151a, so that the source electrode 140 transfers an electrical signal to the active layer 151a, and the active layer 151a transfers an electrical signal to the second portion 152 of the metal oxide pattern 150 serving as the pixel electrode 152a, thereby implementing charge and discharge of the pixel electrode 152 a.
In order to form the active layer 151a in the first portion 151 of the metal oxide pattern 150 as a conductor, the first portion 151 may be formed by a semiconductor process. For example, the first portion 151 may be semiconductorized by ultraviolet light irradiation or plasma implantation or the like.
In the related art, the active layer 151a is generally in direct contact with the source electrode 140, for example, one side of the source electrode 140 is overlaid on the active layer 151a, or one side of the active layer 151a is overlaid on the source electrode 140. With this structure, metal ions such as Cu and Al in the source electrode 140 are directly diffused into the active layer 151a in contact therewith, and after the active layer 151a absorbs the metal ions, the active layer 151a may be conductive, which may affect the semiconductor characteristics of the active layer 151a and thus the characteristics of the TFT device.
As shown in fig. 1, in the present embodiment, the first portion 151 of the metal oxide pattern 150 located in the middle region is semiconducting to form the active layer 151a, and the source electrode 140 is in contact with the second portion 152 of the metal oxide pattern 150, that is, the active layer 151a is spaced apart from the source electrode 140 by the second portion 152, so that metal ions such as Cu, al, etc. in the source electrode 140 can only diffuse into the second portion 152 in contact therewith, and the second portion 152 absorbs the metal ions diffused from the source electrode 140.
In this way, the metal ions in the source electrode 140 cannot diffuse into the active layer 151a, and thus do not affect the active layer 151a, and the active layer 151a can be protected by the second portion 152 of the metal oxide pattern 150 being spaced between the source electrode 140 and the active layer 151a, so that the active layer 151a maintains good semiconductor characteristics, and the performance of the TFT device can be improved.
For example, the material forming the metal oxide pattern 150 may be indium tin oxide ITO, i.e., the metal oxide pattern 150 is an ITO transparent conductive layer. Wherein a second portion 152 of the ITO transparent conductive layer remote from the source electrode 140 serves as a pixel electrode 152a. In some other embodiments, the metal oxide pattern 150 may be formed using other metal oxide materials, which is not limited in this embodiment.
In this embodiment, the metal oxide pattern 150 is divided into the first portion 151 and the second portion 152, the first portion 151 is located in the middle region, the second portion 152 is located at two sides of the first portion 151, the second portion 152 opposite to the source 140 and the source 140 have a region overlapping each other, the second portion 152 away from the source 140 serves as the pixel electrode 152a, and the first portion 151 is semiconducting to form the active layer 151a. Thus, not only can the source electrode 140 transmit the electric signal to the pixel electrode 152a through the active layer 151a, but also the pixel electrode 152a can be charged and discharged; meanwhile, the active layer 151a and the source electrode 140 are spaced apart by the second portion 152, and diffusion of metal ions in the source electrode 140 to the active layer 151a may be blocked to protect semiconductor characteristics of the active layer 151a, thereby improving performance of the TFT device.
In addition, for the formation process of each level structure of the array substrate 100, only three photolithography processes are required in the present embodiment. Specifically, the gate electrode 120 is formed on the substrate 110 through one photolithography process, the source electrode 140 is formed through one photolithography process, and the metal oxide pattern 150 is formed through one photolithography process.
Compared with the formation process of the array substrate 100 in the prior art, the array substrate 100 of the embodiment has fewer times of photolithography processes, and simpler production process, so that the production cost of the array substrate 100 can be reduced.
It should be understood that, in the present embodiment, each of the hierarchical structures forming the array substrate 100 needs to undergo three photolithography processes, but if driving of the TFT device is to be achieved, a portion overlapping with an external device needs to be provided in the array substrate 100, for example, a predetermined hole capable of exposing the gate electrode 120 and the source electrode 140 needs to be reserved in the array substrate 100, and the predetermined hole communicating with the outside is provided on the gate electrode 120 and the source electrode 140 to conduct an external electrical signal into the array substrate 100, so as to achieve driving of the TFT device.
However, since the pre-holes are required to be formed on the gate electrode 120 and the source electrode 140, a process of etching the pre-holes once is inevitably required, and thus a photolithography process is also required to be added.
As shown in fig. 1 and 3, in some embodiments, in the hierarchical structure where the array substrate 100, the source electrode 140, and the metal oxide pattern 150 are located in this example, only the source electrode 140 may be provided, and the drain electrode 180 is not provided, and the active layer 151a formed by semiconducting the first portion 151 of the metal oxide pattern 150 directly contacts the second portion 152 as the pixel electrode 152a, so that an electrical signal of the source electrode 140 is directly transferred to the pixel electrode 152a through the semiconductor layer.
As shown in fig. 2 and 4, in some other embodiments, in the array substrate 100 of the present embodiment, in the hierarchical structure where the source electrode 140 and the metal oxide pattern 150 are located, a drain electrode 180 may be further disposed, and the drain electrode 180 is spaced from the source electrode 140, and an electrical signal is transmitted to the pixel electrode 152a through the drain electrode 180.
For a structure in which the drain electrode 180 is disposed in the array substrate 100, the disposed metal oxide pattern 150 may include a portion between the source electrode 140 and the drain electrode 180 and a portion adjacent to one side of the drain electrode 180. Wherein, the first portion 151 of the metal oxide pattern 150, which is semiconducting into the active layer 151a, is located in the space between the source electrode 140 and the drain electrode 180, and the second portion 152 is located on both sides of the first portion 151 in the space, and the source electrode 140 and the second portion 152 have mutually overlapped regions; the second portion 152 includes a first segment 1521 and a second segment 1522, the first segment 1521 is a region correspondingly connected to two sides of the first portion 151, the second segment 1522 is disposed on one side of the drain electrode 180, a space is provided between the second segment 1522 and the first segment 1521, and the drain electrode 180 is located between the first segment 1521 and the second segment 1522 connected to the first portion 151, so that the second segment 1522 is used as the pixel electrode 152a.
In the structure having the drain electrode 180, an electric signal is transferred from the source electrode 140 to the active layer 151a, the active layer 151a transfers the electric signal to the drain electrode 180, and the drain electrode 180 transfers the electric signal to the pixel electrode 152a, thereby charging and discharging the pixel electrode 152 a.
In addition, in the embodiment, for the array substrate 100 provided with the drain electrode 180, the drain electrode 180 and the source electrode 140 may be formed by the same photolithography process, and although the second portion 152 of the metal oxide pattern 150 includes the first segment 1521 and the second segment 1522, the metal oxide pattern 150 is formed by only one photolithography process, so that the number of photolithography processes of the array substrate 100 is not increased, the manufacturing process of the array substrate 100 is the same as that of the array substrate 100 without the drain electrode 180, the manufacturing process is simpler, and the manufacturing cost of the array substrate 100 is lower.
The following description will be omitted for example, and the following embodiments are equally applicable to the substrate 110 provided with the drain 180, taking the hierarchical structure of the array substrate 100 not provided with the drain 180 as an example.
As shown in fig. 1 and 2, in the present embodiment, the TFT devices in the array substrate 100 may be bottom gate structures. For the array substrate 100 of the bottom gate structure, the gate electrode 120 may be disposed on the substrate 110, the gate insulating layer 130 covers the substrate 110 and the gate electrode 120, and the source electrode 140 and the metal oxide pattern 150 are disposed on the gate insulating layer 130.
In one possible embodiment, a passivation layer 160 may be further disposed on the gate insulating layer 130, the passivation layer 160 covering the source electrode 140 and the metal oxide pattern 150. The passivation layer 160 serves to protect the source electrode 140 thereunder and the pixel electrode 152a and the active layer 151a in the metal oxide pattern 150, and the passivation layer 160 may serve as an outermost structure of the array substrate 100 and may serve as a protective layer structure of the array substrate 100.
Specifically, the passivation layer 160 may include a first passivation layer 161 and a second passivation layer 162 sequentially stacked on the gate insulating layer 130, the first passivation layer 161 may be a silicon oxide layer, and the second passivation layer 162 may be a silicon nitride layer. The first passivation layer 161 directly covers the source electrode 140 and the metal oxide pattern 150, and the second passivation layer 162 covers the first passivation layer 161, so that the source electrode 140 and the metal oxide pattern 150 are better protected by the first passivation layer 161 and the second passivation layer 162.
The first passivation layer 161 of the passivation layer 160 is a silicon oxide layer, and the second passivation layer 162 is a silicon nitride layer. The second passivation layer 162 may be used as an outermost layer structure of the array substrate 100, or the second passivation layer 162 is closer to the outer surface of the array substrate 100, and by setting the second passivation layer 162 as a silicon nitride layer, external moisture may be isolated, so as to prevent the moisture from affecting the metal oxide pattern 150 and the source 140; the first passivation layer 161 directly covers the metal oxide pattern 150 and the source electrode 140, and by providing the first passivation layer 161 as a silicon oxide layer having a good compactness, oxygen atoms enriched in the silicon oxide layer can diffuse into the active layer 151a of the metal oxide pattern 150, supplementing oxygen atoms in the active layer 151a, and maintaining the semiconductor characteristics of the active layer 151 a.
As shown in fig. 3 and 4, in this embodiment, the TFT devices in the array substrate 100 may also be top gate structures. For the array substrate 100 of the top gate structure, the source electrode 140 and the metal oxide pattern 150 may be disposed on the substrate 110, the gate insulating layer 130 may cover the substrate 110 and the source electrode 140 and the metal oxide pattern 150, and the gate electrode 120 is disposed on the gate insulating layer 130.
For a TFT device of a top gate structure, the gate electrode 120 may be positioned over the source electrode 140, the metal oxide pattern 150, the gate insulating layer 130 covers the source electrode 140 and the metal oxide pattern 150, and the gate electrode 120 is disposed on the gate insulating layer 130. The source electrode 140 and the metal oxide pattern 150 may be directly disposed on the substrate 110, and the substrate 110, the source electrode 140, the metal oxide pattern 150, the gate insulating layer 130, and the gate electrode 120 may be sequentially disposed in the stacking direction of the array substrate 100.
The gate insulating layer 130 may include a first gate insulating layer 131 and a second gate insulating layer 132, the first gate insulating layer 131 being located opposite to the outside of the array substrate 100, similar to the protection effect of the passivation layer 160 on the source electrode 140 and the metal oxide pattern 150, whether in a bottom gate structure or a top gate structure; wherein, for the bottom gate structure, the first gate insulating layer 131 is closer to the substrate 110, and for the top gate structure, the first gate insulating layer 131 is closer to the gate 120; the second gate insulating layer 132 is relatively closer to the source electrode 140 and the structural layer where the metal oxide pattern 150 is located; wherein, for a bottom gate structure, the second gate insulating layer 132 may cover the first gate insulating layer 131, and for a top gate structure, the second gate insulating layer 132 directly covers the source electrode 140 and the metal oxide pattern 150, and the first gate insulating layer 131 covers the second gate insulating layer 132.
The first gate insulating layer 131 is a silicon nitride layer, and the silicon nitride layer has a good function of isolating moisture, and can isolate moisture from the outside of the array substrate 100 or from the substrate 110, so as to prevent moisture from entering the active layer 151a, thereby protecting the active layer 151a from being affected by moisture.
The second gate insulating layer 132 is a silicon oxide layer, which has better compactness and is rich in more oxygen elements. If oxygen atoms in the active layer 151a are combined with metal ions in the source electrode 140 or free hydrogen ions present in the passivation layer 160, the active layer 151a is made conductive by losing oxygen atoms, the active layer 151a loses semiconductor characteristics, and oxygen atoms in the second gate insulating layer 132 can diffuse into the active layer 151a to supplement oxygen atoms in the active layer 151a, and the active layer 151a maintains its semiconductor characteristics.
The liquid crystal display panel is used as a passive light emitting device, and a backlight is required to be disposed on the back surface of the display screen, if the source 140 and the metal oxide pattern 150 are directly disposed on the substrate 110, light of the backlight irradiates the metal oxide pattern 150 through the substrate 110, and when the light irradiates the active layer 151a in the metal oxide pattern 150, photo-generated carriers are generated on the active layer 151a, which affects the semiconductor characteristics of the active layer 151a and further affects the off-state current characteristics of the TFT device.
Therefore, in order to prevent the light of the backlight from directly irradiating the active layer 151a formed in the metal oxide pattern 150, in this embodiment, for the top gate structure, an insulating substrate layer 170 is further disposed on the substrate 110, the insulating substrate layer 170 is located between the substrate 110 and the gate insulating layer 130, and the source electrode 140 and the metal oxide pattern 150 are disposed on the insulating substrate layer 170.
As shown in fig. 3 and 4, the source electrode 140 and the metal oxide pattern 150 are disposed on the insulating substrate layer 170 by disposing the insulating substrate layer 170 on the substrate 110 such that the insulating substrate layer 170 is spaced between the substrate 110 and the active layer 151a in the metal oxide pattern 150. Light from the backlight source is firstly irradiated to the insulating substrate layer 170 through the substrate 110, the insulating substrate layer 170 has a certain refractive index, light rays can be scattered, diffusely reflected or reflected, and the like, light ray energy can be attenuated, so that the light from the backlight source is not intensively irradiated to the active layer 151a, the semiconductor characteristic of the active layer 151a is protected, and the off-state current characteristic of the thin film transistor is ensured.
As shown in fig. 3 and 4, the insulating substrate layer 170 may include a first insulating substrate layer 171 and a second insulating substrate layer 172 sequentially stacked on the substrate 110, the first insulating substrate layer 171 being a silicon nitride layer, and the second insulating substrate layer 172 being a silicon oxide layer, similar to the gate insulating layer 130.
By providing a silicon nitride layer on the substrate 110 as the first insulating substrate layer 171, the silicon nitride layer can isolate moisture from outside the array substrate 100 or the substrate 110, protecting the active layer 151a in the metal oxide pattern 150 from moisture; by covering the first insulating substrate layer 171 with a silicon oxide layer as the second insulating substrate layer 172, the source electrode 140 and the metal oxide pattern 150 are directly formed on the silicon oxide layer, and the silicon oxide layer is more dense, and is rich in oxygen elements, oxygen atoms in the active layer 151a can be supplemented, so that the semiconductor characteristics of the active layer 151a can be maintained.
In addition, as shown in fig. 1 to 4, in this embodiment, the source 140, the drain 180 and the gate 120 may be formed by stacking a first metal layer a and a second metal layer b, where the metal in the first metal layer a located at the bottom layer includes at least one of titanium and molybdenum, and the metal in the second metal layer b located at the top layer includes at least one of copper and aluminum.
By providing two metal layers of the first metal layer a and the second metal layer b as the source electrode 140, the drain electrode 180 and the gate electrode 120, the second metal layer b is laminated on the first metal layer a, wherein the first metal layer a is a single metal layer or a composite metal layer of titanium, molybdenum and the like, and the second metal layer b is a single metal layer or a composite metal layer of copper, aluminum and the like. The first metal layer a located at the bottom layer is mainly used for making the connection between the source 140, the drain 180 or the gate 120 and the underlying structure stronger, and enhancing the connection strength between the source 140, the drain 180 or the gate 120 and the underlying structure; the second metal layer b on the top layer is mainly used for exerting the conductivity of the source electrode 140, the drain electrode 180 and the gate electrode 120, so as to ensure the performance of the TFT device.
According to the array substrate provided by the embodiment, the source electrode and the metal oxide pattern are arranged in the same structural layer, and the metal oxide pattern and the source electrode are provided with mutually overlapped parts, wherein the metal oxide pattern comprises a first part and a second part, the first part is positioned in the middle area of the metal oxide pattern, the second part is positioned at two sides of the first part, and the source electrode is in contact with the second part corresponding to the first part; by taking the second part of the metal oxide pattern as the pixel electrode and performing the semi-conductor treatment on the first part of the metal oxide pattern and taking the first part as the active layer, the source electrode can transmit an electric signal to the pixel electrode through the active layer; meanwhile, as the two sides of the active layer are both the second parts, namely the second parts separate the source electrode from the active layer, metal ions in the source electrode cannot diffuse into the active layer, the semiconductor characteristic of the active layer cannot be influenced, and the performance of the thin film transistor can be improved; in addition, the production process of the array substrate is simpler, and the production cost is lower.
Example two
Fig. 5 is a flow chart of a method for manufacturing an array substrate according to a second embodiment of the present invention; fig. 6 is a schematic structural diagram of forming a gate on a substrate according to a second embodiment of the present invention; fig. 7 is a schematic structural diagram of forming a gate insulating layer on a gate electrode according to a second embodiment of the present invention; fig. 8 is a schematic structural diagram of forming source electrode and metal oxide patterns on a gate insulating layer according to a second embodiment of the present invention; fig. 9 is a schematic structural diagram of forming a passivation layer on a source electrode and a metal oxide pattern according to a second embodiment of the present invention.
The present embodiment provides a method for manufacturing an array substrate 100, which is used for manufacturing the array substrate 100 with the bottom gate structure described in the first embodiment. The structure, function and working principle of the array substrate 100 are described in detail in the first embodiment, and are not described here again.
As shown in fig. 5, for the array substrate 100 with a bottom gate structure, the manufacturing method of the array substrate 100 includes the following steps:
s1a, a gate electrode 120 is formed on the substrate 110.
As shown in fig. 6, a gate electrode 120120 is first formed on a substrate 110110. Specifically, a gate metal layer is first deposited on the substrate 110, and then patterned gate 120 is formed from the gate metal layer by a photolithography process. The depositing the gate metal layer includes sequentially depositing a first metal layer a and a second metal layer b on the substrate 110, where the first metal layer a may be a single metal layer or a composite metal layer such as Ti and Mo, and the second metal layer b may be a single metal layer or a composite metal layer such as Cu and Al.
The gate metal layer is subjected to a photolithography process to form the gate electrode 120, which may be specifically: firstly, coating a photoresist layer on a gate metal layer, arranging a mask above the gate metal layer, arranging a light transmission area and a light non-transmission area on the mask, irradiating ultraviolet light to the surface of the photoresist layer through the mask to cause chemical reaction of the photoresist in an exposure area of the photoresist layer, and dissolving and removing the photoresist in the exposure area (positive photoresist) or the photoresist in an unexposed area (negative photoresist) through a developing technology; the remaining photoresist in the photoresist layer only covers the region corresponding to the gate electrode 120 in the gate metal layer, other regions of the gate metal layer are exposed, at this time, the exposed region of the gate metal layer is etched, only the gate electrode 120 is finally reserved, and finally, the photoresist covering the gate electrode 120 is removed, so that the gate electrode 120 can be formed on the substrate 110.
It can be understood that the process of exposing and developing the photoresist layer by irradiating ultraviolet light to the photoresist layer through the mask plate so as to transfer the mask pattern on the mask plate to the photoresist layer to form the photoresist layer pattern, and the process of etching the region uncovered by the photoresist layer after forming the photoresist layer pattern are the same as or similar to the above process flow, and the exposing, developing and etching processes occurring after this embodiment are not repeated one by one.
S2a, forming a gate insulating layer 130 on the substrate 110, the gate insulating layer 130 covering the gate electrode 120.
As shown in fig. 7, after forming the gate electrode 120 on the substrate 110, depositing the gate insulating layer 130 on the substrate 110, the gate insulating layer 130 may cover the entire substrate 110; wherein the gate insulating layer 130 covers the gate electrode 120. Depositing the gate insulating layer 130 includes sequentially depositing a first gate insulating layer 131 and a second gate insulating layer 132 on the substrate 110.
S3a, forming a source electrode 140 and a metal oxide pattern 150 on the gate insulating layer 130; the metal oxide pattern 150 includes a first portion 151 located in the middle region and second portions 152 located at both sides of the first portion 151, and the source electrode 140 and the second portion 152 adjacent to the source electrode 140 have a portion overlapping each other, and the second portion 152 distant from the source electrode 140 serves as a pixel electrode 152a.
As shown in fig. 8, after forming the gate insulating layer 130 by deposition on the substrate 110, the source electrode 140 and the metal oxide pattern 150 are formed on the gate insulating layer 130.
In one possible implementation, a source metal layer may be deposited on the gate insulating layer 130, and then a photolithography process is performed on the source metal layer to form the patterned source 140; a metal oxide layer is then deposited on the gate insulating layer 130, covering the source electrode 140, and a photolithography process is performed on the metal oxide layer to form a metal oxide pattern 150. The metal oxide pattern 150 includes a first portion 151 and second portions 152 located on both sides of the first portion 151, the second portions 152 close to the source 140 are covered on the source 140, and the second portions 152 far from the source 140 are used as pixel electrodes 152a.
In another possible embodiment, a metal oxide layer may be deposited on the gate insulating layer 130, and then subjected to a photolithography process to form the metal oxide pattern 150; then, a source metal layer is deposited on the gate insulating layer 130, the source metal layer covers the metal oxide pattern 150, and a photolithography process is performed on the source metal layer to form a patterned source electrode 140. Thus, the source 140 overlies the second portion 152 of the metal oxide pattern adjacent thereto.
S4a, the first portion 151 of the metal oxide pattern 150 is formed into a semiconductor to form an active layer 151a.
As shown in fig. 8, after the metal oxide pattern 150 is formed, the first portion 151 of the metal oxide pattern 150 is subjected to ultraviolet irradiation, plasma implantation, or the like to form an active layer 151a in a semiconductor state.
Taking an example of the semiconductor formation of the first portion 151 of the metal oxide pattern 150 by plasma implantation, specifically, the semiconductor formation of the first portion 151 of the metal oxide pattern 150 is performed using the ashed photoresist pattern as a mask to form the active layer 151a.
Since the region corresponding to the active layer 151a is exposed in the ashed photoresist pattern and the remaining portion is covered with photoresist, the active layer 151a can be formed in the region where the active layer 151a is to be formed by performing a semiconductor process, for example, ion implantation using the ashed photoresist pattern as a mask.
In the above-described aspect, the region of the metal oxide pattern 150 corresponding to the first portion 151 is ion-implanted using the ashed photoresist pattern as a mask, and in the ion implantation apparatus, the ion implantation reaction chamber has a vacuum degree of 3×10 -4 Pa～8×10 -4 Pa, and the vacuum time is 30-50 s. The ion implantation energy is greater than or equal to 200KeV at a set chamber temperature, for example, a temperature of 200-300 c, and the implantation depth may be the same as the thickness of the metal oxide pattern 150 to separate the second portion 152, which is the pixel electrode 152a, from the second portion 152 in contact with the source electrode 140.
The gas may be selected from a carbon source gas, etc., and the ion implantation composition contains at least one of Cr and HF such that the ions have an implantation energy of about 50KeV to change the atomic arrangement of the conductor surface and recombine continuously. The ion implantation time is not limited, and the metal oxide pattern 150 may have a thickness of 40 to 90nm, for example, and the implantation time may be 200 to 250 seconds.
Ion implantation is performed as described above, and high-temperature annealing is performed, wherein the annealing temperature may be, for example, 250 to 400 ℃, and the first portion 151 on the metal oxide pattern 150 may be semiconducting into the active layer 151a.
S5a, a passivation layer 160 is formed on the gate insulating layer 130, and the passivation layer 160 covers the source electrode 140 and the metal oxide pattern 150.
As shown in fig. 9, after the source electrode 140 and the metal oxide pattern 150 are formed and the first portion 151 of the metal oxide pattern 150 forms the active layer 151a, a passivation layer 160 is deposited on the gate insulating layer 130 such that the passivation layer 160 covers the source electrode 140 and the metal oxide pattern 150. Wherein depositing the passivation layer 160 on the gate insulating layer 130 includes sequentially depositing a first passivation layer 161 and a second passivation layer 162 on the gate insulating layer 130.
Example III
Fig. 10 is a flowchart illustrating a manufacturing method of another array substrate 100 according to the third embodiment of the present invention; fig. 11 is a schematic structural diagram of a third embodiment of the present invention for forming an insulating substrate layer 170 on a substrate 110; fig. 12 is a schematic structural diagram of forming a source electrode 140 and a metal oxide pattern 150 on an insulating substrate layer 170 according to a third embodiment of the present invention; fig. 13 is a schematic structural diagram of a gate insulating layer 130 formed on a source electrode 140 and a metal oxide pattern 150 according to a third embodiment of the present invention; fig. 14 is a schematic diagram of a structure of forming a gate electrode 120 on a gate insulating layer 130 according to a third embodiment of the present invention.
The present embodiment provides another method for manufacturing the array substrate 100, which is used for manufacturing the array substrate 100 with the top gate structure described in the first embodiment.
As shown in fig. 10, for an array substrate 100 with a top gate structure, the method for manufacturing the array substrate 100 includes the following steps:
s1b, an insulating substrate layer 170 is formed on the substrate 110.
As shown in fig. 11, an insulating substrate layer 170 is first deposited on the substrate 110, and the insulating substrate layer 170 may cover the entire substrate 110. Wherein depositing the insulating substrate layer 170 comprises sequentially depositing a first insulating substrate layer 171 and a second insulating substrate layer 172 on the substrate 110.
S2b, forming a source electrode 140 and a metal oxide pattern 150 on the insulating substrate layer 170; the metal oxide pattern 150 includes a first portion 151 located in the middle region and second portions 152 located at both sides of the first portion 151, and the source electrode 140 and the second portion 152 adjacent to the source electrode 140 have a portion overlapping each other, and the second portion 152 distant from the source electrode 140 serves as a pixel electrode 152a.
As shown in fig. 12, after forming an insulating substrate layer 170 on a substrate 110 by deposition, a source electrode 140 and a metal oxide pattern 150 are formed on the insulating substrate layer 170.
In one possible implementation, a source metal layer may be deposited on the insulating substrate layer 170, and then a photolithography process may be performed on the source metal layer to form the patterned source 140; a metal oxide layer is then deposited on the insulating substrate layer 170, the metal oxide layer covering the source electrode 140, and a photolithography process is performed on the metal oxide layer to form the metal oxide pattern 150. The metal oxide pattern 150 includes a first portion 151 and second portions 152 located on both sides of the first portion 151, the second portions 152 close to the source 140 are covered on the source 140, and the second portions 152 far from the source 140 are used as pixel electrodes 152a.
In another possible embodiment, a metal oxide layer may be deposited on the insulating substrate layer 170, and then subjected to a photolithography process to form the metal oxide pattern 150; then, a source metal layer is deposited on the insulating substrate layer 170, the source metal layer covers the metal oxide pattern 150, and a photolithography process is performed on the source metal layer to form the patterned source electrode 140. Thus, the source 140 overlies the second portion 152 of the metal oxide pattern adjacent thereto.
S3b, the first portion 151 of the metal oxide pattern 150 is formed into a semiconductor to form an active layer 151a.
As shown in fig. 12, after the metal oxide pattern 150 is formed, the first portion 151 of the metal oxide pattern 150 is subjected to ultraviolet irradiation, plasma implantation, or the like to form an active layer 151a in a semiconductor state.
S4b, forming a gate insulating layer 130 on the insulating substrate layer 170, the gate insulating layer 130 covering the source electrode 140 and the metal oxide pattern 150.
As shown in fig. 13, after forming the source electrode 140 and the metal oxide pattern 150 and forming the active layer 151a on the first portion 151 of the metal oxide pattern 150, the gate insulating layer 130 is deposited on the insulating substrate layer 170 such that the gate insulating layer 130 covers the source electrode 140 and the metal oxide pattern 150. Wherein depositing the gate insulating layer 130 includes depositing a second gate insulating layer 132 and a first gate insulating layer 131 sequentially on the insulating substrate layer 170.
S5b, the gate electrode 120 is formed on the gate insulating layer 130.
As shown in fig. 14, after the gate insulating layer 130 is formed, a gate metal layer is deposited on the gate insulating layer 130, and then patterned gate electrode 120 is formed by a photolithography process.
Example IV
Fig. 15 is a flowchart of forming a source electrode 140 and a metal oxide pattern 150 according to a fourth embodiment of the present invention; fig. 16 is a flowchart illustrating another method of forming a source electrode 140 and a metal oxide pattern 150 according to a fourth embodiment of the present invention.
As shown in fig. 15 and 16, the drain electrode 180 may be disposed in the array substrate 100, or the drain electrode 180 may not be disposed in the array substrate 100, regardless of whether the array substrate 100 is of a bottom gate structure or a top gate structure. In this embodiment, a process of forming the source electrode 140 and the metal oxide pattern 150 of the two array substrates 100 where the drain electrode 180 is disposed and where the drain electrode 180 is not disposed will be described.
As shown in fig. 15, for the array substrate 100 without the drain electrode 180, in one possible embodiment, the forming of the source electrode 140 and the metal oxide pattern 150 may specifically include the following steps:
s10a, a source metal layer is deposited on the gate insulating layer 130 (insulating substrate layer 170).
And S20a, performing a photoetching process on the source metal layer to form a source electrode 140.
S30a, a metal oxide layer is deposited on the gate insulating layer 130 (insulating substrate layer 170), and covers the source electrode 140.
And S40a, performing a photoetching process on the metal oxide layer to form a metal oxide pattern 150.
The metal oxide pattern 150 is formed to include a first portion 151 and a second portion 152, the second portion 152 being located at both sides of the first portion 151, wherein the second portion 152 near the source 140 covers a partial region of the source 140, and the second portion 152 far from the source 140 may serve as a pixel electrode 152a.
As shown in fig. 16, for the array substrate 100 provided with the drain electrode 180, in one possible embodiment, the forming of the source electrode 140 and the metal oxide pattern 150 may specifically include the following steps:
s10b, depositing a metal layer of the source/drain 180 on the gate insulating layer 130 (the insulating substrate layer 170).
S20b, carrying out a photoetching process on the metal layer of the source drain electrode 180 to form a source electrode 140 and a drain electrode 180; wherein a space is provided between the source 140 and the drain 180.
S30b, a metal oxide layer is deposited on the gate insulating layer 130 (insulating substrate layer 170), and the metal oxide covers the source electrode 140 and the drain electrode 180.
And S40b, performing a photoetching process on the metal oxide layer to form a metal oxide pattern 150.
The metal oxide pattern 150 is formed to include a first portion 151 and a second portion 152, the second portion 152 is located at two sides of the first portion 151, wherein the second portion 152 close to the source 140 covers a partial region of the source 140, the second portion 152 far from the source 140 includes a first segment 1521 and a second segment 1522, the first segment 1521 is connected to the first portion 151 and located in a space between the source 140 and the drain 180, the second segment 1522 is located at a space between the first segment 1521, the second segment 1522 is located at the other side of the drain 180, and a portion of the second segment 1522 covers the drain 180.
Example five
The present embodiment provides a display panel, which includes a color film substrate, a liquid crystal layer, and the array substrate 100 according to the first embodiment. The array substrate 100 and the color film substrate are disposed opposite to each other, and the liquid crystal layer is sandwiched between the array substrate 100 and the color film substrate. By applying an electric field between the array substrate 100 and the color film substrate, the voltage in the electric field can control the arrangement condition of the liquid crystal molecules in the liquid crystal layer, thereby achieving the purposes of shading and transmitting light, so that the display panel displays images.
The structure, function and working principle of the array substrate 100 are described in detail in the first embodiment, and are not described here again.
Another aspect of the present embodiment also provides a display device, including the above display panel. In this embodiment, the display device may be a liquid crystal television, a notebook computer, a tablet computer, an electronic paper, or the like.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (9)

1. An array substrate is characterized by comprising a substrate and a thin film transistor arranged on the substrate, wherein the thin film transistor comprises a grid electrode, a grid insulating layer, a source electrode and a metal oxide pattern, the source electrode and the metal oxide pattern are arranged on the same layer, a part which is overlapped with each other is arranged between the metal oxide pattern and the source electrode, and the grid insulating layer is arranged between the grid electrode and the source electrode in the stacking direction of the array substrate; the metal oxide pattern comprises a first part and second parts, wherein the first part is located in the middle area and opposite to the grid electrode, the second parts are located on two sides of the first part, the first part is semiconducting to form an active layer, a part which is overlapped with each other is arranged between the source electrode and the second parts which are close to the source electrode, the source electrode and the active layer are separated through the second parts which are close to the source electrode, the second parts which are far from the source electrode are used as pixel electrodes, and the first parts are in direct contact with the second parts located on two sides of the first parts.
2. The array substrate of claim 1, wherein the gate electrode is disposed on the substrate, the gate insulating layer covers the substrate and the gate electrode, and the source electrode and the metal oxide pattern are disposed on the gate insulating layer.
3. The array substrate of claim 2, further comprising a passivation layer disposed on the gate insulating layer, the passivation layer covering the source electrode and the metal oxide pattern; the passivation layer comprises a first passivation layer and a second passivation layer which are sequentially laminated on the gate insulating layer, wherein the first passivation layer is a silicon oxide layer, and the second passivation layer is a silicon nitride layer.
4. The array substrate according to claim 1, wherein the source electrode and the metal oxide pattern are disposed on the substrate, the gate insulating layer covers the substrate and the source electrode and the metal oxide pattern, and the gate electrode is disposed on the gate insulating layer.
5. The array substrate of claim 4, further comprising an insulating substrate layer disposed between the substrate and the gate insulating layer, the source electrode and the metal oxide pattern being disposed on the insulating substrate layer; the insulating substrate layer comprises a first insulating substrate layer and a second insulating substrate layer which are sequentially laminated on the substrate, wherein the first insulating substrate layer is a silicon nitride layer, and the second insulating substrate layer is a silicon oxide layer.
6. The manufacturing method of the array substrate is characterized by comprising the following steps of:
forming a gate electrode on a substrate;
forming a gate insulating layer on a substrate, the gate insulating layer covering the gate electrode;
forming a source electrode and a metal oxide pattern on the gate insulating layer; wherein the metal oxide pattern includes a first portion located in a middle region and second portions located at both sides of the first portion, the source electrode and the second portion adjacent to the source electrode having a portion overlapping each other therebetween so as to space the source electrode from the first portion by the second portion adjacent to the source electrode, the second portion remote from the source electrode serving as a pixel electrode; wherein the first portion is in direct contact with second portions located on both sides of the first portion;
semiconducting the first portion of the metal oxide pattern to form an active layer;
and forming a passivation layer on the gate insulating layer, wherein the passivation layer covers the source electrode and the metal oxide pattern.
7. The manufacturing method of the array substrate is characterized by comprising the following steps of:
forming an insulating substrate layer on a substrate;
forming a source electrode and a metal oxide pattern on the insulating substrate layer; wherein the metal oxide pattern includes a first portion located in a middle region and second portions located at both sides of the first portion, the source electrode and the second portion adjacent to the source electrode having a portion overlapping each other therebetween so as to space the source electrode from the first portion by the second portion adjacent to the source electrode, the second portion remote from the source electrode serving as a pixel electrode; wherein the first portion is in direct contact with second portions located on both sides of the first portion;
Semiconducting the first portion of the metal oxide pattern to form an active layer;
forming a gate insulating layer on the insulating substrate layer, the gate insulating layer covering the source electrode and the metal oxide pattern;
and forming a gate electrode on the gate insulating layer.
8. The method for manufacturing an array substrate according to claim 6 or 7, wherein the forming source electrode and metal oxide patterns specifically includes:
depositing a source metal layer on the gate insulating layer or the insulating substrate layer;
performing a photoetching process on the source electrode metal layer to form a source electrode;
depositing a metal oxide layer on the gate insulating layer or the insulating substrate layer, the metal oxide layer covering the source electrode;
performing a photoetching process on the metal oxide layer to form a metal oxide pattern; the metal oxide pattern comprises a first part positioned in the middle area and a second part positioned at two sides of the first part, and a part which is overlapped with each other is arranged between the source electrode and the second part which is close to the source electrode.
9. A display panel comprising the array substrate of any one of claims 1-5.
CN202010447754.7A 2020-05-25 2020-05-25 Array substrate, manufacturing method thereof and display panel Active CN111584521B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010447754.7A CN111584521B (en) 2020-05-25 2020-05-25 Array substrate, manufacturing method thereof and display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010447754.7A CN111584521B (en) 2020-05-25 2020-05-25 Array substrate, manufacturing method thereof and display panel

Publications (2)

Publication Number Publication Date
CN111584521A CN111584521A (en) 2020-08-25
CN111584521B true CN111584521B (en) 2023-10-03

Family

ID=72117549

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010447754.7A Active CN111584521B (en) 2020-05-25 2020-05-25 Array substrate, manufacturing method thereof and display panel

Country Status (1)

Country Link
CN (1) CN111584521B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116825644A (en) * 2023-08-30 2023-09-29 惠科股份有限公司 Preparation method of semiconductor device, array substrate and display panel

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107818989A (en) * 2017-10-20 2018-03-20 武汉华星光电技术有限公司 Array base palte and preparation method thereof
CN107820640A (en) * 2016-11-23 2018-03-20 深圳市柔宇科技有限公司 Array base palte and its manufacture method
WO2018199037A1 (en) * 2017-04-28 2018-11-01 シャープ株式会社 Active matrix substrate and manufacturing method therfor
CN109712993A (en) * 2019-01-02 2019-05-03 南京中电熊猫平板显示科技有限公司 Array substrate and manufacturing method and display device
CN110007536A (en) * 2019-04-01 2019-07-12 深圳市华星光电技术有限公司 Thin-film transistor array base-plate and display panel

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN203085533U (en) * 2012-10-26 2013-07-24 京东方科技集团股份有限公司 Array substrate and display apparatus
CN105633016B (en) * 2016-03-30 2019-04-02 深圳市华星光电技术有限公司 The production method of TFT substrate and TFT substrate obtained

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107820640A (en) * 2016-11-23 2018-03-20 深圳市柔宇科技有限公司 Array base palte and its manufacture method
WO2018199037A1 (en) * 2017-04-28 2018-11-01 シャープ株式会社 Active matrix substrate and manufacturing method therfor
CN107818989A (en) * 2017-10-20 2018-03-20 武汉华星光电技术有限公司 Array base palte and preparation method thereof
CN109712993A (en) * 2019-01-02 2019-05-03 南京中电熊猫平板显示科技有限公司 Array substrate and manufacturing method and display device
CN110007536A (en) * 2019-04-01 2019-07-12 深圳市华星光电技术有限公司 Thin-film transistor array base-plate and display panel

Also Published As

Publication number Publication date
CN111584521A (en) 2020-08-25

Similar Documents

Publication Publication Date Title
US9735182B2 (en) Array substrate, display device, and method for manufacturing the array substrate
US9640559B2 (en) Low temperature poly-silicon array substrate and forming method thereof
JP3964223B2 (en) Thin film transistor device
US4918504A (en) Active matrix cell
US20110299004A1 (en) Array substrate and manufacturing method thereof
CN109300840B (en) Display substrate, manufacturing method thereof and display device
JP2001166338A (en) Thin-film transistor substrate for liquid crystal display device and manufacturing method therefor
US20170285430A1 (en) Array Substrate and Manufacturing Method Thereof, Display Panel and Display Device
KR20180087304A (en) Array substrate used in liquid crystal panel and manufacturing method thereof
CN111725242B (en) Array substrate, preparation method thereof and display device
CN111584521B (en) Array substrate, manufacturing method thereof and display panel
KR100502685B1 (en) Active matrix substrate and method of fabricating the same
CN212517205U (en) Low temperature poly oxide array substrate
WO2011161875A1 (en) Substrate for display device and process for production thereof, and display device
CN111725243A (en) Low-temperature polycrystalline oxide array substrate and manufacturing method thereof
CN111739841A (en) In-cell touch panel with top gate structure and manufacturing method
CN212571000U (en) Low temperature poly oxide array substrate
CN113867053B (en) Display panel and preparation method thereof
KR101268388B1 (en) Fabrication method of liquid crystal display device
CN110648965A (en) Array substrate manufacturing method and array substrate
CN111584520B (en) Array substrate, display panel and manufacturing method of array substrate
CN111584523B (en) Array substrate, display panel and manufacturing method of array substrate
CN212412051U (en) Array substrate and display panel
JPH1090711A (en) Reflection type liquid crystal display device and its manufacture
JP2004146788A (en) Manufacturing method of resin insulating layer, substrate for electro-optical device, manufacturing method of electro-optical device, and electro-optical device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Address after: No. 1778, Qinglan Road, Huangjia Street, Shuangliu District, Chengdu, Sichuan 610200

Applicant after: Chengdu BOE Display Technology Co.,Ltd.

Address before: No. 1778, Qinglan Road, Gongxing street, Shuangliu District, Chengdu, Sichuan 610200

Applicant before: CHENGDU ZHONGDIAN PANDA DISPLAY TECHNOLOGY Co.,Ltd.

CB02 Change of applicant information
GR01 Patent grant
GR01 Patent grant