CN110648965A - Array substrate manufacturing method and array substrate - Google Patents
Array substrate manufacturing method and array substrate Download PDFInfo
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- CN110648965A CN110648965A CN201911013977.6A CN201911013977A CN110648965A CN 110648965 A CN110648965 A CN 110648965A CN 201911013977 A CN201911013977 A CN 201911013977A CN 110648965 A CN110648965 A CN 110648965A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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Abstract
The invention provides a manufacturing method of an array substrate and the array substrate, wherein the manufacturing method comprises the following steps: and depositing a gate metal layer on the substrate, and forming a gate through a first photoetching process. And sequentially depositing a grid insulating layer, a metal oxide layer, an etching barrier layer and a source drain metal layer on the substrate and the grid, forming an active island on the metal oxide layer and the etching barrier layer by a second photoetching process, forming a source electrode and a drain electrode on the source drain metal layer, forming a groove region between the source electrode and the drain electrode, and extending the groove region to the etching barrier layer. And depositing a passivation layer on the gate insulating layer, the source electrode and the drain electrode, and forming a conductive through hole through a third photoetching process. And depositing a transparent conductive layer on the passivation layer, and forming a pixel electrode through a fourth photoetching process. The light shielding layer is coated on the passivation layer and at least covers the groove region, so that the problems of complex manufacturing process and high manufacturing cost of the conventional array substrate are solved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a manufacturing method of an array substrate and the array substrate.
Background
The liquid crystal display panel has many advantages of thin body, power saving, no radiation and the like, and is widely applied to electronic products such as televisions, computers, mobile phones and the like. The liquid crystal display panel generally includes an array substrate (TFT substrate), a color filter substrate (CF substrate) opposite to the array substrate, and a liquid crystal layer sandwiched between the array substrate and the color filter substrate, wherein Thin Film Transistors (TFTs) arranged in a Matrix form are disposed on the array substrate, a color resist layer for filtering light, a Black Matrix (BM) for shielding light and preventing color mixing of different colors of light, and a Photo Spacer (PS) for supporting a Cell Gap between the array substrate and the color filter substrate.
At present, the manufacturing method of the existing array substrate mainly includes six times of photoetching processes, wherein in the first step, a metal layer is deposited on a substrate base plate, and first photoetching is performed to form a grid; depositing a grid insulating layer and an Indium Gallium Zinc Oxide (IGZO) semiconductor layer in sequence, and carrying out second photoetching to form an active layer; depositing an etching barrier layer and carrying out third photoetching; depositing a source and drain metal layer, and performing fourth photoetching to form a source, a drain and a channel region; depositing a passivation layer and a flat layer, and carrying out fifth photoetching to form a conductive through hole; and sixthly, depositing a transparent conductive film, and carrying out sixth photoetching to form a pixel electrode and a communicated pattern of the conductive through hole and the pixel electrode.
The existing array substrate manufacturing process needs to carry out six times of photoetching, and the process is complex, so that the manufacturing cost of the array substrate is higher.
Disclosure of Invention
The invention provides a manufacturing method of an array substrate and the array substrate, which aim to solve the problems of complex manufacturing process and high manufacturing cost of the existing array substrate.
The invention provides a manufacturing method of an array substrate, which comprises the following steps:
depositing a gate metal layer on a substrate, and forming a gate on the gate metal layer by a first photoetching process;
sequentially depositing a grid electrode insulating layer, a metal oxide layer, an etching barrier layer and a source drain metal layer on the substrate and the grid electrode, forming an active island on the metal oxide layer and the etching barrier layer through a second photoetching process, forming a source electrode and a drain electrode on the source drain metal layer, forming a groove area between the source electrode and the drain electrode, and extending the groove area to the etching barrier layer;
depositing a passivation layer on the gate insulating layer, the source electrode and the drain electrode, and forming a conductive through hole on the passivation layer above the drain electrode through a third photolithography process;
depositing a transparent conducting layer on the passivation layer, and enabling the transparent conducting layer to form a pixel electrode through a fourth photoetching process, wherein the pixel electrode is electrically communicated with the drain electrode through the conducting via hole;
and coating a light shielding layer on the passivation layer, wherein the light shielding layer at least covers the groove region.
In a specific embodiment of the present invention, the method further comprises:
and after coating a light shielding layer on the passivation layer, forming a main spacer on the light shielding layer through a fifth photoetching process.
In a specific embodiment of the present invention, the method further comprises:
when a light shielding layer is coated on the passivation layer, the light shielding layer is coated on the pixel electrode corresponding to the gate line;
and forming a sub spacer on the light shielding layer corresponding to the groove region through a fifth photoetching process, and forming a main spacer on the light shielding layer corresponding to the gate line.
In an embodiment of the present invention, the second photolithography process specifically includes:
exposing and developing through a mask plate to form a complete light transmission area, a partial light transmission area and a light-tight area, wherein the light-tight area corresponds to the source electrode and the drain electrode, and the partial light transmission area corresponds to a groove area between the source electrode and the drain electrode;
etching the source drain metal layer, the metal oxide layer and the etching barrier layer of the complete light-transmitting area for the first time;
carrying out a photoetching ashing process for one time to remove the photoresist of a part of light-transmitting areas; and performing second etching to etch the source drain metal layer and the etching barrier layer in the partial light-transmitting region so as to form the source electrode, the drain electrode and the groove region.
In an embodiment of the present invention, the performing the second etching includes:
and etching the etching barrier layer in the partial light-transmitting area completely by controlling an etching process to form the groove area.
In an embodiment of the present invention, the second photolithography process further includes:
after the second etching is completed, N is used2And O, carrying out surface passivation treatment on the metal oxide layer in the groove region.
In a specific embodiment of the invention, the etching barrier layer is a metal oxide semiconductor layer which is resistant to corrosion of an acidic etching solution.
In a specific embodiment of the present invention, the thickness of the metal oxide layer is 2 to 10 times the thickness of the etch stop layer;
the thickness of the metal oxide layer is
The thickness of the etching barrier layer is
In an embodiment of the present invention, the molding material of the light shielding layer is a molding material of a black matrix, and includes an opaque metal material or an opaque organic material.
The invention also provides an array substrate, which is manufactured by the manufacturing method of any one of the array substrates;
the array substrate comprises a substrate, a grid insulating layer, a metal oxide layer, an etching barrier layer, a source electrode, a drain electrode, a passivation layer, a pixel electrode and a shading layer;
the gate electrode is positioned above the substrate base plate, the gate electrode insulating layer covers the gate electrode and the substrate base plate, the metal oxide layer and the etching barrier layer are sequentially arranged on the grid electrode insulating layer and correspond to the grid electrode, the source electrode and the drain electrode are respectively arranged on the etching barrier layer, a groove region is arranged between the source electrode and the drain electrode, and the trench region extends to the etch stop layer, the passivation layer covers the gate insulating layer, the source electrode, the drain electrode and the trench region, and a conductive via hole is formed on the passivation layer over the drain electrode, the pixel electrode is on the passivation layer, and the pixel electrode is communicated with the drain electrode through the conductive via hole, the light shielding layer is positioned on the passivation layer, and the light shielding layer at least covers the groove region.
The invention provides a manufacturing method of an array substrate and the array substrate, wherein the manufacturing method comprises the following steps: depositing a gate metal layer on the substrate, and forming a gate electrode on the gate metal layer by a first photoetching process; sequentially depositing a grid insulation layer, a metal oxide layer, an etching barrier layer and a source drain metal layer on the substrate and the grid, forming an active island on the metal oxide layer and the etching barrier layer through a second photoetching process, forming a source electrode and a drain electrode on the source drain metal layer, forming a groove region between the source electrode and the drain electrode, and extending the groove region to the etching barrier layer; depositing a passivation layer on the gate insulating layer, the source electrode and the drain electrode, and forming a conductive through hole on the passivation layer above the drain electrode through a third photoetching process; depositing a transparent conducting layer on the passivation layer, and forming a pixel electrode on the transparent conducting layer through a fourth photoetching process, wherein the pixel electrode is electrically communicated with the drain electrode through the conducting through hole; and coating a light shielding layer on the passivation layer, wherein the light shielding layer at least covers the groove region. The method is characterized in that a primary halftone or gray tone mask plate is used in a secondary photoetching process to simultaneously form metal oxide semiconductor layer patterns, source and drain metal electrodes, data scanning lines and groove regions among the source and drain electrodes, so that 2 times of photoetching processes are saved, the process is simple, the manufacturing efficiency is improved, the manufacturing cost is reduced, and the problems of complex manufacturing process and high manufacturing cost of the existing array substrate are solved. In addition, the light shielding layer at least covers the groove region, and after the formed array substrate is arranged in a box-to-box mode with the color film substrate, the light shielding layer is arranged close to the color film substrate and can shield light reflected by the color film substrate from irradiating the metal oxide layer in the groove region, so that the generation of illumination current carriers of the metal oxide layer is avoided, the leakage current of a TFT (thin film transistor) is reduced, the display stability and the display quality of the display panel are improved, meanwhile, the array substrate is obtained through four times of etching processes, the process is simple, and the display quality is guaranteed under the condition that the process is not increased. The array substrate solves the problem that the display quality is affected due to the fact that the leakage current of a TFT is increased because a semiconductor layer in the existing array substrate easily generates carriers.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a flowchart illustrating a method for manufacturing an array substrate according to an embodiment of the invention;
fig. 2 is a schematic plan view illustrating an array substrate before a light-shielding layer is coated thereon according to an embodiment of the invention;
fig. 3 is a schematic structural diagram of an array substrate along the AB direction after the first photolithography is completed according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view of an array substrate after performing exposure and development in a second photolithography process according to an embodiment of the present invention;
fig. 5 is a cross-sectional view of an array substrate after a first etching process in a second photolithography process is performed according to an embodiment of the present invention;
FIG. 6 is a cross-sectional view of an array substrate after ashing in a second photolithography process is performed according to an embodiment of the present invention;
FIG. 7 is a cross-sectional view of an array substrate after a second photolithography process is performed according to an embodiment of the present invention;
fig. 8 is a cross-sectional view of an array substrate after a third photolithography process is performed according to an embodiment of the present invention;
FIG. 9 is a cross-sectional view of an array substrate after a fourth photolithography process is performed according to an embodiment of the present invention;
FIG. 10 is a cross-sectional view of an array substrate after a light-shielding layer is coated;
fig. 11 is a plan view of an array substrate after a fifth photolithography process is performed according to an embodiment of the present invention;
FIG. 12 is a cross-sectional view of another array substrate after a fifth photolithography process is performed according to an embodiment of the present invention;
FIG. 13 is a plan view of another array substrate after a fifth photolithography process is performed according to an embodiment of the present invention;
fig. 14 is a circuit diagram of a GOA circuit according to an embodiment of the present invention.
Description of reference numerals:
11-a substrate base plate;
12-a gate;
13-a gate insulating layer;
14-a metal oxide layer;
15-etching the barrier layer;
16-source drain metal layer;
161-source;
162-a drain electrode;
17-photoresist;
18-a fully light transmitting area;
19-opaque areas;
20-partially light transmitting area;
21-a trench region;
22-a passivation layer;
23-a conductive via;
24-pixel electrodes;
25-gate lines;
26-data line;
27-a light-shielding layer;
271-a primary spacer;
272-a daughter spacer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be understood that, a conventional liquid crystal display panel is formed by attaching a Thin Film Transistor Array Substrate (TFT Array Substrate for short) to a Color Filter Substrate (CF Substrate for short), a pixel electrode and a common electrode are formed on the Array Substrate and the Color Filter Substrate, respectively, and liquid crystal is filled between the Array Substrate and the Color Filter Substrate.
The GOA circuit comprises a TFT region, and since a metal oxide layer in a thin film transistor belongs to a wide bandgap semiconductor, a photo-generated carrier is easily formed under light irradiation, which causes an I-V curve drift of the TFT, that is, a negative threshold voltage drift of the TFT, Vth may also be less than 0, and an electrical sub-threshold swing (S factor) value of the TFT is generally small, so when Vgs of the TFT is 0, a leakage current of the TFT is very large, which causes a slow output voltage speed and a low voltage of the GOA unit, thereby causing a GOA unit failure, affecting stability of the GOA circuit, and reducing display quality. In the display panel, the array substrate and the color film substrate are arranged in a box-to-box manner, light emitted by the backlight source irradiates the color film substrate, and may be reflected by opaque metal in the color film substrate to irradiate into the channel region, so that the metal oxide layer in the channel region generates a photon-generated carrier, thereby affecting the display quality.
The embodiment provides a manufacturing method of an array substrate and the array substrate, wherein the array substrate is formed by four times of photolithography processes, and specific examples are as follows:
example one
Fig. 1 is a flowchart of a manufacturing method of an array substrate provided in this embodiment, and fig. 2 is a schematic plan view of the array substrate provided in this embodiment before a light shielding layer is coated, where fig. 2 shows a structure of a pixel unit, it should be understood that the array substrate includes a plurality of structures shown in fig. 2 on a substrate 11, and as shown in fig. 2, the array substrate obtained by the manufacturing method of the array substrate provided in this embodiment includes: the array substrate comprises a substrate 11, and a source electrode 161, a drain electrode 162, a gate line 25, a data line 26, a conductive via 23 and a pixel electrode 24 which are arranged on the substrate 11, wherein the gate line 25 and the gate electrode 12 are communicated and positioned in the same layer, the data line 26 is communicated and positioned in the same layer with the source electrode 161, the gate line 25 and the data line 26 which are perpendicular to each other define a pixel area, and the source electrode 161, the drain electrode 162 and the pixel electrode 24 are formed in the pixel area.
Referring to fig. 1, the method for manufacturing an array substrate according to the present embodiment includes:
s101: a gate metal layer is deposited on the substrate 11, and the gate metal layer is formed into a gate electrode 12 by a first photolithography process.
Specifically, the substrate 11 may be a transparent glass substrate or a quartz substrate, and the thickness of the substrate 11 may be about the same as that of the substrate deposited by sputtering or thermal evaporationThe gate metal layer can be made of Cr, W, Ti, Ta, Mo, Al, Cu and other metals or alloys, and the gate metal layer consisting of multiple layers of metals can also meet the requirement. FIG. 3 is a schematic view of an array substrate according to the present embodimentAfter the first photolithography, the structure is schematically shown along the AB direction, and as shown in fig. 3, the gate 12 is formed by the gate 12 metal layer after the first photolithography process.
In step S101, the gate 12 and the gate line 25 are located in the same layer, and the gate line 25 may be formed at the same time as the gate 12 is formed by the first photolithography process.
S102: a gate insulating layer, a metal oxide layer 14, an etching barrier layer 15 and a source-drain metal layer 16 are sequentially deposited on the substrate 11 and the gate 12, an active island is formed on the metal oxide layer 14 and the etching barrier layer 15 through a second photolithography process, the source-drain metal layer 16 is formed into a source 161 and a drain 162, a trench region 21 is formed between the source 161 and the drain 162, and the trench region 21 extends to the etching barrier layer 15.
Specifically, on the substrate base plate 11 where S101 is completed, a thickness of Plasma Enhanced Chemical Vapor Deposition (PECVD) is depositedThe gate insulating layer 13 may be an oxide, a nitride, or an oxynitride, and the corresponding reaction gas may be SiH4，NH3，N2Or SiH2Cl2，NH3，N2A gate insulating layer 13 covers the substrate 11 and the gate electrode 12.
And then sequentially deposited on the gate insulating layer 13 by sputtering to a thickness of
Metal oxide layer 14 and
the metal oxide layer 14 is a metal oxide semiconductor layer, which may be an amorphous oxide semiconductor or a polycrystalline oxide semiconductor, and may include amorphous IGZO, HIZO, IZO, a-InZnO, ZnO: F, In2O3:Sn、In2O3:Mo、Cd2SnO4、ZnO:Al、TiO2Nb, Cd-Sn-O or other metal oxides, preferably in a thickness of
The etching stop layer 15 is a thin film layer with high conductivity, specifically, in the embodiment, the etching stop layer 15 is a metal oxide semiconductor resistant to corrosion of acid etching solution, and may include corrosion-resistant metal oxides such as Ln-ZTO, ITZO, IGO, polycrystalline IGZO, CAAC-IGZO, and the like, and the thickness thereof is preferably set to be high
In the present embodiment, the thickness of the metal oxide layer 14 is 2 to 10 times the thickness of the etch stopper layer 15.
Then depositing on the etching barrier layer 15 by sputtering or thermal evaporationThe source-drain metal layer 16, the source-drain metal may be Cr, W, Ti, Ta, Mo, or other metals and alloys, may be a single-layer metal layer or may be composed of multiple metal layers, and finally, the metal oxide layer 14 and the etching stopper layer 15 form an active island through a second photolithography process, the source-drain metal layer 16 forms a source 161 and a drain, and a trench region 21 is formed between the source 161 and the drain 162, and between the etching stopper layer 15 opposite to the source 161 and the etching stopper layer 15 opposite to the drain 162.
In this embodiment, the second photolithography process specifically includes the following steps:
fig. 4 is a cross-sectional view of the array substrate after the exposure development in the second photolithography process is completed, and as shown in fig. 3 and fig. 4, a photoresist 17 is coated on the source and drain metal layer 16, and after the exposure development is performed through a gray or halftone mask plate, the photoresist 17 forms a completely exposed region, a partially transparent region 20 and an opaque region 19, where the opaque region 19 corresponds to the source electrode 161, the drain electrode 162 and the data line 26, the partially transparent region 20 corresponds to the trench region 21 between the source electrode 161 and the drain electrode 162, and the completely transparent region 18 corresponds to a region other than the opaque region 19 and the partially transparent region 20.
Fig. 5 is a cross-sectional view of the array substrate provided in this embodiment after the first etching in the second photolithography process is completed, and as shown in fig. 5, the source/drain metal layer 16, the metal oxide layer 14, and the etch stop layer 15 in the completely light-transmitting region 18 are removed by the first etching process.
Fig. 6 is a cross-sectional view of the array substrate provided in this embodiment after ashing in the second photolithography process is completed, and as shown in fig. 6, the photoresist 17 in a part of the light-transmitting region 20 is removed by performing the photolithography ashing process once.
Fig. 7 is a cross-sectional view of the array substrate after the second photolithography process is completed, and as shown in fig. 7, a second etching is performed to etch away a portion of the source/drain metal layer 16 in the light-transmitting region 20 through the etching process, a trench region 21 is formed between the source 161 and the drain 162, the left side of the source/drain metal layer 16 that is not etched away forms the source 161, and the right side of the source/drain metal layer 16 that is not etched away forms the drain 162. Because the etching barrier layer 15 is a metal oxide semiconductor which is resistant to corrosion of acid etching liquid, when the source-drain metal layer 16 in a part of the light-transmitting area 20 is etched by using a wet etching process, the etching barrier layer 15 is not corroded, and the metal oxide layer 14 below the etching barrier layer is also protected from corrosion, so that the design can reduce the process difficulty and improve the stability of the thin film transistor.
In the second etching process, by controlling the etching process, when the source-drain metal layer 16 in the partial light-transmitting region 20 is etched, all the etching barrier layer 15 located in the partial light-transmitting region 20 is etched at the same time, that is, the trench region 21 extends toward the etching barrier layer 15, and the trench region 21 is also provided between the etching barrier layer opposite to the source electrode 161 and the etching barrier layer opposite to the drain electrode 162, that is, a channel of the thin film transistor is formed.
In this embodiment, after the second etching process is completed, N may be used2O performs a surface passivation process on the metal oxide layer 14 on the surface of the trench region 21, thereby repairing damage and contamination to the metal oxide layer 14 during etching and improving the performance of the metal oxide layer 14.
S103: a passivation layer 22 is deposited on the gate insulating layer 13, the source electrode 161 and the drain electrode 162, and a conductive via 23 is formed on the passivation layer 22 over the drain electrode 162 through a third photolithography process.
Specifically, on the substrate base plate 11 on which S102 is completed, a thickness of
The passivation layer 227, the passivation layer 22 covers the gate insulating layer 13, the source electrode 161, the drain electrode 162 and the trench region 21, the passivation layer 22 may be an oxide, a nitride or an oxynitride, the passivation layer 22 may be a single layer or a multi-layer combination, and the corresponding reaction gas may be SiH4，NH3，N2Or SiH2Cl2，NH3，N2. Fig. 8 is a cross-sectional view of the array substrate provided in this embodiment after a third photolithography process is performed, and as shown in fig. 8, a passivation layer 22 having a conductive via 23 is formed by the third photolithography process, where the conductive via 23 is located above the drain electrode 162.
S104: a transparent conductive layer is deposited on the passivation layer 22, and the transparent conductive layer is formed into a pixel electrode 24 through a fourth photolithography process, and the pixel electrode 24 is electrically connected to the drain electrode 162 through the conductive via 23.
Fig. 9 is a cross-sectional view of the array substrate provided in this embodiment after the fourth photolithography process is completed, and specifically, as shown in fig. 9, on the substrate 11 after S103 is completed, a thickness of about a deposited layer is formed by sputtering or thermal evaporation
The transparent conductive layer of (2) may be ITO or IZO, or may be another transparent metal oxide. Through the fourth photolithography process, the pixel electrode 24 is formed on the transparent conductive layer, and the pixel electrode 24 is electrically connected to the drain 162 through the conductive via 23.
In this embodiment, the pixel electrode 24 is not covered on the corresponding position of the thin film transistor, one end of the pixel electrode 24 is electrically conducted with the drain 162 through the conductive via 23, and the other end of the pixel electrode 24 extends in a direction away from the thin film transistor, so that compared with the prior art in which the pixel electrode 24 of the transparent conductive layer is disposed between the metal oxide and the source 161 and the drain 162, or the transparent conductive layer is disposed on the passivation layer 22 and covers the corresponding position of the thin film transistor, the resistance of the pixel electrode 24 can be reduced, the conductivity can be improved, the leakage current of the thin film transistor can be reduced, and the display stability can be improved.
S105: a light-shielding layer 27 is coated on the passivation layer 22, and the light-shielding layer 27 covers at least the trench region 21.
Fig. 10 is a cross-sectional view of the array substrate provided in this embodiment after the light shielding layer 27 is coated, and as shown in fig. 10, specifically, on the substrate 11 after the above-mentioned S104, a layer of organic resin may be coated on the passivation layer 22 by a suspension coating process to form the light shielding layer 27, and the light shielding layer 27 at least covers the trench region 21. The light shielding layer 27 has a function of shielding light, so that the light shielding layer 27 at least covers the groove region 21, and after the formed array substrate is arranged in a box-to-box manner with the color film substrate, the light shielding layer 27 is arranged close to the color film substrate, so that the light shielding layer 27 can shield light reflected from the color film substrate from irradiating the metal oxide layer 14 in the groove region 21, the generation of an illumination carrier of the metal oxide layer 14 is avoided, the leakage current of a TFT (thin film transistor) is reduced, and the display stability and the display quality of the display panel are improved. In addition, the manufacturing method of the array substrate is still realized through four times of photoetching processes, the process is simple, and on the basis of not increasing the photoetching processes, the generation of photo carriers of the metal oxide layer 14 in the groove region 21 is avoided, and the display quality is ensured.
In this embodiment, the light shielding layer 27 may be made of an opaque organic material. In addition, the material of the light-shielding layer 27 may be the same as the material of the opaque structure originally existing in the display panel, such as a photo spacer or a black matrix, so as to facilitate the formation of the light-shielding layer 27.
Further, in an embodiment, the method for manufacturing the array substrate further includes: after the light shielding layer 27 is coated on the passivation layer 22, the light shielding layer 27 is formed into the main spacers 271 by a fifth photolithography process.
Fig. 12 is a cross-sectional view of another array substrate provided in this embodiment after a fifth photolithography process is completed, and fig. 13 is a plan view of the another array substrate provided in this embodiment after the fifth photolithography process is completed, and as shown in fig. 12 and fig. 13, the light-shielding layer 27 is patterned into a main spacer 271 by the fifth photolithography process, the light-shielding layer 27 is used as the main spacer 271, and the light-shielding function is performed to prevent photo carriers from being generated in the metal oxide layer 14 of the trench region 21, and at the same time, the supporting function is performed to maintain a distance difference between the array substrate and the color filter substrate when the cell is set between the color filter substrate and the substrate.
In another embodiment, the method for manufacturing an array substrate further includes: when the light shielding layer 27 is coated on the passivation layer 22, the light shielding layer 27 is coated on the pixel electrode 24 corresponding to the gate line 25; then, through a fifth photolithography process, the sub-spacers 272 are formed on the light-shielding layer 27 corresponding to the trench region 21, and the main spacers 271 are formed on the light-shielding layer 27 corresponding to the gate line 25.
Specifically, in the present embodiment, when the light shielding layer 27 is coated on the passivation layer 22, the light shielding layer 27 is coated on the pixel electrode 24 corresponding to the gate line 25, fig. 11 is a plan view of the array substrate provided in this embodiment after a fifth photolithography process is completed, and as shown in fig. 11, through the fifth photolithography process, specifically, the light-shielding layer 27 on the trench region 21 may be patterned to form sub-spacers 272 by a gray-tone or halftone mask exposure and development, the light-shielding layer 27 corresponding to the gate line 25 may be patterned to form main spacers 271, the sub-spacers 272 formed by the light-shielding layer 27 may serve as a light-shielding function to prevent the metal oxide layer 14 in the trench region 21 from generating photo-carriers, when the main spacer 271 is elastically deformed under stress and the color film substrate abuts against the sub-spacer 272, the sub-spacer 272 can also play a supporting role; in addition, when the color filter substrate is aligned with the color filter substrate, the sub-spacers 272 can also facilitate alignment, and facilitate assembly of the color filter substrate and the array substrate.
In addition, the manufacturing method of the array substrate specifically illustrates a manufacturing method of TFTs in a display area of the array substrate, where the array substrate further includes a GOA circuit area, fig. 14 is a circuit diagram of the GOA circuit provided in this embodiment, the GOA circuit area is connected to the display area to perform gate driving on the display area, and the TFTs in the GOA circuit area can also be obtained by the manufacturing method.
The manufacturing method of the array substrate provided by the embodiment includes: depositing a gate metal layer on a substrate 11, and forming a gate 12 by the gate metal layer through a first photoetching process; sequentially depositing a gate insulating layer 13, a metal oxide layer 14, an etching barrier layer 15 and a source-drain metal layer 16 on the substrate base plate 11 and the gate 12, forming an active island on the metal oxide layer 14 and the etching barrier layer 15 through a second photoetching process, forming a source 161 and a drain 162 on the source-drain metal layer 16, forming a trench region 21 between the source 161 and the drain 162, and extending the trench region 21 to the etching barrier layer 15; depositing a passivation layer 22 on the gate insulating layer 13, the source electrode 161 and the drain electrode 162, and forming a conductive via 23 on the passivation layer 22 above the drain electrode 162 through a third photolithography process; depositing a transparent conductive layer on the passivation layer 22, and forming a pixel electrode 24 on the transparent conductive layer through a fourth photolithography process, wherein the pixel electrode 24 is electrically connected with the drain electrode 162 through the conductive via 23; a light-shielding layer 27 is coated on the passivation layer 22, and the light-shielding layer 27 covers at least the trench region 21. In the embodiment, the metal oxide semiconductor layer pattern, the source and drain metal electrodes, the data scanning line and the trench region between the source and drain electrodes are simultaneously formed by using the half-tone or gray-tone mask plate in the second photoetching process, so that 2 times of photoetching processes are saved, the process is simple, the manufacturing efficiency is improved, and the manufacturing cost is reduced. In addition, the light shielding layer 27 at least covers the groove region 21, and after the formed array substrate is arranged in a box-to-box manner with the color film substrate, the light shielding layer 27 is arranged close to the color film substrate, so that light reflected from the color film substrate can be shielded from irradiating the metal oxide layer 14 in the groove region 21, the generation of an irradiation carrier of the metal oxide layer 14 is avoided, the leakage current of the TFT is reduced, and the display stability and the display quality of the display panel are improved.
Example two
The present embodiment provides an array substrate, referring to fig. 10 and 11, including a substrate 11, a gate electrode 12, a gate insulating layer 13, a metal oxide layer 14, an etch stopper layer 15, a source electrode 161, a drain electrode 162, a passivation layer 22, a pixel electrode 24, and a light shielding layer 27.
Wherein, the grid electrode 12 is located above the substrate 11, the grid insulating layer 13 is covered above the grid electrode 12 and the substrate 11, the metal oxide layer 14 and the etching barrier layer 15 are sequentially arranged on the grid insulating layer 13 and correspond to the grid electrode 12, the source electrode 161 and the drain electrode 162 are respectively arranged on the etching barrier layer 15, a trench region 21 is formed between the source electrode 161 and the drain electrode 162, the trench region 21 extends to the etching barrier layer 15, the passivation layer 22 is covered on the grid insulating layer 13, the source electrode 161, the drain electrode 162 and the trench region 21, a conductive via hole 23 is arranged on the passivation layer 22 above the drain electrode 162, the pixel electrode 24 is located on the passivation layer 22, the pixel electrode 24 is communicated with the drain electrode 162 through the conductive via hole 23, the shading layer 27 is located on the passivation layer 22, and the shading layer 27 at least covers the trench region 21, after the array substrate is arranged with a color film substrate, the shading layer 27 is, therefore, the light shielding layer 27 can shield light reflected from the color film substrate from being irradiated on the metal oxide layer 14 in the trench region 21, thereby avoiding generation of light carriers in the metal oxide layer 14, reducing leakage current of the TFT, and improving display stability and display quality of the display panel.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are used merely for convenience of description and for simplicity of description, and do not indicate or imply that the device or element so referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus should not be considered as limiting the present invention.
In the description of the present invention, it is to be understood that the terms "comprises" and "comprising," and any variations thereof, as used herein, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Unless expressly stated or limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integral to one another; either directly or indirectly through intervening media, may be used in either the internal or the external relationship of the two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations. Furthermore, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A method for manufacturing an array substrate includes:
depositing a gate metal layer on a substrate, and forming a gate on the gate metal layer by a first photoetching process;
sequentially depositing a grid electrode insulating layer, a metal oxide layer, an etching barrier layer and a source drain metal layer on the substrate and the grid electrode, forming an active island on the metal oxide layer and the etching barrier layer and forming a source electrode and a drain electrode on the source drain metal layer through a second photoetching process, forming a groove area between the source electrode and the drain electrode, and extending the groove area to the etching barrier layer;
depositing a passivation layer on the gate insulating layer, the source electrode and the drain electrode, and forming a conductive through hole on the passivation layer above the drain electrode through a third photolithography process;
depositing a transparent conducting layer on the passivation layer, and enabling the transparent conducting layer to form a pixel electrode through a fourth photoetching process, wherein the pixel electrode is electrically communicated with the drain electrode through the conducting via hole;
and coating a light shielding layer on the passivation layer, wherein the light shielding layer at least covers the groove region.
2. The method of manufacturing an array substrate according to claim 1, further comprising:
and after coating a light shielding layer on the passivation layer, forming a main spacer on the light shielding layer through a fifth photoetching process.
3. The method of manufacturing an array substrate according to claim 1, further comprising:
when a light shielding layer is coated on the passivation layer, the light shielding layer is coated on the pixel electrode corresponding to the gate line;
and forming a sub spacer on the light shielding layer corresponding to the groove region through a fifth photoetching process, and forming a main spacer on the light shielding layer corresponding to the gate line.
4. The method for manufacturing the array substrate according to claim 1, wherein the second photolithography process specifically comprises:
exposing and developing through a mask plate to form a complete light transmission area, a partial light transmission area and a light-tight area, wherein the light-tight area corresponds to the source electrode and the drain electrode, and the partial light transmission area corresponds to a groove area between the source electrode and the drain electrode;
etching the source drain metal layer, the metal oxide layer and the etching barrier layer of the complete light-transmitting area for the first time;
carrying out a photoetching ashing process for one time to remove the photoresist of a part of light-transmitting areas; and performing second etching to etch the source drain metal layer and the etching barrier layer in the partial light-transmitting region so as to form the source electrode, the drain electrode and the groove region.
5. The method for manufacturing the array substrate according to claim 4, wherein the performing the second etching comprises:
and etching the etching barrier layer in the partial light-transmitting area completely by controlling an etching process to form the groove area.
6. The method for manufacturing the array substrate according to claim 5, wherein the second photolithography process further comprises:
after the second etching is completed, N is used2And O, carrying out surface passivation treatment on the metal oxide layer in the groove region.
7. The method of fabricating an array substrate according to any one of claims 1 to 6, wherein the etch stop layer is a metal oxide semiconductor layer resistant to corrosion by an acidic etching solution.
8. The method for manufacturing the array substrate according to any one of claims 1 to 6, wherein the thickness of the metal oxide layer is 2 to 10 times of the thickness of the etching barrier layer;
the thickness of the metal oxide layer is
The thickness of the etching barrier layer is
9. The method for manufacturing the array substrate according to any one of claims 1 to 6, wherein the light shielding layer is formed of a black matrix forming material including an opaque metal material or an opaque organic material.
10. An array substrate manufactured by the method of any one of claims 1 to 9;
the array substrate comprises a substrate, a grid insulating layer, a metal oxide layer, an etching barrier layer, a source electrode, a drain electrode, a passivation layer, a pixel electrode and a shading layer;
the gate electrode is positioned above the substrate base plate, the gate electrode insulating layer covers the gate electrode and the substrate base plate, the metal oxide layer and the etching barrier layer are sequentially arranged on the grid electrode insulating layer and correspond to the grid electrode, the source electrode and the drain electrode are respectively arranged on the etching barrier layer, a groove region is arranged between the source electrode and the drain electrode, and the trench region extends to the etch stop layer, the passivation layer covers the gate insulating layer, the source electrode, the drain electrode and the trench region, and a conductive via hole is formed on the passivation layer over the drain electrode, the pixel electrode is on the passivation layer, and the pixel electrode is communicated with the drain electrode through the conductive via hole, the light shielding layer is positioned on the passivation layer, and the light shielding layer at least covers the groove region.
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