CN212412051U - Array substrate and display panel - Google Patents

Abstract

The utility model provides an array substrate and display panel. The utility model provides an array substrate, including substrate base plate, the grid of setting on substrate base plate, the grid insulation layer that covers grid and substrate base plate, semiconductor layer, source electrode and drain electrode of setting on the grid insulation layer to and cover the passivation layer of semiconductor layer, source electrode, drain electrode and grid insulation layer; the source electrode and the drain electrode are respectively positioned on two sides of the semiconductor layer, and an overlapping region is arranged between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer; the protective layer is arranged on the passivation layer and correspondingly positioned above the semiconductor layer, and at least covers the region of the semiconductor layer exposed out of the source electrode and the drain electrode. The utility model provides an array substrate can prevent that semiconductor layer's semiconductor characteristic from becoming invalid, guarantees thin film transistor's demonstration drive performance.

Description

Array substrate and display panel

Technical Field

The utility model relates to a liquid crystal display technology field especially relates to an array substrate and display panel.

Background

With the development of display technology, people have increasingly growing demands for display quality of displays, and demands for displays with high quality and high resolution are more and more common and more paid more and more attention by display panel manufacturers. A Thin-film transistor (TFT) is a main driving device of a liquid crystal display panel, and is directly related to the development direction of a high-performance flat panel display device.

Fig. 1 is a schematic structural diagram of an array substrate in the prior art. As shown in fig. 1, the array substrate generally includes a substrate, and a TFT and a pixel electrode sequentially stacked on the substrate, wherein the TFT includes a gate electrode disposed on the substrate, a gate insulating layer covering the gate electrode and the substrate, an active island disposed on the gate insulating layer, and a passivation layer covering the active island and the gate insulating layer, the active island includes a semiconductor layer, and a source electrode and a drain electrode located at both sides of the semiconductor layer; the pixel electrode is disposed on the passivation layer and contacts the drain electrode through a contact hole disposed in the passivation layer. The semiconductor characteristics of the semiconductor layer are particularly important for the display driving performance of the TFT, and therefore, the passivation layer is usually made of an inorganic silicon oxide material to cover the active island for insulation protection of the semiconductor layer.

However, since the inorganic silicon oxide material has a high brittleness, cracks are easily formed in the passivation layer, which may cause corrosion of the semiconductor layer by the penetration of corrosive liquid medicine into the semiconductor layer during the subsequent fabrication process of the array substrate, and further cause the failure of the characteristics of the semiconductor layer to cause the failure of the TFT display driving performance.

SUMMERY OF THE UTILITY MODEL

The utility model provides an array substrate and display panel, array substrate can prevent that semiconductor layer's semiconductor characteristic from becoming invalid, guarantees thin film transistor's demonstration drive performance.

An aspect of the present invention provides an array substrate, which includes a substrate base plate, a gate electrode disposed on the substrate base plate, a gate insulating layer covering the gate electrode and the substrate base plate, a semiconductor layer disposed on the gate insulating layer, a source electrode and a drain electrode, and a passivation layer covering the semiconductor layer, the source electrode, the drain electrode and the gate insulating layer; the source electrode and the drain electrode are respectively positioned on two sides of the semiconductor layer, and an overlapping region is arranged between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer; the semiconductor device further comprises a protective layer arranged at intervals with the grid electrode, the semiconductor layer, the source electrode and the drain electrode, the protective layer is arranged on the passivation layer and is correspondingly positioned above the semiconductor layer, and the protective layer at least covers the region of the semiconductor layer exposed out of the source electrode and the drain electrode.

In one possible embodiment, the source electrode and the drain electrode are respectively overlapped on two sides of the semiconductor layer, the middle part of the semiconductor layer is an exposed part exposed out of the source electrode and the drain electrode, and the protective layer covers the exposed part.

In one possible embodiment, the orthographic projection of the protective layer on the semiconductor layer has an overlap region with both the source and the drain.

In one possible embodiment, the width of the overlapping region between the protective layer and the source electrode and between the protective layer and the drain electrode is 3 μm to 5 μm.

In one possible embodiment, the edge of the protective layer exceeds the edge of the exposed portion, and the distance between the edge of the protective layer and the edge of the exposed portion is greater than or equal to 5 μm.

In one possible embodiment, the semiconductor layer is a metal oxide semiconductor layer, the passivation layer is an amorphous silicon layer, and the protection layer is a metal oxide layer.

In one possible embodiment, the passivation layer comprises a silicon oxide layer.

In a possible implementation mode, a pixel electrode is further arranged on the passivation layer, the pixel electrode is arranged at a distance from the protection layer, a contact hole corresponding to a local area of the drain electrode is arranged in the passivation layer, and a part of the pixel electrode extends into the contact hole to be in contact with the drain electrode.

In one possible embodiment, the pixel electrode and the protective layer are both made of indium tin oxide.

Another aspect of the present invention provides a display panel, which includes an opposite substrate, a liquid crystal layer and an array substrate as described above, wherein the opposite substrate and the array substrate are disposed oppositely, and the liquid crystal layer is disposed between the opposite substrate and the array substrate.

The utility model provides an array substrate and display panel, array substrate sets up the protective layer through the position that corresponds the semiconductor layer top on the passivation layer, and the protective layer covers the region that exposes outside source electrode and drain electrode of semiconductor layer at least, even there is the crackle in the passivation layer like this, because the passivation layer top in the region that exposes of semiconductor layer covers there is the protective layer, array substrate is in the preparation process after the passivation layer, owing to receive the barrier effect of protective layer, can avoid corrosive liquid medicine to pass through the crack infiltration of passivation layer to the regional surface that exposes of semiconductor layer, and then can prevent that semiconductor layer from being corroded by corrosive liquid medicine and producing the defect, avoid leading to the semiconductor characteristic of semiconductor layer to become invalid from this, thereby prevent that thin film transistor from taking place to show the drive inefficacy and influencing.

Drawings

In order to illustrate the embodiments of the present invention or the technical solutions in the prior art more clearly, a brief description will be given below of the drawings required for the description of the embodiments or the prior art, and it is obvious that the drawings in the following description are some embodiments of the present invention. For a person skilled in the art, without inventive effort, further figures can be obtained from these figures.

Fig. 1 is a schematic structural diagram of an array substrate in the prior art;

fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.

Description of reference numerals:

1-a substrate base plate; 2-a grid; 3-a gate insulating layer; 41-source electrode; 42-a semiconductor layer; 421-an exposed portion; 43-a drain electrode; 5-a passivation layer; 51-a contact hole; 6-a protective layer; 7-pixel electrodes.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

Example one

Fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention. As shown in fig. 2, the present embodiment provides an array substrate including a substrate 1, a gate electrode 2 disposed on the substrate 1, a gate insulating layer 3 covering the gate electrode 2 and the substrate 1, a semiconductor layer 42 disposed on the gate insulating layer 3, a source electrode 41 and a drain electrode 43, and a passivation layer 5 covering the semiconductor layer 42, the source electrode 41, the drain electrode 43 and the gate insulating layer 3.

As shown in fig. 2, the array substrate includes a substrate 1, the substrate 1 serves as a base supporting structure of the array substrate, and the remaining hierarchical structures of the array substrate are formed on the substrate 1, wherein the substrate 1 may be a quartz substrate or a glass substrate.

It should be noted that, for an array substrate applied in a liquid crystal display panel, the array substrate forms a pixel region for displaying an image on a substrate 1, a plurality of data lines and a plurality of scan lines are distributed in the pixel region, the pixel region is divided into a plurality of sub-pixel regions arranged in a matrix form in a plane by the plurality of data lines and the plurality of scan lines, at least one Thin-film transistor (TFT) is arranged in each sub-pixel region, and the display state of the corresponding sub-pixel region is controlled by each TFT.

Specifically, be parallel to each other and the equidistance interval sets up between many data lines, be parallel to each other and the equidistance interval sets up between many scanning lines, and data line and scanning line violently indulge crisscross setting in space, for example, use array substrate's shape to be the rectangle for example, the data line can extend along array substrate's width direction, the scanning line can extend along array substrate's length direction, with through data line and scanning line with the pixel region partition on the array substrate for being a plurality of sub-pixel regions that the matrix was arranged. For example, a plurality of sub-pixel regions having the same size and shape may be formed.

In a specific application, a driving power supply is usually disposed on the array substrate, for example, the driving power supply is disposed at an edge portion of one side or two sides of the array substrate, the driving power supply is connected to the data lines and the scanning lines near the edge of the array substrate, so as to drive all the data lines and the scanning lines in the pixel region, and then the TFT in each sub-pixel region is driven through the data lines and the scanning lines, so as to drive the liquid crystal display panel through the TFT to display an image. The data lines and the scanning lines can drive the TFTs in a progressive manner.

As shown in fig. 2, a TFT is provided on the substrate base 1, and the TFT is composed of a gate electrode 2, a gate insulating layer 3, a source electrode 41, a semiconductor layer 42, a drain electrode 43, and a passivation layer 5. Wherein the gate electrode 2 is directly disposed on the substrate base plate 1, the gate insulating layer 3 covers the gate electrode 2, and the source electrode 41, the semiconductor layer 42, and the drain electrode 43 are disposed on the gate insulating layer 3. The gate electrode 2 and the semiconductor layer 42 are spaced apart by a gate insulating layer 3 to insulate and isolate the gate electrode 2 from the semiconductor layer 42.

The source 41 and the drain 43 are respectively located at two sides of the semiconductor layer 42, and an overlap region is formed between the source 41 and the semiconductor layer 42 and between the drain 43 and the semiconductor layer 42, so that electrical signals can be sequentially transmitted among the source 41, the semiconductor layer 42 and the drain 43.

The source electrode 41 may be disposed on the same layer as the data line corresponding to each sub-pixel region, that is, the data line and the source electrode 41 are formed on the gate insulating layer 3, and the source electrode 41 and the data line may be formed using the same material and through the same process step, and the source electrode 41 may be a branch connected to the data line and located in each sub-pixel region; the gate electrode 2 may be disposed on the same layer as the scan line corresponding to the source electrode 41, that is, the scan line and the gate electrode 2 are formed on the substrate 1, and the gate electrode 2 and the scan line may be made of the same material and formed through the same process step, and the gate electrode 2 may be a branch connected to the scan line and located in each sub-pixel region.

In addition, the drain electrode 43 disposed on the same layer as the source electrode 41 and spaced apart from the other side of the semiconductor layer 42 may be formed of the same material and through the same process step as the data line.

Illustratively, the scanning lines and the gate 2 are formed on the substrate base plate 1, and the specific process may be that a gate metal layer is formed on the substrate base plate 1 by deposition through a magnetron sputtering process, and then the gate metal layer is subjected to a photolithography process to form the patterned scanning lines and the patterned gate 2; similarly, the data line, the source electrode 41 and the drain electrode 43 are formed on the gate insulating layer 3 by depositing a source metal layer on the gate insulating layer 3 by a magnetron sputtering process, and then performing a photolithography process on the source metal layer to form the patterned data line, the source electrode 41 and the drain electrode 43.

The semiconductor layer 42 is usually made of a material different from the source electrode 41 and the drain electrode 43 so that the semiconductor layer 42 has semiconductor characteristics. Before forming the source electrode 41 and the drain electrode 43, a semiconductor metal layer may be deposited on the gate insulating layer 3 by a magnetron sputtering process to form a semiconductor layer 42, and then a patterned semiconductor layer 42 may be formed by a photolithography process, and then the source electrode 41 and the drain electrode 43 may be formed on the semiconductor layer 42, where the source electrode 41 and the drain electrode 43 are respectively overlapped on two sides of the semiconductor layer 42; alternatively, the source electrode 41 and the drain electrode 43 are formed on the gate insulating layer 3, then a semiconductor metal layer is deposited on the gate insulating layer 3 by a magnetron sputtering process, the semiconductor metal layer covers the source electrode 41 and the drain electrode 43, and finally a patterned semiconductor layer 42 is formed by a photolithography process, wherein two sides of the semiconductor layer 42 are respectively overlapped on the source electrode 41 and the drain electrode 43.

The passivation layer 5 covers the gate insulating layer 3, and the passivation layer 5 covers the semiconductor layer 42, the passivation layer 5 also serving as an insulating spacer. Explaining in the stacking direction of the array substrate, the passivation layer 5 and the gate insulating layer 3 located below the semiconductor layer 42 can both play a role in protecting the semiconductor layer 42, and by respectively arranging the gate insulating layer 3 and the passivation layer 5 on two sides of the semiconductor layer 42, the gate insulating layer 3 and the passivation layer 5 can prevent other structural layers from influencing the semiconductor layer 42, and the semiconductor characteristics of the semiconductor layer 42 are protected from being affected.

The switching state of the TFT can be controlled by the semiconductor characteristics of the semiconductor layer 42. Specifically, after the driving power source drives the data line and the scan line, the scan line is energized to generate an electrical signal and transmit the electrical signal to the gate electrode 2, the semiconductor layer 42 spaced from the gate electrode 2 by the gate insulating layer 3 can be made conductive after the gate electrode 2 is charged, the conductive semiconductor layer 42 can transmit the electrical signal of the source electrode 41 (the data line is energized to generate the electrical signal and transmit the electrical signal to the source electrode 41) to the drain electrode 43, and further turn on the TFT to enable the TFT to be in an on state, and at this time, the TFT can control the corresponding sub-pixel region to be in a bright spot state capable of displaying images.

When the scanning line is not powered on, no electric signal is applied to the gate 2, so the semiconductor layer 42 still maintains its semiconductor characteristics, the electric signal of the source 41 cannot be transmitted to the drain 43 through the semiconductor layer 42, and at this time, the TFT is in an off state, and the corresponding sub-pixel region is in a dark spot state where no image can be displayed.

However, since the passivation layer 5 is generally made of an inorganic amorphous silicon material such as silicon oxide or silicon nitride, which makes the passivation layer 5 more brittle, cracks may be formed in the passivation layer 5 during the process of forming the passivation layer 5, or during the process after the array substrate is formed on the passivation layer 5, and during the process of transporting the array substrate.

Once the passivation layer 5 has cracks, during a subsequent manufacturing process of the array substrate (after the passivation layer 5 is formed), a corrosive chemical used in the process may penetrate into the structural layer where the semiconductor layer 42 is located through the cracks in the passivation layer 5. Since the source electrode 41 and the drain electrode 43 are provided on both sides of the semiconductor layer 42, and the source electrode 41 and the drain electrode 43 overlap both sides of the semiconductor layer 42, respectively, but the source electrode 41 and the drain electrode 43 have a gap therebetween, the semiconductor layer 42 is inevitably exposed to the outside of the source electrode 41 and the drain electrode 43, and if the corrosive chemical liquid contacts the exposed region of the semiconductor layer 42, the semiconductor layer 42 is corroded, and the semiconductor layer 42 is locally damaged.

If the semiconductor layer 42 is corroded by the corrosive chemical solution and a local defect is generated, the semiconductor characteristics of the semiconductor layer 42 are deteriorated. Once the semiconductor characteristics of the semiconductor layer 42 fail, the semiconductor layer 42 can transmit the electric signal in the source electrode 41 to the drain electrode 43 even if the scanning line is not energized. Therefore, whether the scanning line is electrified or not, the TFT is always in a conducting state, so that the display driving performance of the TFT is invalid, the sub-pixel area controlled by the TFT is always kept in a normally-on state, and the part of the display panel corresponding to the sub-pixel area is always a normally-on point, so that the display effect of the display panel is influenced.

As shown in fig. 2, in order to prevent the semiconductor layer 42 from being corroded by a corrosive chemical solution in a subsequent process to cause a failure of the semiconductor characteristics of the semiconductor layer 42, in this embodiment, a protective layer 6 is further disposed in the array substrate, the protective layer 6 is disposed on the passivation layer 5, the protective layer 6 is correspondingly located above the semiconductor layer 42, and the protective layer 6 at least covers a region of the semiconductor layer 42 exposed outside the source electrode 41 and the drain electrode 43.

Specifically, by providing the protection layer 6 on the passivation layer 5, the protection layer 6 is correspondingly disposed above the semiconductor layer 42, and the protection layer 6 at least covers the region of the semiconductor layer 42 exposed outside the source electrode 41 and the drain electrode 43, so that, by the blocking effect of the protection layer 6, even if there is a crack in the region of the passivation layer 5 corresponding to the semiconductor layer 42, the corrosive chemical liquid in the subsequent process cannot penetrate into the local region of the passivation layer 5 covered with the protection layer 6, and further, the exposed region of the semiconductor layer 42 cannot be corroded by the corrosive chemical liquid, and thus the semiconductor characteristics cannot be lost due to corrosion.

The semiconductor characteristic of the semiconductor layer 42 is maintained through the protection effect of the protection layer 6 on the semiconductor layer 42, then the semiconductor layer 42 can effectively control the on-off state of the TFT, the display driving performance failure of the TFT is avoided, and then the normally-on state of the sub-pixel area controlled by the TFT cannot occur, so that the display effect of the display panel can be guaranteed to be unaffected.

In this embodiment, the protective layer 6 is only used to cover the passivation layer 5 at a portion corresponding to the semiconductor layer 42, so as to prevent the semiconductor layer 42 from being corroded by the corrosive chemical. The protective layer 6 is not connected to other circuits such as the gate electrode 2, the source electrode 41, and the drain electrode 43 in the array substrate, and the protective layer 6 is provided above the gate electrode 2, the semiconductor layer 42, the source electrode 41, and the drain electrode 43 at an interval, which corresponds to the protective layer 6 being provided separately.

In this case, it is to be avoided that the exposed region of the semiconductor layer 42 is located outside the orthographic projection of the protection layer 6, so that if there is a crack in the passivation layer 5 located outside the protection layer 6 and corresponding to the exposed region of the semiconductor layer 42, the corrosive chemical may penetrate into the exposed region of the semiconductor layer 42 through the crack, and the semiconductor layer 42 may be corroded to lose the semiconductor property. Therefore, it is ensured that the protective layer 6 can completely cover the region of the semiconductor layer 42 exposed outside the source electrode 41 and the drain electrode 43, so that the protective layer 6 can effectively isolate the corrosive chemical liquid that may penetrate into the exposed region of the semiconductor layer 42.

As shown in fig. 2, in the array substrate of this embodiment, a pixel electrode 7 may be further disposed on the passivation layer 5, the pixel electrode 7 is disposed at a distance from the protection layer 6, a contact hole 51 corresponding to a local area of the drain electrode 43 is disposed in the passivation layer 5, and a portion of the pixel electrode 7 extends into the contact hole 51 and contacts the drain electrode 43.

The passivation layer 5 is further provided with a pixel electrode 7, the pixel electrode 7 is in contact with the drain electrode 43, and the drain electrode 43 transmits an electric signal to the pixel electrode 7, thereby charging and discharging the pixel electrode 7. Since the pixel electrode 7 is disposed on the passivation layer 5, and the passivation layer 5 is spaced between the pixel electrode 7 and the drain electrode 43, it is necessary to provide a contact hole 51 in the passivation layer 5, and the contact hole 51 corresponds to a local area of the drain electrode 43 and penetrates through two sides of the passivation layer 5, so that a portion of the pixel electrode 7 extending into the contact hole 51 can contact the drain electrode 43, and the drain electrode 43 can transmit an electrical signal to the pixel electrode 7.

In this embodiment, the corrosive chemical solution introduced into the array substrate in the subsequent process after the passivation layer 5 is formed may be, for example, a chemical solution involved in the process of forming the pixel electrode 7. The forming process of the pixel electrode 7 may specifically be: firstly, a transparent conducting layer is deposited on a passivation layer 5, then a patterned pixel electrode 7 is formed by carrying out a photoetching process on the transparent conducting layer, the formed pixel electrode 7 corresponds to each sub-pixel region, and a gap is formed between the pixel electrodes 7 between adjacent sub-pixel regions, so that the pixel electrodes 7 in each sub-pixel region can independently control the sub-pixel region.

In the process of forming the pixel electrode 7 by performing the photolithography process on the transparent conductive layer, an etching solution is introduced during the etching process, and the etching solution is usually corrosive, and if there is a crack in the passivation layer 5, the etching solution penetrates into the passivation layer 5 without the protection of the protection layer 6, so as to corrode the semiconductor layer 42.

Alternatively, the corrosive liquid may be a cleaning liquid introduced when the array substrate is subsequently cleaned after the array substrate is manufactured, or the corrosive liquid may be introduced in other links, which is not specifically limited in this embodiment.

As to the specific constitution of the passivation layer 5, in one possible embodiment, the passivation layer 5 is an amorphous silicon layer. In this embodiment, the passivation layer 5 is an amorphous silicon layer, for example, the passivation layer 5 may be a silicon oxide layer, the silicon oxide layer is spaced between the pixel electrode 7 and the semiconductor layer 42, and since the silicon oxide layer is rich in oxygen atoms, if metal ions in the pixel electrode 7 diffuse into the semiconductor layer 42, the metal ions will be firstly combined with the oxygen atoms in the silicon oxide layer, so that the silicon oxide layer will consume the metal ions, so as to prevent the metal ions from diffusing into the semiconductor layer 42 to be combined with the oxygen atoms in the semiconductor layer 42 to affect the semiconductor characteristics of the semiconductor layer 42.

Further, oxygen atoms in the silicon oxide layer may diffuse into the semiconductor layer 42, and supplement oxygen atoms in the semiconductor layer 42, thereby maintaining the semiconductor characteristics of the semiconductor layer 42.

In some other embodiments, the passivation layer 5 may include not only a silicon oxide layer, for example, the passivation layer 5 may include a silicon oxide layer directly stacked on the gate insulating layer 3 and a silicon nitride layer stacked on the silicon oxide layer. As described above, the silicon oxide layer is in direct contact with the exposed region of the semiconductor layer 42, and the silicon oxide layer has high density, and the silicon oxide layer can prevent metal ions in the pixel electrode 7 from diffusing into the semiconductor layer 42 and can supplement oxygen atoms in the semiconductor layer 42, thereby helping to maintain the semiconductor characteristics of the semiconductor layer 42.

Opposite to substrate base plate 1, passivation layer 5 is located the outside of array base plate or is close to the outside of array base plate, through set up one deck silicon nitride layer again on silicon oxide layer, and pixel electrode 7 directly forms on silicon nitride layer, and silicon nitride layer has the performance of better isolation steam as array base plate outside protective layer 6, can keep apart external steam, prevents that steam from causing the influence to semiconductor layer 42.

For a specific configuration of the semiconductor layer 42, in one possible embodiment, the semiconductor layer 42 may be a metal oxide semiconductor layer. Compared with the traditional mode that an amorphous silicon material is adopted as the semiconductor layer 42, the carrier mobility of the metal oxide semiconductor layer is higher, the charge-discharge rate of the TFT to the pixel electrode 7 can be effectively improved, and the response speed of the array substrate is further improved; meanwhile, in the case of achieving the same effect, the thickness required for the metal oxide semiconductor layer is smaller than that required for using amorphous silicon as the semiconductor layer 42, and the cost of the metal oxide semiconductor layer is also lower.

For example, the metal oxide semiconductor layer may be made of metal oxide such as Indium Gallium Zinc Oxide (IGZO) or indium gallium oxide.

Since the semiconductor layer 42 is a metal oxide semiconductor layer, the semiconductor layer 42 is easily corroded, and therefore, by providing the protective layer 6 on the passivation layer 5 in a region corresponding to the semiconductor layer 42, the protective layer 6 covers at least the exposed region of the semiconductor layer 42. The protective layer 6 thus serves to cover the cracks in the passivation layer 5, and the protective layer 6 can prevent the corrosive chemical from penetrating into the cracks in the passivation layer 5, thereby preventing the corrosive chemical from corroding the metal oxide semiconductor layer and protecting the semiconductor characteristics of the semiconductor layer 42.

With regard to the specific construction of the protective layer 6, in one possible embodiment, the protective layer 6 may be a metal oxide layer. In this embodiment, protective layer 6 specifically can be metal oxide layer, compares in non-metal oxide layer, and metal oxide layer's compactness is better, and metal oxide layer's intensity is better, is difficult for producing the crackle in protective layer 6 like this, and the corrosivity liquid medicine can not permeate to protective layer 6 in, and then can not permeate passivation layer 5 through protective layer 6 in, protective layer 6 can play the effect of effective separation corrosivity liquid medicine corruption semiconductor layer 42.

In addition, the metal oxide layer is used as the protective layer 6, and the compactness and the strength of the metal oxide layer are better, so that the thickness of the protective layer 6 can be correspondingly reduced on the basis of ensuring that the protective layer 6 can prevent corrosive liquid medicine from permeating into the passivation layer 5, and the manufacturing cost of the protective layer 6 is reduced.

In this embodiment, the pixel electrode 7 may be made of indium tin oxide. The pixel electrode 7 may be made of Indium Tin Oxide (ITO), that is, the pixel electrode 7 is an ITO thin film. ITO has good conductivity and transparency, and can be easily etched into fine patterns in acid solution, wherein the light transmittance is more than 90%. Therefore, ITO is generally sprayed on glass, plastic, and electronic display panels to be used as a transparent conductive film, and also reduces electron radiation harmful to the human body and ultraviolet and infrared rays.

In order to simplify the structure of the array substrate and improve the manufacturing efficiency of the array substrate, in one embodiment, the protection layer 6 disposed on the passivation layer 5 may also be made of indium tin oxide. By using the ITO layer as a metal oxide layer, the protective layer 6 can effectively isolate corrosive liquid medicine from permeating into the passivation layer 5 area covered by the ITO layer, and the protective layer 6 and the pixel electrode 7 are both made of ITO, so that the protective layer 6 and the pixel electrode 7 can be formed through the same process steps, the manufacturing efficiency of the array substrate is improved, and the manufacturing cost of the array substrate is reduced.

Specifically, an ITO thin film is deposited on the passivation layer 5, and then the protective layer 6 and the pixel electrode 7 are formed by performing a photolithography process on the ITO thin film and performing the same exposure and etching steps. Wherein, the structure of a mask plate adopted in the exposure process can be designed, so that a space is formed between the formed protective layer 6 and the pixel electrode 7; in addition, in the present embodiment, specific thicknesses of the protective layer 6 and the pixel electrode 7 are not limited, and the thicknesses of the two may be the same, or the thicknesses of the two may be different by setting different transmittances in regions corresponding to the two on the mask plate.

In order to enable the protective layer 6 to effectively protect the semiconductor layer 42 from corrosion, in one possible embodiment, the edge of the protective layer 6 may extend beyond the edge of the exposed portion 421 of the semiconductor layer 42, and the distance between the edge of the protective layer 6 and the edge of the exposed portion 421 of the semiconductor layer 42 may be greater than or equal to 5 μm.

The exposed portion 421 of the semiconductor layer 42 is a channel region of the semiconductor layer 42 exposed outside the source electrode 41 and the drain electrode 43.

By making the edge of the protective layer 6 beyond the exposed portion 421 of the semiconductor layer 42, it is ensured that the protective layer 6 entirely covers the portion of the semiconductor layer 42 exposed outside the source electrode 41 and the drain electrode 43, and the protective layer 6 exceeds the edge of the exposed portion 421 of the semiconductor layer 42 by at least 5 μm, which increases the area of the protective layer 6 covering the semiconductor layer 42, and even if there is a crack in the passivation layer 5 inclined from the periphery of the exposed area of the semiconductor layer 42 into the exposed area of the semiconductor layer 42, the protective layer 6 can effectively cover the crack, to improve the blocking range of the protective layer 6 against the corrosive chemical.

When the source electrode 41, the semiconductor layer 42 and the drain electrode 43 are formed on the gate insulating layer 3, in one embodiment, the source electrode 41 and the drain electrode 43 may be formed on the gate insulating layer 3, and then the semiconductor layer 42 may be formed between the source electrode 41 and the drain electrode 43, so that both sides of the semiconductor layer 42 respectively overlap the source electrode 41 and the drain electrode 43, the entire semiconductor layer 42 is exposed outside the source electrode 41 and the gate electrode 2, and the exposed portion 421 of the semiconductor layer 42 is the entire surface thereof; at this time, the protective layer 6 needs to be able to cover the entire surface of the semiconductor layer 42, and the edge of the protective layer 6 exceeds the edge of the entire semiconductor layer 42 by at least 5 μm.

In another embodiment, when the source electrode 41, the semiconductor layer 42 and the drain electrode 43 are formed on the gate insulating layer 3, the semiconductor layer 42 may be formed on the gate insulating layer 3, and then the source electrode 41 and the drain electrode 43 may be formed on both sides of the semiconductor layer 42, respectively, so that the source electrode 41 and the drain electrode 43 overlap both sides of the semiconductor layer 42, and the middle portion of the semiconductor layer 42 not covered by the source electrode 41 and the drain electrode 43 is the exposed portion 421; at this time, the protective layer 6 needs to be able to completely cover the exposed central portion of the semiconductor layer 42, and the edge of the protective layer 6 exceeds the edge of the exposed portion 421 of the semiconductor layer 42 by at least 5 μm.

As shown in fig. 2, in the case where the source electrode 41 and the drain electrode 43 are respectively overlapped on both sides of the semiconductor layer 42, in the present embodiment, the orthographic projection of the protective layer 6 on the semiconductor layer 42 may have an overlapping region with both the source electrode 41 and the drain electrode 43 on the basis of ensuring that the protective layer 6 can fully cover the exposed portion 421 of the middle region of the semiconductor layer 42.

By the fact that the orthographic projection of the protective layer 6 on the semiconductor layer 42 has an overlapping region with the source electrode 41 and the drain electrode 43, on one hand, the edge of the protective layer 6 can be guaranteed to exceed the edge of the exposed part 421 of the semiconductor layer 42, and the protective layer 6 can be guaranteed to completely cover the exposed part 421 of the semiconductor layer 42, so that the protective layer 6 can effectively protect the semiconductor layer 42 from being corroded by corrosive liquid medicine; on the other hand, the protective layer 6 covers at least partial regions of the source electrode 41 and the drain electrode 43, and further the protective layer 6 also has a protective effect on the partial regions of the source electrode 41 and the drain electrode 43 covered by the protective layer 6, so that the source electrode 41 and the drain electrode 43 can be prevented from being corroded by corrosive liquid medicine, the source electrode 41 and the drain electrode 43 are prevented from being damaged due to corrosion, and the source electrode 41 and the drain electrode 43 can be ensured to have better conductivity.

Specifically, the width of the overlapping region between the protective layer 6 and the source electrode 41 and between the protective layer 6 and the drain electrode 43 may be 3 μm to 5 μm. Thus, the protective layer 6 and the source 41 and the protective layer 6 and the drain 43 have sufficient overlapping widths to ensure the protective effect of the protective layer 6 on the semiconductor layer 42; in addition, the overlapping regions between the protective layer 6 and the source 41 and between the protective layer 6 and the drain 43 are not too large, so that the edge of the protective layer 6 is prevented from contacting the edge of the pixel electrode 7 or being too close to the edge of the pixel electrode 7, and the protective layer 6 does not affect the pixel electrode 7.

Illustratively, the width of the overlapping region between the protective layer 6 and the source electrode 41 and between the protective layer 6 and the drain electrode 43 may be 3 μm, 3.5 μm, 4 μm, 4.5 μm, or 5 μm.

According to the array substrate provided by the embodiment, the protective layer is arranged on the passivation layer corresponding to the position above the semiconductor layer, and the protective layer at least covers the region, exposed out of the source electrode and the drain electrode, of the semiconductor layer, even if a crack exists in the passivation layer, the protective layer covers the passivation layer of the exposed region of the semiconductor layer, and in the manufacturing process of the array substrate after the passivation layer, due to the blocking effect of the protective layer, corrosive liquid medicine can be prevented from permeating into the surface of the exposed region of the semiconductor layer through the crack of the passivation layer, so that the semiconductor layer can be prevented from being corroded by the corrosive liquid medicine to generate defect, the semiconductor characteristic failure of the semiconductor layer is avoided, and the display effect of the display panel is prevented from being influenced due to the.

Example two

The present embodiment provides a display panel, which includes an opposite substrate, a liquid crystal layer, and the array substrate of the first embodiment, wherein the opposite substrate and the array substrate are disposed opposite to each other, and the liquid crystal layer is disposed between the opposite substrate and the array substrate.

The opposite substrate arranged opposite to the array substrate can be a color film substrate, for example, an electric field is applied between the array substrate and the color film substrate, and the arrangement condition of liquid crystal molecules in a liquid crystal layer can be controlled by voltage in the electric field, so that the purposes of shading and transmitting light are achieved, and the display panel can display images.

The structure, function and operation principle of the array substrate are described in detail in the first embodiment, and are not described herein again.

Another aspect of the present embodiment also provides a display device, which includes the above display panel. For example, in this embodiment, the display device may be a liquid crystal television, a notebook computer, a tablet computer, an electronic paper, or the like.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.

Claims (10)

1. An array substrate is characterized by comprising a substrate base plate, a grid electrode arranged on the substrate base plate, a grid insulating layer covering the grid electrode and the substrate base plate, a semiconductor layer, a source electrode and a drain electrode arranged on the grid insulating layer, and a passivation layer covering the semiconductor layer, the source electrode, the drain electrode and the grid insulating layer; the source electrode and the drain electrode are respectively positioned on two sides of the semiconductor layer, and an overlapping region is arranged between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer; the semiconductor device further comprises a protective layer arranged at intervals with the grid electrode, the semiconductor layer, the source electrode and the drain electrode, the protective layer is arranged on the passivation layer and correspondingly located above the semiconductor layer, and the protective layer at least covers the region of the semiconductor layer exposed out of the source electrode and the drain electrode.

2. The array substrate of claim 1, wherein the source electrode and the drain electrode are respectively overlapped at two sides of the semiconductor layer, the middle part of the semiconductor layer is an exposed part exposed out of the source electrode and the drain electrode, and the protective layer covers the exposed part.

3. The array substrate of claim 2, wherein an orthographic projection of the protective layer on the semiconductor layer has an overlapping region with both the source electrode and the drain electrode.

4. The array substrate of claim 3, wherein the width of the overlapping region between the protective layer and the source electrode and between the protective layer and the drain electrode is 3 μm-5 μm.

5. The array substrate of claim 2, wherein the edge of the protection layer exceeds the edge of the exposed portion, and a distance between the edge of the protection layer and the edge of the exposed portion is greater than or equal to 5 μm.

6. The array substrate of any one of claims 1-5, wherein the semiconductor layer is a metal oxide semiconductor layer, the passivation layer is an amorphous silicon layer, and the protective layer is a metal oxide layer.

7. The array substrate of claim 6, wherein the passivation layer comprises a silicon oxide layer.

8. The array substrate of claim 7, wherein the passivation layer further has a pixel electrode disposed thereon and spaced apart from the protective layer, the passivation layer has a contact hole corresponding to a local region of the drain electrode, and a portion of the pixel electrode extends into the contact hole and contacts the drain electrode.

9. The array substrate of claim 8, wherein the pixel electrode and the protective layer are each formed of indium tin oxide.

10. A display panel comprising a counter substrate, a liquid crystal layer and the array substrate of any one of claims 1 to 9, wherein the counter substrate and the array substrate are disposed opposite to each other, and the liquid crystal layer is disposed between the counter substrate and the array substrate.

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