JPH03148636A - Manufacture of active matrix type liquid crystal display element - Google Patents

Manufacture of active matrix type liquid crystal display element

Info

Publication number
JPH03148636A
JPH03148636A JP1287509A JP28750989A JPH03148636A JP H03148636 A JPH03148636 A JP H03148636A JP 1287509 A JP1287509 A JP 1287509A JP 28750989 A JP28750989 A JP 28750989A JP H03148636 A JPH03148636 A JP H03148636A
Authority
JP
Japan
Prior art keywords
film
electrode
substrate
liquid crystal
scanning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1287509A
Other languages
Japanese (ja)
Inventor
Masushi Honjo
本城 益司
Motohiro Kigoshi
基博 木越
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP1287509A priority Critical patent/JPH03148636A/en
Publication of JPH03148636A publication Critical patent/JPH03148636A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a large aperture rate and increase the transmissivity by providing a transparent conductive film on a substrate, performing back exposure using scanning electrode wires and a semiconductor film as a mask, and then patterning the film and thus forming picture element electrodes. CONSTITUTION:The glass substrate 30 is provided with scanning electrode lines 36 and gate electrodes 31 which are connected thereto, and they are covered with a gate insulating film 32. Then a protection insulating film 33 is arranged on an Si film 34 and a drain electrode 38 and a source electrode 39 are formed across an Si film 35 with low resistance to form a TFT 40. When a picture element electrode 37 is formed, the scanning electrode lines 36 and Si films are utilized for the back exposure to form picture element electrodes inside measures. Thus, TFTs are formed in matrix nearby the intersections of the scanning lines 36 and signal electrode lines 34. The pattern of an insulating film 41 is formed and covered with an orienting film 42. A light shield film 45, an ITO electrode 46, and an orienting film 47 are provided on an opposite substrate 44 at positions facing the TFTs, the substrates are adhered together across spacers, and liquid crystal is injected to complete the element. In this configuration, the electrodes 37 can be put extremely close to the signal electrode lines and the aperture rate is improved.

Description

【発明の詳細な説明】 [発明の目的1 (産業上の利用分野) この発明はアクティブマトリクス型液晶表示素子の製造
方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention 1 (Field of Industrial Application) This invention relates to a method for manufacturing an active matrix liquid crystal display element.

(従来の技術) 電子機器の小形化、軽量化及び低消費電力化が進む中で
、ディスプレイの分野においても、CRT (Cath
ode Ray Tube)に代わるものとして、フラ
ットパネルディスプレイの研究・開発が活発に行なわれ
ている。この中でも、液晶ディスプレイは大面積表示が
可能であること、フルカラー化が可能であること、及び
低電流・低電圧動作であること等の点で最も注目を集め
ている。
(Prior art) As electronic devices become smaller, lighter, and consume less power, CRT (Cathode
Research and development of flat panel displays is being actively conducted as an alternative to ode ray tubes. Among these, liquid crystal displays are attracting the most attention because of their ability to display large areas, full color display, and low current/low voltage operation.

液晶ディスプレイにはその目的に応じて様々−な動作方
式があるが、アクティブマトリクス方式はフルカラーの
動画表示を高解像度で行なうことが可能であることが特
徴である。アクティブマトリクス方式はマトリクス状に
配置した電極の交点を一画素とし、その一画素ごとにス
イッチング素子を設ける方式である。アクティブマトリ
クス方式は非線形ダイオード型と薄膜トランジスタ(T
PT)型に分類できるが、このうち特に後者の研究・開
発が活発に行われている。TPTとコンデンサのアレイ
をガラス板に配設したものを一方の基板とするものは、
例えばアイイーイーイー・トランザクション・オン・エ
レクトロン・デバイス(IEEE Trans、 on
 Electron Devlces−)第20巻の第
995頁乃至第toot頁(1973年)に詳細に記載
さ  −れている。
There are various operating systems for liquid crystal displays depending on their purpose, but the active matrix system is characterized by its ability to display full-color moving images at high resolution. The active matrix method is a method in which each pixel is an intersection of electrodes arranged in a matrix, and a switching element is provided for each pixel. The active matrix method uses nonlinear diode type and thin film transistor (T
(PT) type, of which the latter is particularly actively researched and developed. One substrate has an array of TPT and capacitors arranged on a glass plate.
For example, IEEE Trans on Electron Devices (IEEE Trans, on
It is described in detail in Electron Devices, Vol. 20, pages 995 to 20 (1973).

第6図はTPTを使用したTFTアレイ基板の概略平面
図であり、TPTは等価回路で示している。第6図にお
いて、硝子基板仕には、はぼ平行に等間隔で配設された
信号電極線2と、この信号電極線2とほぼ直交し且つ酸
化硅素等の層間絶縁膜で信号電極線2と電気的に絶縁さ
れた走査電極線3と、信号電極線2と走査電極線3との
交点付近に配置され全体としてマトリクス状になった表
示画素部4から構成される装置 第7図はこの表示画素部4の一例を示す断面図である。
FIG. 6 is a schematic plan view of a TFT array substrate using TPT, and TPT is shown as an equivalent circuit. In FIG. 6, the glass substrate has signal electrode lines 2 arranged substantially parallel to each other at equal intervals, and signal electrode lines 2 that are substantially orthogonal to the signal electrode lines 2 and are formed using an interlayer insulating film such as silicon oxide. FIG. 7 shows a device consisting of a scanning electrode line 3 electrically insulated from the signal electrode line 2 and a display pixel section 4 arranged in the vicinity of the intersection of the signal electrode line 2 and the scanning electrode line 3 and having a matrix shape as a whole. 3 is a cross-sectional view showing an example of a display pixel section 4. FIG.

第7図において、硝子基板10上に、ゲ4電極1l、ゲ
ート絶縁膜12、半導体膜13、半導体保護膜14、低
低抵抗半一体膜5−、ソース電極16及びドレイン電極
l7から構成されるTPTは、ソース電極16の部分で
画素電極18に接続されている。ここで、ゲート電極1
lは第6図における走査電極線3と一体であり、ドレイ
ン電極17は′Mフ図における信号電極線2と一体であ
る。そして、TPTを保護するため、この上部を酸化硅
素等の絶縁膜l9で覆うとともに、更に、この上に配向
膜20を形成している。一方、硝子基板10上には、T
PTと対向するように遮光膜22が形成されており、更
に、対向電極23及び配向膜24が順次形成されている
。そして、2つの硝子基板10.21の間には液晶25
が挟持されている。
In FIG. 7, on a glass substrate 10, there is formed a gate 4 electrode 1l, a gate insulating film 12, a semiconductor film 13, a semiconductor protective film 14, a low-resistance semi-integral film 5-, a source electrode 16, and a drain electrode 17. TPT is connected to the pixel electrode 18 at the source electrode 16 portion. Here, gate electrode 1
1 is integrated with the scanning electrode line 3 in FIG. 6, and the drain electrode 17 is integrated with the signal electrode line 2 in FIG. In order to protect the TPT, its upper part is covered with an insulating film 19 made of silicon oxide or the like, and an alignment film 20 is further formed on this. On the other hand, on the glass substrate 10, T
A light shielding film 22 is formed to face the PT, and furthermore, a counter electrode 23 and an alignment film 24 are formed in this order. A liquid crystal 25 is placed between the two glass substrates 10 and 21.
is being held.

第7図に示したTFTアレイ基板を製作する工程は次の
通りである。まず、硝子基板10上に第6図における走
査電極線3及びゲート電極l1を同時に形成し、この上
にゲート絶縁膜12、半導体膜13、及び半導体保護膜
14を順次成膜する。
The steps for manufacturing the TFT array substrate shown in FIG. 7 are as follows. First, the scanning electrode line 3 and the gate electrode l1 shown in FIG. 6 are simultaneously formed on the glass substrate 10, and the gate insulating film 12, the semiconductor film 13, and the semiconductor protective film 14 are sequentially formed thereon.

次に、半導体保護膜14を成形した後、低抵抗半一体膜
15を成膜し、半導体膜l3と低抵抗半導体膜15を同
時に同一形状に成形する。その後、画素電極18の形成
及び電極パッド上のゲート絶縁膜12の除去を行い、第
6図における信号電極線2、ソース電極16及びドレイ
ン電極17を形成する。続いてこの状態では、ソース電
極16とドレイン電極17が低抵抗半導体膜15により
短絡しているので、例えば特開昭60−428611号
公報に記載されているように、ソース電極16とドレイ
ン電極17をマスクにして、半導体保護膜l4上の低抵
抗半導体膜15を除去する。そして、硝子基板10上に
絶縁膜19と配向膜2Gを順次形成することにより、T
FTアレイ基板が完成する。
Next, after forming the semiconductor protective film 14, a low resistance semi-integral film 15 is formed, and the semiconductor film 13 and the low resistance semiconductor film 15 are simultaneously formed into the same shape. Thereafter, the pixel electrode 18 is formed and the gate insulating film 12 on the electrode pad is removed, and the signal electrode line 2, source electrode 16, and drain electrode 17 shown in FIG. 6 are formed. Subsequently, in this state, since the source electrode 16 and the drain electrode 17 are short-circuited by the low-resistance semiconductor film 15, the source electrode 16 and the drain electrode 17 are short-circuited by the low-resistance semiconductor film 15. Using as a mask, the low resistance semiconductor film 15 on the semiconductor protective film l4 is removed. Then, by sequentially forming an insulating film 19 and an alignment film 2G on the glass substrate 10, T
The FT array board is completed.

(発明が解決しようとする課題) しかしながら、この種の液晶表示素子において、画素電
極18とドレイン電極17及び信号電極線2とは同一平
面内に近接して形成されるために、画素電極18とドレ
イン電極17及び信号電極線2とが短絡し、欠陥画素が
発生することがあった。このため、画素電極l8とドレ
イン電極17及び信号電極線2との間隔を大きくとる必
要が生じ、開口率が低下することがあつた。
(Problem to be Solved by the Invention) However, in this type of liquid crystal display element, the pixel electrode 18, the drain electrode 17, and the signal electrode line 2 are formed close to each other in the same plane. In some cases, the drain electrode 17 and the signal electrode line 2 were short-circuited, resulting in defective pixels. Therefore, it became necessary to increase the distance between the pixel electrode 18, the drain electrode 17, and the signal electrode line 2, and the aperture ratio sometimes decreased.

この発明は、このような従来の事情に鑑みてなされたも
のである。
This invention was made in view of such conventional circumstances.

[発明の構成] (課題を解決するための手段) この発明は、第1基板上にゲート電極、ゲート絶縁膜、
半導体膜、ソース電極及びドレイン電極から構成される
薄膜トランジスタを複数本の走査電極線と信号電極線の
交点付近に配置してマトリクス状にし且つ各々の薄膜ト
ランジスタに画素電極を接続してなるアレイ基板と、第
2基板上に対向電極を形成してなる対向基板との間に液
晶を挟持してなるアクティブマトリクス型液晶表示素子
の製造方法についてのものである。そして、この発明は
、第1基板上に透明導電膜を成膜した後、走査電極線と
半導体膜をマスクとした背面露光法を用いて、透明導電
膜をパターニングすることにより、画素電極を形成する
工程を備えている。また、この発明は、上述の工程に代
えて、第1基板上に先遮蔽膜を成膜した後にパターニン
グしてブラックマトリックスを形成する工程と、第1基
板上に透明導電膜を成膜した後、走査電極線とブラック
マトリックスをマスクとした背面露光法を用いて、透明
導電膜をパターニングすることにより、画素電極を形成
する工程を備えている。
[Structure of the Invention] (Means for Solving the Problems) This invention provides a gate electrode, a gate insulating film, a gate insulating film, and a gate electrode on a first substrate.
an array substrate in which thin film transistors each consisting of a semiconductor film, a source electrode, and a drain electrode are arranged in a matrix near the intersections of a plurality of scanning electrode lines and signal electrode lines, and each thin film transistor is connected to a pixel electrode; This invention relates to a method for manufacturing an active matrix liquid crystal display element in which a liquid crystal is sandwiched between a second substrate and a counter substrate formed with a counter electrode formed thereon. This invention forms pixel electrodes by forming a transparent conductive film on a first substrate and then patterning the transparent conductive film using a back exposure method using a scanning electrode line and a semiconductor film as a mask. It has a process to In addition, in place of the above steps, the present invention includes a step of first forming a shielding film on the first substrate and then patterning to form a black matrix, and a step of forming a black matrix after forming a transparent conductive film on the first substrate. , a process of forming pixel electrodes by patterning a transparent conductive film using a back exposure method using scanning electrode lines and a black matrix as a mask.

(作 用) この発明では、透明導電膜から画素電極を背面露光によ
り形成することで、金属粉に代表されるような光が透過
しない異物上の透明導電膜は除去されるため、画素電極
とドレイン電極及び信号電極線との短絡が減少し、点欠
陥を低減できる。
(Function) In this invention, by forming the pixel electrode from the transparent conductive film by back exposure, the transparent conductive film on the foreign matter through which light does not pass, such as metal powder, is removed. Short circuits between the drain electrode and the signal electrode line are reduced, and point defects can be reduced.

また、信号電極線と画素電極が近接して形成されるため
、開口率が大きくなり、透過率が高い表示素子を形成す
ることができる。
Furthermore, since the signal electrode line and the pixel electrode are formed close to each other, the aperture ratio is increased and a display element with high transmittance can be formed.

(実施例) 以下、図面を参照してこの発明を詳細に説明する。(Example) Hereinafter, the present invention will be explained in detail with reference to the drawings.

第1図は第1の発明の一実施例によって得られるアクテ
ィブマトリクス型液晶表示素子を示す断面図を表してお
り、これを製造工程上従って説明する。第1図において
、まず、例えば硝子からなる第1基板30の一生面上に
、例えばモリブデン・タンタル(Mo−Ta)合金膜を
スパッタ法等により厚さ約0.2μmに成膜し、ホトリ
ソグラフィ一法によりストライブ状の走査電極線(図示
せず)と、この走査電極線に電気的に接続しているゲー
ト電極31を成形する。次に、プラズマCvD (Ch
emical Vapor Deposltioo )
法等により、例えば厚さ約0.3μmの窒化硅素(S 
i Nx )膜、例えば厚さ約(L1μmの非晶質硅素
(a−Si)膜及び厚さ約0.3μmのSiNx膜を、
順次連続して堆積し、最下部のSiNx膜からなるゲー
ト絶縁膜32を得るとともに、ホトリソグラフィ一法に
より最上部のSiNxflkに加工を施し、ゲート電極
31に対応した部分より内側に半導体保護膜33を島状
に成形する。続いて、プラズマCVD法により厚さ約0
,05μmのn 型のa−Si膜を成膜し、ホトリソグ
ラフィ一法により半導体膜34と低抵抗半導体膜35を
同時に成形する。
FIG. 1 shows a cross-sectional view of an active matrix liquid crystal display element obtained according to an embodiment of the first invention, and the manufacturing process will be explained accordingly. In FIG. 1, first, for example, a molybdenum-tantalum (Mo-Ta) alloy film is formed to a thickness of about 0.2 μm by sputtering or the like on the whole surface of a first substrate 30 made of glass, and then photolithography is performed. A striped scanning electrode line (not shown) and a gate electrode 31 electrically connected to the scanning electrode line are formed by one method. Next, plasma CvD (Ch
chemical vapor deposition)
For example, silicon nitride (S) with a thickness of about 0.3 μm is
i Nx ) films, for example, an amorphous silicon (a-Si) film with a thickness of about (L1 μm) and a SiNx film with a thickness of about 0.3 μm,
The gate insulating film 32 made of the SiNx film at the bottom is obtained by sequentially depositing the SiNx film at the bottom, and the SiNx flk at the top is processed by a photolithography method to form a semiconductor protective film 33 on the inner side of the part corresponding to the gate electrode 31. Form into an island shape. Next, the plasma CVD method is used to reduce the thickness to about 0.
, 05 μm, and a semiconductor film 34 and a low-resistance semiconductor film 35 are simultaneously formed by photolithography.

第2図はこの実施例における走査電極線36と半導体膜
34のパターンを示す概略平面図である。
FIG. 2 is a schematic plan view showing the pattern of the scanning electrode line 36 and the semiconductor film 34 in this embodiment.

同図かられかるように、半導体膜34と低抵抗半導体膜
35の積層膜は第7図における信号電極線2に類似した
形状を有しており、走査電極線3Bとの間で所定の升目
を形造っている。
As can be seen from the figure, the laminated film of the semiconductor film 34 and the low-resistance semiconductor film 35 has a shape similar to the signal electrode line 2 in FIG. is forming.

次に、第1基板30の一生面上に例えばITO(Ind
ium Tin Oxide)からなる透明導電膜をス
パッタ法で約0.1amの厚さに堆積し、ホトリソグラ
フィ一法により画素電極37を成形する。ここで、画素
電極37を成形する際には、例えばネガ型のホトレジス
トを塗布し、第1基板30の他主面側から露光・現像を
行う。こうすることにより、走査電極1136と半導体
膜34により形成されている升目の内側にレジストパタ
ーンが形成され、透明導電膜をエッチングすると、升目
の内側に画素電極37が形成される。
Next, for example, ITO (Ind.
A transparent conductive film made of (Ium Tin Oxide) is deposited to a thickness of about 0.1 am by sputtering, and a pixel electrode 37 is formed by photolithography. Here, when forming the pixel electrode 37, for example, a negative type photoresist is applied, and exposure and development are performed from the other main surface side of the first substrate 30. By doing this, a resist pattern is formed inside the square formed by the scanning electrode 1136 and the semiconductor film 34, and when the transparent conductive film is etched, the pixel electrode 37 is formed inside the square.

次に、例えば厚さ約0.05μmのモリブデン(Mo)
膜と厚さ約1.0μmのアルミニウム(Al)膜をスパ
ッタ法等で堆積し、ホトリソグラフィ一法によりストラ
イプ状の信号電極線(図示せず)、この信号電極線に電
気的接続しているドレイン電極38、及びソース電極3
9を同時に形成する。このとき、信号電極線とドレイン
電極38は、半導体膜34と低抵抗半導体膜35の積層
膜のパターン上内側に形成するのに対し、ソース電極3
9は画素電極37と電気的に接続するように形成される
。また、この状態では、ドレイン電極38とソース電極
39の間が低抵抗半導体膜35により短絡してしまうの
で、この部分の低抵抗半導体膜35をエッチングにより
除去する。こうして、T51基板30上にゲート電極3
1、ゲート絶縁膜32、半導体膜34ドレイン電極38
及びソース電極39から構成されるTFT40が得られ
、図示はしないが、TFT40はそれぞれ複数本の走査
電極線36と信号電極線の交点付近に位置し、全体とし
てマトリクス状に配置されている。続いて、例えば窒化
硅素からなる膜を第1基板30の一生面上に約0.1μ
mから約1−0μmの厚さで堆積し、ホトリソグラフィ
一法にて、絶縁膜41を所望のパターンに形成する。そ
してこの後、第1基板30の一生面上に、例えばポリイ
ミドからなる配向膜42を例えばスピナコート法等によ
り塗布し、約100℃から約200℃の間の適当な温度
で焼成してからラビングを行う。こうして、所望のアレ
イ基板43が得られる。
Next, make molybdenum (Mo) with a thickness of about 0.05 μm, for example.
An aluminum (Al) film with a thickness of about 1.0 μm is deposited by sputtering or the like, and a striped signal electrode line (not shown) is electrically connected to the signal electrode line by photolithography. Drain electrode 38 and source electrode 3
9 is formed at the same time. At this time, the signal electrode line and the drain electrode 38 are formed on the inner side of the pattern of the laminated film of the semiconductor film 34 and the low-resistance semiconductor film 35, while the source electrode
9 is formed to be electrically connected to the pixel electrode 37. Furthermore, in this state, a short circuit occurs between the drain electrode 38 and the source electrode 39 due to the low resistance semiconductor film 35, so this portion of the low resistance semiconductor film 35 is removed by etching. In this way, the gate electrode 3 is placed on the T51 substrate 30.
1. Gate insulating film 32, semiconductor film 34, drain electrode 38
Although not shown, the TFTs 40 are respectively located near the intersections of the plurality of scanning electrode lines 36 and the signal electrode lines, and are arranged in a matrix as a whole. Subsequently, a film made of silicon nitride, for example, is deposited on the whole surface of the first substrate 30 in a thickness of about 0.1 μm.
The insulating film 41 is deposited to a thickness of approximately 1-0 μm from m to a desired pattern using photolithography. Thereafter, an alignment film 42 made of polyimide, for example, is coated on the entire surface of the first substrate 30 by, for example, a spinner coating method, baked at an appropriate temperature between about 100° C. and about 200° C., and then rubbed. I do. In this way, a desired array substrate 43 is obtained.

一方、第2基板44の一生面上には、アレイ基板43の
TFT40と対向させる位置に、例えばAIからなる遮
光膜45を形成し、更に、例えばITOからなる対向電
極46を形成する。そしてこの後は前と同様に、第2基
板44の一生面上に、例えばポリイミドからなる配向1
4147を例えばスピナコート法などにより塗布し、約
100℃から約200℃の間の適当な温度で焼成してか
らラビングを行う。こうして、所望の対向基板48が得
られる。次に、アレイ基板43と対向基板48を、スペ
ーサ(図示せず)である例えば約IOμmのアルミナの
ビーズを介して、配向膜42,47が対向した状態で一
体となるように、液晶の注入口となる部分を除いて、例
えばエポキシ系の接着剤からなる封着材(図示せず)で
ほぼlOμm II tて概略平行に貼り合わせる。次
に、前述の注入口より液晶49を注入した後、例えばエ
ポキシ系の接着剤からなる封止材(図示せず)で注入口
を封止する。
On the other hand, on the entire surface of the second substrate 44, a light shielding film 45 made of, for example, AI is formed at a position facing the TFT 40 of the array substrate 43, and a counter electrode 46 made of, for example, ITO is further formed. After this, as before, an alignment layer made of polyimide, for example, is placed on the entire surface of the second substrate 44.
4147 is applied by, for example, a spinner coating method, baked at an appropriate temperature between about 100° C. and about 200° C., and then rubbed. In this way, the desired counter substrate 48 is obtained. Next, the array substrate 43 and the counter substrate 48 are placed together with a spacer (not shown), for example, alumina beads of about IO μm, so that the alignment films 42 and 47 face each other. Except for the portion that will become the entrance, they are bonded together in approximately parallel to each other with a sealing material (not shown) made of, for example, an epoxy adhesive at a thickness of approximately 10 μm. Next, after the liquid crystal 49 is injected through the injection port described above, the injection port is sealed with a sealant (not shown) made of, for example, an epoxy adhesive.

こうして、アレイ基板43と対向基板48との間に液晶
49を挟持してなる所望のアクティブマトリクス型液晶
表示素子が得られる。
In this way, a desired active matrix type liquid crystal display element in which the liquid crystal 49 is sandwiched between the array substrate 43 and the counter substrate 48 is obtained.

この実施例では、第1基板30の一生面上に透明導電膜
を成膜した後、走査電極線36と半導体膜34をマスク
とした背面露光法を用いて、上述の透明導電膜をパター
ニングすることにより、画素電極37を形成している。
In this embodiment, after forming a transparent conductive film on the entire surface of the first substrate 30, the transparent conductive film described above is patterned using a back exposure method using the scanning electrode line 36 and the semiconductor film 34 as a mask. As a result, a pixel electrode 37 is formed.

この結果、画素電極37を形成する以前に例えば金属粉
のような異物が第1基板30に付着していた場合、この
異物上では透明導電膜が除去されるため、画素電極37
とドレイン電極38及び信号電極線との短絡が減少する
。また、信号電極線に極めて近接した形で画素電極37
を形成することが可能となり、表示素子の開口率が従来
に比べ向上する。
As a result, if foreign matter such as metal powder is attached to the first substrate 30 before forming the pixel electrode 37, the transparent conductive film is removed on the foreign matter, so that the pixel electrode 37
Short circuits between the drain electrode 38 and the signal electrode line are reduced. In addition, the pixel electrode 37 is placed very close to the signal electrode line.
The aperture ratio of the display element is improved compared to the conventional one.

第3図は第2の発明の一実施例によって得られるアクテ
ィブマトリクス型液晶表示素子を示す断面図を表してお
り、これを製造工程に従って説明する。第3図において
、まず、例えば硝子からなる第1基板30の一生面上に
、例えばクロム(C「)からなる光遮蔽膜をスパッタ法
等により厚さ約0.15μmに成膜し、ホトリソグラフ
ィ一法により格子状のブラックマトリクス50を成形す
る。
FIG. 3 shows a cross-sectional view of an active matrix liquid crystal display element obtained according to an embodiment of the second invention, and this will be explained according to the manufacturing process. In FIG. 3, first, a light shielding film made of, for example, chromium (C'') is formed to a thickness of about 0.15 μm by sputtering or the like on the entire surface of a first substrate 30 made of, for example, glass, and then photolithography is performed. A grid-like black matrix 50 is formed by one method.

続いて、全面に例えばプラズマCVD法等【巳より、例
えば厚さ約(12μmのSiOxからなる絶縁層51を
形成する。次に、例えばM o −T a合金膜をスパ
ッタ法等により厚さ約0.2μmに成膜し、ホトリソグ
ラフィ一法によりストライブ状の走査電極線(図示せず
)と、この走査電極線に電気的に接続しているゲート電
極31を成形する。
Next, an insulating layer 51 made of SiOx with a thickness of about 12 μm is formed on the entire surface by, for example, a plasma CVD method or the like. Next, an insulating layer 51 made of SiOx is formed to a thickness of about 12 μm by a sputtering method or the like. A film is formed to a thickness of 0.2 μm, and a striped scanning electrode line (not shown) and a gate electrode 31 electrically connected to the scanning electrode line are formed by photolithography.

第4図はこの実施例における走査電極線36とブラック
マトリクス50のパターンを示す概略平面図である。同
図かられかるように、ブラックマトリクス50は第7図
における信号電極線2に類似した形状を有しており、走
査電極線36との間で所定の升目を形造っている。
FIG. 4 is a schematic plan view showing the pattern of the scanning electrode lines 36 and the black matrix 50 in this embodiment. As can be seen from the figure, the black matrix 50 has a shape similar to the signal electrode line 2 in FIG. 7, and forms a predetermined square with the scanning electrode line 36.

次に、プラズマCVD法等により、例えば厚さ約0,3
μmのSiOx膜、例えば厚さ約0.1μmのa−Si
膜及び厚さ約L3pmのSiNx膜を、順次連続して堆
積し、最下部のSiOx膜からなるゲート絶縁膜32を
得るとともに、ホトリソグラフィ一法により最上部のS
iNx膜に加工を施し、ゲート電極31に対応した部分
より内側に半導体保護膜33を島状に成形する。続いて
、プラズマCVD法により厚さ約0.05μmのn 型
のa−Si膜を成膜し、ホトリソグラフィ一法により半
導体膜34と低抵抗半導体膜35を同時に成形する。次
に、第1基板30の一生面上に例えばI To (In
dfus Tin Oxide)からなる透明導電膜を
スパッタ法で約0.111mの厚さに堆積し、ホトリソ
グラフィ一法により画素電極37を成形する。
Next, by plasma CVD method or the like, a thickness of about 0.3 mm is formed, for example.
μm SiOx film, e.g. a-Si with a thickness of about 0.1 μm
A SiNx film with a thickness of about L3 pm is sequentially deposited to obtain a gate insulating film 32 consisting of the SiOx film at the bottom, and a SiNx film at the top by photolithography.
The iNx film is processed to form a semiconductor protective film 33 into an island shape inside a portion corresponding to the gate electrode 31. Subsequently, an n-type a-Si film having a thickness of about 0.05 μm is formed by plasma CVD, and a semiconductor film 34 and a low-resistance semiconductor film 35 are simultaneously formed by photolithography. Next, for example, I To (In
A transparent conductive film made of (dfus tin oxide) is deposited to a thickness of about 0.111 m by sputtering, and a pixel electrode 37 is formed by photolithography.

ここで、画素電極3丁を成形する際には、例えばネガ型
のホトレジストを塗布し、第1基板30の他主面側から
露光・現像を行う。こうすることにより、走査電極線3
6とブラックマトリクス50により形成されている升目
の内側のみにレジストパターンが形成され、透明導電膜
をエッチングすると、升目の内側に画素電極37が形成
される。
Here, when molding the three pixel electrodes, for example, a negative type photoresist is applied, and exposure and development are performed from the other main surface side of the first substrate 30. By doing this, the scanning electrode line 3
A resist pattern is formed only on the inside of the square formed by 6 and the black matrix 50, and when the transparent conductive film is etched, the pixel electrode 37 is formed inside the square.

これ以降は第1図に示した実施例と同様な工程を行うこ
とにより、所望のアクティブマトリクス型液晶表示素子
が得られる。
Thereafter, by performing the same steps as in the embodiment shown in FIG. 1, a desired active matrix liquid crystal display element can be obtained.

この実施例では、第1基板30上に光遮蔽膜を成膜した
後にパターニングしてブラックマトリクス50を形成す
るとともに、第1基板3G上に透明導電膜を成膜した後
、走査電極線36とブラックマトリクス50をマスクと
した背面露光法を用いて、透明導電膜をパターニングす
ることにより、画素電極37を形成している。この結果
、この実施例は、第1図に示した実施例と同様の効果を
有している。特に、この実施例では、ブラックマトリク
ス50が光遮蔽膜から構成されるため、半導体1113
4を利用する第1図に示した実施例に比べて上述の効果
が顕著である。
In this embodiment, a light shielding film is formed on the first substrate 30 and then patterned to form the black matrix 50, and a transparent conductive film is formed on the first substrate 3G, and then the scanning electrode lines 36 and The pixel electrode 37 is formed by patterning the transparent conductive film using a back exposure method using the black matrix 50 as a mask. As a result, this embodiment has the same effects as the embodiment shown in FIG. In particular, in this embodiment, since the black matrix 50 is composed of a light shielding film, the semiconductor 1113
The above-mentioned effect is more remarkable than the embodiment shown in FIG.

第5図は第2の発明の他の実施例によって得られるアク
ティブマトリクス型液晶表示素子を示す断面図を表して
おり、これを製造工程に従って説明する。第5図におい
て、まず、例えば硝子からなる第1基板30の一生面上
に、例えばCrからなる光遮蔽膜をスパッタ法等により
厚さ約0.15μmに成膜し、ホトリソグラフィ一法に
より格子状のブラックマトリクス50を成形する。続い
て、全面に例えばプラズマCVD法等により、例えば厚
さ約0.2μmのSiOxからなる絶縁層51を形成す
る。次に、例えばM o −T a合金膜をスパッタ法
等により厚さ約0.2μmに成膜し、ホトリソグラフィ
一法によりストライブ状の走査電極線(図示せず)と、
この走査電極線に電気的に接続しているゲート電極31
を成形する。ここで、走査電極線とブラックマトリクス
50のパターンの位置関係は、第4図の場合と同様であ
る。
FIG. 5 shows a cross-sectional view of an active matrix liquid crystal display element obtained according to another embodiment of the second invention, and this will be explained according to the manufacturing process. In FIG. 5, first, a light shielding film made of, for example, Cr is formed to a thickness of about 0.15 μm on the entire surface of a first substrate 30 made of, for example, glass, by sputtering, and then a grid is formed by photolithography. A black matrix 50 having a shape is formed. Subsequently, an insulating layer 51 made of SiOx and having a thickness of approximately 0.2 μm is formed over the entire surface by, for example, plasma CVD. Next, for example, a Mo-Ta alloy film is formed to a thickness of about 0.2 μm by sputtering or the like, and striped scanning electrode lines (not shown) are formed by photolithography.
Gate electrode 31 electrically connected to this scanning electrode line
to form. Here, the positional relationship between the scanning electrode lines and the pattern of the black matrix 50 is the same as in the case of FIG. 4.

続いて、第1基板30の一生面上の全面に、例えばプラ
ズマCVD法等により厚さ約0.2μmのSiOxから
なる−層目のゲート絶縁膜32aを形成する。次に、第
1基板30の一生面上に例えばITOからなる透明導電
膜をスパッタ法で約0.1 μmの厚さに堆積し、ホト
リソグラフィ一法により画素電極37を成形する。ここ
で、画素電極37を成形する際には、例えばネガ型のホ
トレジストを塗布し、第1基板30の他主面側から露光
・現像を行う。こうすることにより、走査電極!136
とブラックマトリクス50により形成されている升目の
内側のみにレジストパターンが形成され、透明導電膜を
エッチングすると、升目の内側に画素電極37が形成さ
れる。次に、第1基板30の一生面上の全面に、例えば
プラズマCVD法等により厚さ約0.2μmのSiOx
からなる二層目のゲート絶縁膜32bを形成する。
Subsequently, a -th layer gate insulating film 32a made of SiOx and having a thickness of approximately 0.2 μm is formed on the entire surface of the first substrate 30 by, for example, plasma CVD. Next, a transparent conductive film made of, for example, ITO is deposited on the whole surface of the first substrate 30 to a thickness of about 0.1 μm by sputtering, and a pixel electrode 37 is formed by photolithography. Here, when forming the pixel electrode 37, for example, a negative type photoresist is applied, and exposure and development are performed from the other main surface side of the first substrate 30. By doing this, the scanning electrode! 136
A resist pattern is formed only inside the square formed by the black matrix 50, and when the transparent conductive film is etched, the pixel electrode 37 is formed inside the square. Next, SiOx with a thickness of about 0.2 μm is deposited on the entire surface of the first substrate 30 by, for example, plasma CVD.
A second layer gate insulating film 32b is formed.

次に、プラズマCVD法等により、例えば厚さ約0.0
5μmのa−Si膜及び厚さ約0.2μmのSiNx膜
を順次連続して堆積し、ホトリソグラフィ一法により最
上部のSiNx膜に加工を施し、ゲート電極31に対応
した部分より内側に半導体保護膜33を島状に成形する
。続いて、プラズマCVD法により厚さ約0.05μm
のn 型のa−Si膜を成膜し、ホトリソグラフィ一法
により半導体膜34と低抵抗半導体膜35を同時に成形
する。次に、ゲート絶縁膜32b1半導体膜34及び低
抵抗半導体膜35のIa層膜の所定部分に、画素電極3
7とソース電極39を電気的に接続させるためのコンタ
クトホールをホトリソグラフィ一法により形成する。続
いて、例えば厚さ約0.05μmのモリブデン(M o
 )膜と厚さ約1.0μmのアルミニウム(AI)膜を
スパッタ法等で堆積し、ホトリソグラフィ一法によりス
トライブ状の信号電極線(図示せず)、この信号電極線
に電気的接続しているドレイン電極38、及びソース電
極39を同時に形成する。このとき、信号電極線とドレ
イン電極38は、ブラックマトリクス50のパターン上
内側に形成するのに対し、ソース電極39は上述したコ
ンタクトホールを介して画素電極37と電気的に接続す
るように形成される。また、この状態では、ドレイン電
極38とソース電極39の間が低抵抗半導体膜35によ
り短絡してしまうので、この部分の低抵抗半導体膜35
をエッチングにより除去する。こうして、第1基板30
上にゲート電極31、ゲート絶縁膜32、半導体膜34
、ドレイン電極38及びソース電極39から構成される
TFT40が得られる。これ以降は第1図に示した実施
例と同様な工程を行うことにより、所望のアクティブマ
トリクス型液晶表示素子が得られる。
Next, by plasma CVD method etc., a thickness of about 0.0, for example, is formed.
A 5 μm a-Si film and an approximately 0.2 μm thick SiNx film are successively deposited, and the uppermost SiNx film is processed by photolithography to form a semiconductor layer inside the portion corresponding to the gate electrode 31. The protective film 33 is formed into an island shape. Subsequently, the thickness was approximately 0.05 μm by plasma CVD method.
An n-type a-Si film is formed, and a semiconductor film 34 and a low-resistance semiconductor film 35 are simultaneously formed by photolithography. Next, the pixel electrode 3
A contact hole for electrically connecting 7 and source electrode 39 is formed by photolithography. Subsequently, molybdenum (Mo
) film and an aluminum (AI) film with a thickness of approximately 1.0 μm are deposited by sputtering or the like, and a striped signal electrode wire (not shown) is electrically connected to the signal electrode wire by photolithography. A drain electrode 38 and a source electrode 39 are formed at the same time. At this time, the signal electrode line and the drain electrode 38 are formed on the inner side of the pattern of the black matrix 50, while the source electrode 39 is formed so as to be electrically connected to the pixel electrode 37 through the above-mentioned contact hole. Ru. Furthermore, in this state, a short circuit occurs between the drain electrode 38 and the source electrode 39 due to the low resistance semiconductor film 35.
is removed by etching. In this way, the first substrate 30
A gate electrode 31, a gate insulating film 32, and a semiconductor film 34 are formed on the top.
, a TFT 40 composed of a drain electrode 38 and a source electrode 39 is obtained. Thereafter, by performing the same steps as in the embodiment shown in FIG. 1, a desired active matrix liquid crystal display element can be obtained.

この実施例では、第3図に示した実施例と同様に、T5
1基板30上に光遮蔽膜を成膜した後にパターニングし
てブラックマトリクス50を形成するとともに、第1基
板3G上に透明導電膜を成膜した後、走査電極線36と
ブラックマトリクス50をマスクとした背面露光法を用
いて、透明導電膜をパターニングすることにより、画素
電極37を形成している。この結果、この実施例は、今
まで述べた実施例と同様の効果を有している。
In this embodiment, as in the embodiment shown in FIG.
After forming a light shielding film on the first substrate 30, patterning is performed to form a black matrix 50, and after forming a transparent conductive film on the first substrate 3G, the scanning electrode line 36 and the black matrix 50 are used as a mask. The pixel electrode 37 is formed by patterning the transparent conductive film using the back exposure method. As a result, this embodiment has the same effects as the embodiments described so far.

そして特に、この実施例では、画素電極37とドレイン
電極38の間にゲート絶縁膜32bを介在させることに
より、異物による画素電極37とドレイン電極38及び
信号電極線との短絡を皆無とすることができた。
In particular, in this embodiment, by interposing the gate insulating film 32b between the pixel electrode 37 and the drain electrode 38, it is possible to completely eliminate short circuits between the pixel electrode 37 and the drain electrode 38 and the signal electrode line due to foreign matter. did it.

なお、第1図に示した実施例において、背面露光法を用
いる際の半導体膜34と低抵抗半導体膜35の積層膜の
遮光性を向上させる必要があるときには、低抵抗半導体
膜35上に所定の金属膜例えば厚さ約0.1μmのMO
膜を積層した後、画素電極37の形成を行えばよい。
In the embodiment shown in FIG. 1, when it is necessary to improve the light-shielding property of the laminated film of the semiconductor film 34 and the low-resistance semiconductor film 35 when using the back exposure method, a predetermined layer is formed on the low-resistance semiconductor film 35. For example, MO with a thickness of about 0.1 μm.
After laminating the films, the pixel electrode 37 may be formed.

[発明の効果] この発明は、走査電極線と半導体膜或いはブラックマト
リクスとをマスクとした背面露光法を利用して画素電極
を形成することにより、信号電極線と画素電極を近接し
て形成できるため、開口率が大きく透過率の高いアクテ
ィブマトリクス型液晶表示素子を歩留りよく製造するこ
とが可能である。
[Effects of the Invention] This invention allows the signal electrode line and the pixel electrode to be formed close to each other by forming the pixel electrode using a back exposure method using the scanning electrode line and the semiconductor film or black matrix as a mask. Therefore, it is possible to manufacture an active matrix liquid crystal display element with a large aperture ratio and high transmittance with a high yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は第1の発明の一実施例によって得られるアクテ
ィブマトリクス型液晶表示素子を示す断面図、第2図は
第1図に示した実施例における走査電極線と半導体膜の
パターンを示す概略平面図、第3図は第2の発明の一実
施例によって得られるアクティブマトリクス型液晶表示
素子を示す断面図、第4図は第3図に示した実施例にお
ける走査電極線とブラックマトリクスのパターンを示す
概略平面図、第5図は第2の発明の他の実施例によって
得られるアクティブマトリクス型液晶表示素子を示す断
面図、第6図は従来のTFTアレイ基板の概略平面図、
第7図は従来のアクティブマトリクス型液晶表示素子の
表示画素部の一例を示す断面図である。 30・−・第1基板、    31・−・ゲート電極3
2.32a、32b−・・ゲート絶縁膜34・・・半導
体膜 36・・−走査電極線、   3フー・画素電極38・
・・ドレイン電極、   39−・−ソース電極40・
−・TFT、      43−・・アレイ基板46・
・−対向電極、    48・・・対向基板49・・一
液晶、     5G−・・ブラックマトリクス代理人
 弁理士 則 近 憲 佑 同    竹 花 喜久男 岨対緘艮阪 452先膜 44藁2XKt)   46j拘を徹l 
 / 34斗喜本腰 バ\、 −′Tt  廿 仔 45 7.4  46  48 1/    t/− 3531SOiフー/771−37.t51#q第  
3 図 45 44     7.6 2{′!う電ぷi漿 1 11+11 1I+−砧魂
FIG. 1 is a cross-sectional view showing an active matrix liquid crystal display element obtained by an embodiment of the first invention, and FIG. 2 is a schematic diagram showing the pattern of scanning electrode lines and semiconductor films in the embodiment shown in FIG. A plan view, FIG. 3 is a sectional view showing an active matrix liquid crystal display element obtained by an embodiment of the second invention, and FIG. 4 is a pattern of scanning electrode lines and a black matrix in the embodiment shown in FIG. 3. 5 is a cross-sectional view showing an active matrix liquid crystal display element obtained by another embodiment of the second invention, FIG. 6 is a schematic plan view of a conventional TFT array substrate,
FIG. 7 is a cross-sectional view showing an example of a display pixel portion of a conventional active matrix liquid crystal display element. 30.--First substrate, 31.--Gate electrode 3
2.32a, 32b--gate insulating film 34...semiconductor film 36--scanning electrode line, 3-pixel electrode 38-
・・Drain electrode, 39−・−Source electrode 40・
-・TFT, 43-・array board 46・
・-Counter electrode, 48...Counter substrate 49...1 liquid crystal, 5G-...Black matrix agent Patent attorney Nori Chika Ken Yudo Takehana Kikuoaki vs. Isaka 452 first film 44 straw 2XKt) 46j Toru l
/ 34 Douki Honkoshiba\, -'Tt 廿子45 7.4 46 48 1/ t/- 3531SOi Fu/771-37. t51#qth
3 Figure 45 44 7.6 2{'! Udenpui 1 11+11 1I+- Kinutama

Claims (2)

【特許請求の範囲】[Claims] (1)第1基板上にゲート電極、ゲート絶縁膜、半導体
膜、ソース電極及びドレイン電極から構成される薄膜ト
ランジスタを複数本の走査電極線と信号電極線の交点付
近に配置してマトリクス状にし且つ各々の薄膜トランジ
スタに画素電極を接続してなるアレイ基板と、第2基板
上に対向電極を形成してなる対向基板との間に液晶を挟
持してなるアクティブマトリクス型液晶表示素子の製造
方法において、 前記第1基板上に透明導電膜を成膜した後、前記走査電
極線と前記半導体膜をマスクとした背面露光法を用いて
、前記透明導電膜をパターニングすることにより、前記
画素電極を形成する工程を備えたことを特徴とするアク
ティブマトリクス型液晶表示素子の製造方法。
(1) Thin film transistors consisting of a gate electrode, a gate insulating film, a semiconductor film, a source electrode, and a drain electrode are arranged on the first substrate near the intersections of a plurality of scanning electrode lines and signal electrode lines in a matrix shape, and In a method for manufacturing an active matrix liquid crystal display element, in which a liquid crystal is sandwiched between an array substrate in which a pixel electrode is connected to each thin film transistor, and a counter substrate in which a counter electrode is formed on a second substrate, After forming a transparent conductive film on the first substrate, the pixel electrode is formed by patterning the transparent conductive film using a back exposure method using the scanning electrode line and the semiconductor film as a mask. 1. A method for manufacturing an active matrix liquid crystal display element, comprising the steps of:
(2)第1基板上にゲート電極、ゲート絶縁膜、半導体
膜、ソース電極及びドレイン電極から構成される薄膜ト
ランジスタを複数本の走査電極線と信号電極線の交点付
近に配置してマトリクス状にし且つ各々の薄膜トランジ
スタに画素電極を接続してなるアレイ基板と、第2基板
上に対向電極を形成してなる対向基板との間に液晶を挟
持してなるアクティブマトリクス型液晶表示素子の製造
方法において、 前記第1基板上に光遮蔽膜を成膜した後にパターニング
してブラックマトリクスを形成する工程と、前記第1基
板上に透明導電膜を成膜した後、前記走査電極線と前記
ブラックマトリックスをマスクとした背面露光法を用い
て、前記透明導電膜をパターニングすることにより、前
記画素電極を形成する工程を備えたことを特徴とするア
クティブマトリクス型液晶表示素子の製造方法。
(2) Thin film transistors consisting of a gate electrode, a gate insulating film, a semiconductor film, a source electrode, and a drain electrode are arranged on the first substrate near the intersections of a plurality of scanning electrode lines and signal electrode lines in a matrix form, and In a method for manufacturing an active matrix liquid crystal display element, in which a liquid crystal is sandwiched between an array substrate in which a pixel electrode is connected to each thin film transistor, and a counter substrate in which a counter electrode is formed on a second substrate, A step of forming a light shielding film on the first substrate and then patterning to form a black matrix; and after forming a transparent conductive film on the first substrate, masking the scanning electrode line and the black matrix. A method for manufacturing an active matrix liquid crystal display element, comprising the step of forming the pixel electrode by patterning the transparent conductive film using a back exposure method.
JP1287509A 1989-11-06 1989-11-06 Manufacture of active matrix type liquid crystal display element Pending JPH03148636A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1287509A JPH03148636A (en) 1989-11-06 1989-11-06 Manufacture of active matrix type liquid crystal display element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1287509A JPH03148636A (en) 1989-11-06 1989-11-06 Manufacture of active matrix type liquid crystal display element

Publications (1)

Publication Number Publication Date
JPH03148636A true JPH03148636A (en) 1991-06-25

Family

ID=17718262

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JPH03148636A (en)

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