CN103715200A - Array substrate, preparation method thereof and display device - Google Patents
Array substrate, preparation method thereof and display device Download PDFInfo
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- CN103715200A CN103715200A CN201310706411.8A CN201310706411A CN103715200A CN 103715200 A CN103715200 A CN 103715200A CN 201310706411 A CN201310706411 A CN 201310706411A CN 103715200 A CN103715200 A CN 103715200A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
Abstract
The invention provides an array substrate, a preparation method thereof and a display device, and belongs to the display technical field. With the array substrate, the preparation method thereof and the display device of the invention adopted, the problem of complex production process of an existing array substrate can be solved. The preparation method of the array substrate comprises the following steps that: a pixel electrode film and an active layer film are sequentially deposited on a substrate; and a pattern including a pixel electrode and a film transistor active layer can be formed through one-step patterning process.
Description
Technical field
The invention belongs to Display Technique field, be specifically related to a kind of array base palte and preparation method thereof, display unit.
Background technology
In Display Technique field, the active layer of thin-film transistor is the excellent silicon based material such as stability in use energy, processing characteristics always, silicon based material is mainly divided into amorphous silicon and polysilicon, wherein amorphous silicon material mobility is very low, and although polycrystalline silicon material has higher mobility, but poor by the device uniformity of its manufacture, yield is low, and unit price is high.So in recent years, transparent oxide semiconductor film is manufactured to thin-film transistor (TFT) etc. for channel formation region, and the technology that is applied to electronic device and optical device is subject to extensive concern.Wherein, utilize and take the FET of the noncrystalline In-Ga-Zn-O based material (a-IGZO) that indium, gallium, zinc, oxygen be Constitution Elements and there is high mobility because of it, larger on-off ratio, and obtained maximum attracting attention.
As shown in Figure 1, its preparation method comprises in the cross section of existing thin-film transistor (top gate type structure):
Step 1, in substrate, deposit one deck active layer film, and form by composition technique the figure that comprises thin film transistor active layer 102;
Step 2, in the substrate that completes above-mentioned steps, form gate insulator 103;
Step 3, in the substrate that completes above-mentioned steps, deposition gate metal film, and form the figure that comprises grid 104 by composition technique;
Step 4, in the substrate that completes above-mentioned steps, form planarization layer 105;
Step 5, in the substrate that completes above-mentioned steps, by composition technique, form and to run through planarization layer 105 and gate insulator 103, what for source, the drain electrode 106 of thin-film transistor, be connected with active layer 102 first contacts via holes 110;
Step 6, in the substrate that completes above-mentioned steps, metallic film is leaked in formation source, and forms by composition technique the figure that comprises source electrode and drain electrode 106, source electrode and drain electrode 106 contact via hole 110 by corresponding first respectively and are connected with active layer 102;
Step 7, in the substrate that completes above-mentioned steps, form passivation layer 112;
Step 8, in the substrate that completes above-mentioned steps, form and to run through passivation layer 112, what for draining, is connected with pixel electrode 108 second contacts via hole 111;
Step 9, in the substrate that completes above-mentioned steps, by composition technique, form the figure comprise pixel electrode 108, and pixel electrode is connected with the drain electrode 106 of thin-film transistor by the second contact via hole 111.
In sum, the manufacturing process of existing thin-film transistor need be carried out mask exposure 6 times, and inventor finds that in prior art, at least there are the following problems: mask exposure has repeatedly strengthened the difficulty of technique, easily occur due to aligning accuracy deficiency cause bad, product yield declines, and cost is higher.
Summary of the invention
Technical problem to be solved by this invention comprises, the above-mentioned problem existing for the preparation method of existing array base palte, provides a kind of processing step simple, reduces costs the preparation method of the array base palte of enhancing productivity and array base palte, display unit.
The technical scheme that solution the technology of the present invention problem adopts is a kind of preparation method of array base palte, comprising:
Pixel deposition electrode film and active layer film successively in substrate, and form by a composition technique figure that comprises pixel electrode and thin film transistor active layer.
In the preparation method of array base palte of the present invention, pixel electrode and thin film transistor active layer are prepared by a composition technique, processing step is simplified compared with prior art, and then can be cost-saving, and has improved production efficiency.
Preferably, described formation comprises the figure of pixel electrode and thin film transistor active layer, adopts intermediate tone mask plate or gray scale mask plate.
Preferably, the material of described active layer is any one in indium oxide gallium zinc, indium zinc oxide, tin indium oxide, indium oxide gallium tin.
Further preferably, after comprising the figure of pixel electrode and thin film transistor active layer, formation also comprises:
Form gate insulator;
In the substrate that completes above-mentioned steps, by composition technique, form the figure that comprises film crystal tube grid;
In the substrate that completes above-mentioned steps, form planarization layer;
In the substrate that completes above-mentioned steps, by an etching technics, form and run through planarization layer, gate insulator, the first contact via hole contacts via hole with second;
In the substrate that completes above-mentioned steps, by composition technique, form the figure that comprises thin-film transistor source electrode and drain electrode, described the first contact via hole is for the source of thin-film transistor, drain electrode are connected with active layer respectively, and described the second contact via hole is for being connected thin-film transistor drain electrode with pixel electrode.
Further preferably, before comprising the figure of pixel electrode and thin film transistor active layer, formation also comprises:
In substrate, by composition technique, form the figure that comprises film crystal tube grid;
In the substrate that completes above-mentioned steps, form gate insulator.
Further preferably, after comprising the figure of pixel electrode and thin film transistor active layer, formation also comprises:
In substrate, form planarization layer;
In the substrate that completes above-mentioned steps, by an etching technics, the first contact via hole that formation runs through planarization layer contacts via hole with second;
In the substrate that completes above-mentioned steps, by composition technique, form the figure that comprises thin-film transistor source electrode and drain electrode, described the first contact via hole is for the source of thin-film transistor, drain electrode are connected with active layer respectively, and described the second contact via hole is for being connected thin-film transistor drain electrode with pixel electrode.
Preferably, the material of described active layer is amorphous silicon.
Further preferably, after comprising the figure of pixel electrode and thin film transistor active layer, formation also comprises:
In substrate, form gate insulator;
In the substrate that completes above-mentioned steps, by composition technique, form the figure that comprises film crystal tube grid;
In the substrate that completes above-mentioned steps, form planarization layer;
In the substrate that completes above-mentioned steps, by an etching technics, the first contact via hole that formation runs through planarization layer, gate insulator contacts via hole with second;
In the substrate that completes above-mentioned steps, form successively ohmic contact film and source and leak metallic film, and by composition technique, form the figure comprise ohmic contact layer, source electrode and drain electrode, described the first contact via hole is for the source of thin-film transistor, drain electrode are electrically connected to active layer respectively, and described the second contact via hole is for being electrically connected to thin-film transistor drain electrode with pixel electrode.
Further preferably, before comprising the figure of pixel electrode and thin film transistor active layer, formation also comprises:
In substrate, by composition technique, form the figure that comprises film crystal tube grid;
In the substrate that completes above-mentioned steps, form gate insulator.
Further preferably, after comprising the figure of pixel electrode and thin film transistor active layer, formation also comprises:
In substrate, form planarization layer;
In the substrate that completes above-mentioned steps, by an etching technics, form and to run through planarization layer, the first contact via hole contact via hole with second;
In the substrate that completes above-mentioned steps, form successively ohmic contact film and source and leak metallic film, and by composition technique, form the figure comprise ohmic contact layer, source electrode and drain electrode, described the first contact via hole is for the source of thin-film transistor, drain electrode are electrically connected to active layer respectively, and described the second contact via hole is for being electrically connected to thin-film transistor drain electrode with pixel electrode.
The technical scheme that solution the technology of the present invention problem adopts is a kind of array base palte, comprise thin film transistor region and viewing area, it is characterized in that, described thin film transistor region comprises thin-film transistor and pixel electrode, described viewing area comprises pixel electrode, the pixel electrode of described thin film transistor region and the pixel electrode of described viewing area arrange with layer and both disconnect, and the active layer of described thin-film transistor is arranged on the pixel electrode top of described thin film transistor region.
Array base palte provided by the present invention can be prepared by said method, therefore its cost is lower.
The technical scheme that solution the technology of the present invention problem adopts is a kind of display unit, and it comprises above-mentioned array base palte.
Because display unit of the present invention comprises above-mentioned array base palte, therefore its cost is lower.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of existing array base palte;
Fig. 2 is the preparation flow figure of step 1 in embodiments of the invention 1 and 2;
Fig. 3 is step 2 in embodiments of the invention 1 and 2, three schematic diagram;
Fig. 4 is step 4 in embodiments of the invention 1 and 2, five schematic diagram;
Fig. 5 is the schematic diagram of step 6 in embodiments of the invention 1; And,
Fig. 6 is the schematic diagram of step 6 in embodiments of the invention 2.
Wherein Reference numeral is: 101, substrate; 102, active layer; 103, gate insulator; 104, grid; 105, planarization layer; 106, source electrode and drain electrode; 107, passivation layer; 108, pixel electrode; 109, photoresist; 110, the first contact via hole; 111, the second contact via hole; 112, ohmic contact layer.
Embodiment
For making those skilled in the art understand better technical scheme of the present invention, below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Embodiment 1:
In conjunction with shown in Fig. 2 to 5, the present embodiment provides a kind of preparation method of array base palte, and it comprises the steps:
As shown in Figure 2, step 1, pixel deposition electrode film and active layer film successively in substrate 101, and apply one deck photoresist (PR) 109, preferably, adopt intermediate tone mask plate (Half Tone) or gray scale mask plate (Gray Tone) to expose, develop, (obtaining as shown in first figure in Fig. 2), then active layer film is done for the first time and carved and pixel electrode film wet etching, the photoresist of ashing part afterwards 109, (obtaining as shown in second figure in Fig. 2), carry out subsequently active layer film dry quarter for the second time, after stripping photoresist, (obtaining as shown in the 3rd figure in Fig. 2), formation comprises the figure of pixel electrode 108 and thin film transistor active layer 102.
Wherein, the material of pixel electrode 108 is the electric conducting materials such as tin indium oxide (ITO).
Wherein, the material of active layer 102 can be to comprise In(indium), Ga(gallium), Zn(zinc), O(oxygen), Sn(tin) etc. the film of element by sputter, form, wherein in film, must comprise two or more element of oxygen element and other, be preferably indium oxide gallium zinc (IGZO), indium zinc oxide (IZO), tin indium oxide (InSnO), indium oxide gallium tin (InGaSnO) etc.
It should be noted that, substrate 101 both can refer to not form the substrate of any rete, as white glass, also can refer to be formed with the substrate of other retes or pattern, for example, be formed with the substrate of resilient coating.Wherein, be easy to find out that pixel electrode 108 and thin film transistor active layer 102 prepared by a composition technique in step 1, processing step is simplified compared with prior art, and then can be cost-saving, and has improved production efficiency.
Step 2, in the substrate 101 that completes above-mentioned steps, adopt the preparation methods such as hot growth, aumospheric pressure cvd, low-pressure chemical vapor deposition, plasma auxiliary body chemical vapor deposition, sputter, form gate insulator 103.
Wherein, the material of described gate insulator 103 can be for the oxide (SiOx) of silicon, the oxide (HfOx) of the nitride (SiNx) of silicon, hafnium, the multilayer complex films a kind of or that in them, bi-material forms in the oxide (AlOx) of the nitrogen oxide (SiON) of silicon, aluminium etc.
Step 3, in the substrate 101 that completes above-mentioned steps, adopt method deposition one deck gate metal layer film of magnetron sputtering, and by composition technique, form the figure that comprises film crystal tube grid 104; Wherein, composition technique generally includes the techniques such as photoresist coating, exposure, development, etching, photoresist lift off.Above-mentioned steps first forms gate metal layer film, applies photoresist cover gate metal level film; Utilize mask plate exposure, form exposure region and non-exposed area; Develop and remove the photoresist (take positive photoresist as example) of exposure region, non-exposed area photoresist retains; Etching grid metal level film, the gate metal layer film of non-exposed area is not etched due to the protection of photoresist, and last stripping photoresist, forms the figure that comprises film crystal tube grid 104, obtains structure as shown in Figure 3.
Wherein, the material of described grid 104 can be the single or multiple lift composite laminate a kind of or that in them, multiple material forms in molybdenum (Mo), molybdenum niobium alloy (MoNb), aluminium (Al), aluminium neodymium alloy (AlNd), titanium (Ti) and copper (Cu), is preferably Mo, Al or containing the single or multiple lift composite membrane of the alloy composition of Mo, Al.
Step 4, in the substrate 101 that completes above-mentioned steps, form planarization layer 105.
Wherein, the material of planarization layer 105 can be for the oxide (SiOx) of silicon, the oxide (HfOx) of the nitride (SiNx) of silicon, hafnium, the oxide (AlOx) of the nitrogen oxide (SiON) of silicon, aluminium etc. or formed by two or three multilayer film forming wherein.
Step 5, in the substrate 101 that completes above-mentioned steps, by an etching technics, form the first contact via hole 110 run through planarization layer 105, gate insulator 103 and contact via hole 111 with second, obtain structure as shown in Figure 4.
Wherein, the first contact via hole 110 contacts via hole 111 with second be to adopt an etching technics to form, and controls the consumption of etching liquid in forming process, to control the first contact via hole 110, contacts the formation of via hole 111 with second.
Step 6, complete in the substrate of above-mentioned steps 101, adopt method deposition one deck source of magnetron sputtering to leak metallic film, and by composition technique, form the figure comprise thin-film transistor source electrode and drain electrode 106, wherein, the first contact via hole 110 is for being connected the source of thin-film transistor, drain electrode 106 respectively with active layer 102, the second contact via hole 111, for thin-film transistor drain electrode 106 is connected with pixel electrode, obtains the structure as shown in 5.Concrete formation method is similar to the formation of grid 104, at this, is not described in detail.
Wherein, described source electrode and drain electrode 106 material can be that one or more materials in molybdenum (Mo), molybdenum niobium alloy (MoNb), aluminium (Al), aluminium neodymium alloy (AlNd), titanium (Ti) and copper (Cu) form, and are preferably Mo, Al or contain the alloy material of Mo, Al.
The preparation method of the array base palte that the present embodiment provides has adopted photoetching process 4 times, compared with prior art, has saved production cost, has improved production efficiency, simplified production process, so practicality is stronger.
It will be understood by those skilled in the art that, thin-film transistor in above-mentioned array base palte is the thin-film transistor of top gate structure, certainly the thin-film transistor of preparing bottom grating structure is also fine, concrete steps and above-mentioned steps are roughly the same, different when difference is its order that forms each structure and prepares top gate type thin film transistor, its preparation process can comprise:
In substrate 101, form gate metal film, and form by composition technique the figure that comprises film crystal tube grid 104;
In the substrate 101 that completes above-mentioned steps, form gate insulator 103;
In the substrate 101 that completes above-mentioned steps, pixel deposition electrode film and active layer film successively, and form by a composition technique figure that comprises pixel electrode 108 and thin film transistor active layer 102;
In the substrate 101 that completes above-mentioned steps, form planarization layer 105;
In the substrate 101 that completes above-mentioned steps, by an etching technics, the first contact via hole 110 that formation runs through planarization layer 105 contacts via hole 111 with second.
In the substrate 101 that completes above-mentioned steps, metallic film is leaked in formation source, and by composition technique, form the figure comprise thin-film transistor source electrode and drain electrode 106, wherein, described the first contact via hole 110 is for the source of thin-film transistor, drain electrode 106 are connected with active layer 102 respectively, and described the second contact via hole 111 is for being connected thin-film transistor drain electrode 106 with pixel electrode 108.
It should be noted that, the thin-film transistor of above-mentioned bottom grating structure is that from the main difference of the thin-film transistor of top gate type structure grid 104 is different with the formation order of active layer 102, the material adopting of the thin-film transistor of two kinds of structures is identical, at this, does not repeat to repeat.
Embodiment 2:
As shown in Fig. 2,3,4,6, the present embodiment provides a kind of preparation method of array base palte, roughly the same with the preparation method of the array base palte described in embodiment 1, and topmost difference is the material difference that active layer adopts, and it specifically comprises the steps:
As shown in Figure 2, step 1, pixel deposition electrode film and active layer film successively in substrate 101, and apply one deck photoresist (PR) 109, preferably, adopt intermediate tone mask plate (Half Tone) or gray scale mask plate (Gray Tone) to expose, develop, (obtaining as shown in first figure in Fig. 2), then active layer film is done and carved and pixel electrode film wet etching for the first time, the photoresist of ashing part afterwards 109, (obtaining as shown in second figure in Fig. 2), carry out subsequently active layer film dry quarter for the second time, after stripping photoresist, (obtaining as shown in the 3rd figure in Fig. 2), formation comprises the figure of pixel electrode 108 and thin film transistor active layer 102.
Wherein, the material of pixel electrode 108 is the electric conducting materials such as tin indium oxide (ITO).
Wherein, the material of active layer 102 is preferably amorphous silicon (a-Si).
Wherein, be easy to find out that pixel electrode 108 and thin film transistor active layer 102 prepared by a composition technique in step 1, processing step is simplified compared with prior art, and then can be cost-saving, and has improved production efficiency.
Step 2, in the substrate 101 that completes above-mentioned steps, adopt the preparation methods such as hot growth, aumospheric pressure cvd, low-pressure chemical vapor deposition, plasma auxiliary body chemical vapor deposition, sputter, form gate insulator 103.
Wherein, the material of described gate insulator 103 can be for the oxide (SiOx) of silicon, the oxide (HfOx) of the nitride (SiNx) of silicon, hafnium, the multilayer complex films a kind of or that in them, bi-material forms in the oxide (AlOx) of the nitrogen oxide (SiON) of silicon, aluminium etc.
Step 3, in the substrate 101 that completes above-mentioned steps, adopt method deposition one deck gate metal layer film of magnetron sputtering, and by composition technique, form the figure that comprises film crystal tube grid 104, obtain structure as shown in Figure 3.
Wherein, the material of described grid 104 can be the single or multiple lift composite laminate a kind of or that in them, multiple material forms in molybdenum (Mo), molybdenum niobium alloy (MoNb), aluminium (Al), aluminium neodymium alloy (AlNd), titanium (Ti) and copper (Cu), is preferably Mo, Al or containing the single or multiple lift composite membrane of the alloy composition of Mo, Al.
Step 4, in the substrate 101 that completes above-mentioned steps, form planarization layer 105.
Wherein, the material of planarization layer 105 can be for the oxide (SiOx) of silicon, the oxide (HfOx) of the nitride (SiNx) of silicon, hafnium, the oxide (AlOx) of the nitrogen oxide (SiON) of silicon, aluminium etc. or formed by two or three multilayer film forming wherein.
Step 5, in the substrate 101 that completes above-mentioned steps, by an etching technics, form the first contact via hole 110 run through planarization layer 105, gate insulator 103 and contact via hole 111 with second, obtain structure as shown in Figure 4.
Wherein, the first contact via hole 110 contacts via hole 111 with second be to adopt an etching technics to form, and controls the consumption of etching liquid in forming process, to control the first contact via hole 110, contacts the formation of via hole 111 with second.
Step 6, in the substrate 101 that completes above-mentioned steps, adopt the method for magnetron sputtering to deposit successively one deck formation ohmic contact film and source leakage metallic film, and by composition technique, form the figure comprise ohmic contact layer (n+a-Si) 112, thin-film transistor source electrode and drain electrode 106, wherein, described the first contact via hole 110 is for being electrically connected to the source of thin-film transistor, drain electrode 106 respectively with active layer 102, described the second contact 111 via holes, for thin-film transistor drain electrode 106 is electrically connected to pixel electrode 108, obtain structure as shown in Figure 6.Concrete formation method is similar to the formation of grid 104, at this, is not described in detail.
Wherein, the ohmic contact of ohmic contact layer 112 for guaranteeing that source electrode and drain electrode and active layer 102 are good.
Wherein, described source electrode and drain electrode 106 material can be that one or more materials in molybdenum (Mo), molybdenum niobium alloy (MoNb), aluminium (Al), aluminium neodymium alloy (AlNd), titanium (Ti) and copper (Cu) form, and are preferably Mo, Al or contain the alloy material of Mo, Al.
The preparation method of the array base palte that the present embodiment provides has adopted photoetching process 4 times, compared with prior art, has saved production cost, has improved production efficiency, simplified production process, so practicality is stronger.
It will be understood by those skilled in the art that, thin-film transistor in above-mentioned array base palte is the thin-film transistor of top gate structure, certainly the thin-film transistor of preparing bottom grating structure is also fine, concrete steps and above-mentioned steps are roughly the same, different when difference is its order that forms each structure and prepares top gate type thin film transistor, its preparation process can comprise:
In substrate 101, form gate metal film, and form by composition technique the figure that comprises film crystal tube grid 104;
In the substrate 101 that completes above-mentioned steps, form gate insulator 103;
In the substrate 101 that completes above-mentioned steps, pixel deposition electrode film and active layer film successively, and form by a composition technique figure that comprises pixel electrode 108 and thin film transistor active layer 102;
In the substrate 101 that completes above-mentioned steps, form planarization layer 105;
In the substrate 101 that completes above-mentioned steps, by an etching technics, the first contact via hole 110 that formation runs through planarization layer 105 contacts via hole 111 with second;
In the substrate 101 that completes above-mentioned steps, form successively ohmic contact film and source and leak metallic film, and by composition technique, form the figure comprise ohmic contact layer 112, source electrode and drain electrode 106, wherein, described the first contact via hole 110 is for the source of thin-film transistor, drain electrode 106 are electrically connected to active layer 102 respectively, and described the second contact via hole 111 is for being electrically connected to thin-film transistor drain electrode 106 with pixel electrode 108.
It should be noted that, the main difference of the thin-film transistor of the thin-film transistor of above-mentioned bottom grating structure and top gate type structure is the formation order of grid 104 and active layer 102, the material adopting of the thin-film transistor of two kinds of structures is identical, at this, does not repeat to repeat.
Embodiment 3:
The present embodiment provides a kind of array base palte, comprise thin film transistor region and viewing area, it is characterized in that, described thin film transistor region comprises thin-film transistor and pixel electrode, described viewing area comprises pixel electrode, the pixel electrode of described thin film transistor region and the pixel electrode of described viewing area arrange with layer and both disconnect, and the active layer of described thin-film transistor is arranged on the pixel electrode top of described thin film transistor region.
Because the array base palte that the present embodiment provides can be prepared by the preparation method described in embodiment 1 or 2, its structure also structure prepared with method described in embodiment 1 or 2 is identical, at this, is not repeated in this description other structures of this array base palte.Therefore the cost of its this array base palte is low.
Certainly this array base palte also comprises the element of other conventional arrays substrates such as data wire, scan line.
Embodiment 4:
The present embodiment provides a kind of display unit, it comprises the array base palte in embodiment 3, and this display unit can be: any product or parts with Presentation Function such as mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.
In the display unit of the present embodiment, there is the array base palte in embodiment 3, therefore its cost is low.
Certainly, in the display unit of the present embodiment, can also comprise other conventional structures, as power subsystem, display driver unit etc.
Be understandable that, above execution mode is only used to principle of the present invention is described and the illustrative embodiments that adopts, yet the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.
Claims (12)
1. a preparation method for array base palte, is characterized in that, comprising:
Pixel deposition electrode film and active layer film successively in substrate;
By a composition technique, form the figure that comprises pixel electrode and thin film transistor active layer.
2. the preparation method of array base palte according to claim 1, is characterized in that, described formation comprises the figure of pixel electrode and thin film transistor active layer, adopts intermediate tone mask plate or gray scale mask plate.
3. the preparation method of array base palte according to claim 1, is characterized in that, the material of described active layer is any one in indium oxide gallium zinc, indium zinc oxide, tin indium oxide, indium oxide gallium tin.
4. the preparation method of array base palte according to claim 3, is characterized in that, after formation comprises the figure of pixel electrode and thin film transistor active layer, also comprises:
Form gate insulator;
In the substrate that completes above-mentioned steps, by composition technique, form the figure that comprises film crystal tube grid;
In the substrate that completes above-mentioned steps, form planarization layer;
In the substrate that completes above-mentioned steps, by an etching technics, the first contact via hole that formation runs through planarization layer, gate insulator contacts via hole with second;
In the substrate that completes above-mentioned steps, by composition technique, form the figure that comprises thin-film transistor source electrode and drain electrode, described the first contact via hole is for the source of thin-film transistor, drain electrode are connected with active layer respectively, and described the second contact via hole is for being connected thin-film transistor drain electrode with pixel electrode.
5. the preparation method of array base palte according to claim 3, is characterized in that, also comprises before comprising the figure of pixel electrode and thin film transistor active layer in formation:
In substrate, by composition technique, form the figure that comprises film crystal tube grid;
In the substrate that completes above-mentioned steps, form gate insulator.
6. the preparation method of array base palte according to claim 5, is characterized in that, after formation comprises the figure of pixel electrode and thin film transistor active layer, also comprises:
In substrate, form planarization layer;
In the substrate that completes above-mentioned steps, by an etching technics, the first contact via hole that formation runs through planarization layer contacts via hole with second;
In the substrate that completes above-mentioned steps, by composition technique, form the figure that comprises thin-film transistor source electrode and drain electrode, described the first contact via hole is for the source of thin-film transistor, drain electrode are connected with active layer respectively, and described the second contact via hole is for being connected thin-film transistor drain electrode with pixel electrode.
7. the preparation method of array base palte according to claim 1, is characterized in that, the material of described active layer is amorphous silicon.
8. the preparation method of array base palte according to claim 7, is characterized in that, after formation comprises the figure of pixel electrode and thin film transistor active layer, also comprises:
Form gate insulator;
In the substrate that completes above-mentioned steps, by composition technique, form the figure that comprises film crystal tube grid;
In the substrate that completes above-mentioned steps, form planarization layer;
In the substrate that completes above-mentioned steps, by an etching technics, the first contact via hole that formation runs through planarization layer, gate insulator contacts via hole with second;
In the substrate that completes above-mentioned steps, by composition technique, form the figure that comprises ohmic contact layer, source electrode and drain electrode successively, described the first contact via hole is for the source of thin-film transistor, drain electrode are electrically connected to active layer respectively, and described the second contact via hole is for being electrically connected to thin-film transistor drain electrode with pixel electrode.
9. the preparation method of array base palte according to claim 7, is characterized in that, also comprises before comprising the figure of pixel electrode and thin film transistor active layer in formation:
In substrate, form gate metal film, and form by composition technique the figure that comprises film crystal tube grid;
In the substrate that completes above-mentioned steps, form gate insulator.
10. the preparation method of array base palte according to claim 9, is characterized in that, after formation comprises the figure of pixel electrode and thin film transistor active layer, also comprises:
In substrate, form planarization layer;
In the substrate that completes above-mentioned steps, by an etching technics, formation runs through planarization layer, for the first contact via hole that the source of thin-film transistor, drain electrode are connected with active layer respectively and the second contact via hole being connected with pixel electrode for thin-film transistor is drained;
In the substrate that completes above-mentioned steps, form successively ohmic contact film and source and leak metallic film, and form by composition technique the figure that comprises ohmic contact layer, source electrode and drain electrode.
11. 1 kinds of array base paltes, comprise thin film transistor region and viewing area, it is characterized in that, described thin film transistor region comprises thin-film transistor and pixel electrode, described viewing area comprises pixel electrode, the pixel electrode of described thin film transistor region and the pixel electrode of described viewing area arrange with layer and both disconnect, and the active layer of described thin-film transistor is arranged on the pixel electrode top of described thin film transistor region.
12. 1 kinds of display unit, is characterized in that, comprise the array base palte described in claim 11.
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