JPS61194779A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To form opening sections for a drain electrode and a source electrode in a self-alignment manner to a gate electrode by forming a first insulating film coating the surface and side surface of the gate electrode, shaping a second insulating film coating the upper sections of source-in regions and the upper section of the first insulating film and selecting the etching rate of the second insulating film at a value higher than the etching rate of the first insulating film. CONSTITUTION:An SiO2 film 10 is grown on the upper surface and side surface of a gate electrode 7, an Si3N4 film 11 and further SiO2 12 onto the Si3N4 film 11 are grown in a vapor phase manner, and laminatings except a gate region are removed. Si3N4 13 is grown on the whole surface in the vapor phase manner. The Si3N4 layer is etched extending over the whole surface through a reactive ion etching method. The SiO2 film 12 on a gate is removed through etching, and a PSG film 8 is grown on the whole surface in the vapor phase manner. A resist film 14 to which source-drain electrode contact forming sections are bored through a photolithographic method is shaped, and the PSG film 8 is etched. Contact opening sections 9 for the PSG film are etched by a selection ratio of the PSG film 8 to the Si3N4 film 13 through the etching, and the stepped section of the Si3N4 film 13 is hardly etched.

Description

[Detailed Description of the Invention] [Summary] In order to eliminate the need to consider mask alignment errors when forming electrode contact openings and to improve the degree of integration, source and drain electrode contact openings are formed in a self-aligned manner. MIS (Metal
Insulator Semiconductor)
F ET (Field Effect "l'ra"
nsistor) structure and formation method.

[Industrial application field]

The present invention relates to a structure of a gate insulating film in a MIS structure and a method of forming source and drain electrode contact portions related thereto.

With the improvement in the degree of integration of semiconductor integrated circuits, MI5FET
There is a tendency for the gap size between the gate I-electrode and the source and drain electrodes to become smaller and smaller.

However, when forming the source and drain electrode contacts, it is necessary to select the gap dimensions as design dimensions, including the alignment tolerance, taking into account the alignment accuracy of the mask. There is a need for improvements to reduce this.

[Conventional technology]

Gate electrode structure of MisFET according to conventional technology,
A method for forming the source and drain electrode contact portions will be explained in detail with reference to FIG.

FIG. 2(a) shows a cross-sectional view of the process immediately before forming source and drain electrode contact portions.

In the drawing, a p-type silicon substrate 1 is provided with n-type source and drain diffusion regions 2 and 3, a field oxide film 4, a p-type parasitic channel prevention layer 5, and a gate layer 5). A silicon dioxide insulating film 6 is provided in the J region.
, the formation of the polycrystalline silicon that will become the gate electrode 7 is completed,
A state in which a PSG film 8 is laminated as an insulating film over the entire surface is shown.

Next, by photolithography, the PSG film 8 is removed by etching, except for the region where the electrode contact opening 9 is to be formed, while masking the rest with a resist film. This state is shown in FIG. 2(b).

At this time, the polycrystalline silicon gate electrode 7 and the remaining PSG
If the film dimension a is 0.3 to 0.5 μm, it will have a sufficient function as an insulating layer.

However, in forming the contact opening 9, the three dimensions are designed to be 0.8 to 1.0 μm, taking into account the tolerance of mask alignment accuracy of 0.3 to 0.5 μm.

[Problem that the invention seeks to solve]

As explained in the above conventional technology, the gap dimension a between the gate electrode and the source or drain electrode is approximately 0.5 μm.
In order to have a margin of 1.0 .mu.m, a dimensional margin of approximately 1.0 .mu.m is required for each transistor.

This is a semiconductor integrated circuit that uses a large number of transistors &, 1
This is a major obstacle to achieving high integration in LSI designs that require a single integration, and a solution is required.

[Means for solving problems]

In order to solve the above problem, the structure around the gate electrode is constructed as shown in FIG. 1 (dl, (elO).

That is, the first insulating film 1 has a gate electrode 7, a source region 2, and a drain region 3, and covers the front and side surfaces of the gate electrode.
1.13 is formed.

Next, a second insulating film 8 is provided covering the source and drain regions and the first insulating film.

Since the etching rate of the second insulating film formed at this time is selected to be higher than the etching rate of the first insulating film, it is formed on the side surface of the gate electrode within the electrode window for connecting the drain electrode and source electrode. The first insulating film is exposed, and the MIS FE has extremely high alignment accuracy.
The structure of T is obtained.

Further, as a manufacturing method thereof, a first insulating film is formed to cover the side surfaces and the surface of the gate electrode. Next, a second insulating film is formed which covers the source, drain and the first insulating film and has a higher etching rate than the first insulating film.

Next, by forming openings for connecting the source and drain electrodes in the second insulating film, the first insulating film is exposed on the side surface of the gate electrode, resulting in a misalignment with extremely high alignment accuracy.
The FET structure is formed in a self-aligned manner.

[Effect]

The gate electrode was made of thin 5iO12, then thick Si3N.
By stacking a, the gap size between the gate electrode and the source and drain electrodes is mostly regulated by the thickness of the 5i3Nn film at the stepped portion of the gate electrode.

For this reason, the source and drain electrode cores are formed on the PSG film by a dry etching method.
By using the etching selectivity with respect to the 3N4 film, it is possible to form the gate electrode in a self-aligned manner.

〔Example〕

An embodiment according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing the PS
A cross-sectional view of the structure at each step is shown before the G film 8 is formed.

In the drawings, explanations of the same numbers explained in FIG. 2 will be omitted.

FIG. 1 (Al is Si on the top and side surfaces of the gate electrode 7.
A total of 100 to 500 O□ films were grown, and then Si3N
4 membranes 11 for about 1000 to 2000 people, and furthermore, S i 3
1000~200 5iOz12 on the N4 film 11
The state is shown in which the layer is grown in a vapor phase to a thickness of 0.0 mm and the stacked layers other than the gate region are removed.

Here, 5iOz12 is not necessarily required.

Next, apply approximately 2000 to 2500 5i3N413 to the entire surface.
It is grown by vapor phase to the thickness of a person. This is shown in Figure 1 (bl).

Furthermore, Si3 was etched using reactive ion etching (RIE).
Etch the entire N4 layer. Since the RIE method is anisotropic, Si stacked on a plane parallel to the substrate surface
The 3N4 layer 13 is removed, and the 5izN411 protected by the Si3N4 film 13 and the 5i02 film 12 stacked vertically on the gate portion is left in the shape shown in FIG. 1 (C1).

Next, the entire SiO□ film 12 on the gate is removed by 12 steps, and a PSG film 8 is grown in a vapor phase over the entire surface. This is shown in Figure 1 (
Shown in d).

Next, a resist film 14 with openings for source and train electrode contact forming portions is formed by photolithography,
The PSG film 8 is etched using a reactive plasma etching method.

In this etching, the contact opening 9 of the PSG film is etched due to the selection ratio between the PSG film 8 and the 5i3Na film 13, and the step portion of the film 13 where S i 3 N < is hardly etched.

Therefore, the gap size between the electrode contact opening 9 and the gate electrode is determined mostly by the thickness of the Si3N4 layer 13. By the above method, the gap between the source/drain electrode and the gate electrode is formed in a self-aligned manner depending on the thickness of the S+3Na film.

The subsequent process of forming the aluminum electrode layer is the same as the conventional method.

〔Effect of the invention〕

By using the insulating layer structure of the gate electrode and the method for forming the electrode contact portion of the present invention, the source and drain electrode contact openings are formed in a self-aligned manner with respect to the gate electrode, taking into account accuracy errors in mask alignment. The electrode gap size can be determined without any problems. Therefore, it greatly contributes to higher integration.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing an embodiment of the present invention in the order of steps, and FIG. 2 is a cross-sectional view showing an electrode contact part in the middle of the process according to the prior art. In the drawing, ① indicates a p-type silicon substrate, 2 indicates a source diffusion region, 3 indicates a drain diffusion region, 4 indicates a field oxide film, 5 indicates a parasitic channel prevention layer, 6.10.12 indicates a 5in2 film, and 7 indicates a gate electrode. , 8 is a PSG film, 9 is an electrode contact opening, 11.13 is a Si3N film, and 14 is a resist film. The present invention/l (other fl'Jr + engineering 1!
iOz Example of ablation of the present invention τ Hogami explanatory diagram 1r'4

Claims (2)

[Claims] (1) A first insulating film 1 that has a gate electrode 7, a source region 2, and a drain region 3 and covers the front and side surfaces of the gate electrode.
1 and 13, and a second insulating film 8 covering the source and drain regions and the first insulating film, the etching rate of the second insulating film being equal to that of the first insulating film. A semiconductor device characterized in that the first insulating film formed on the side surface of the gate electrode is exposed within an electrode window for connecting a drain electrode and a source electrode, the first insulating film being higher than an etching rate. (2) forming a first insulating film that covers the side surfaces and surface of the gate electrode; and forming a second insulating film that covers the source, drain, and the first insulating film and has a higher etching rate than the first insulating film; a step of forming an insulating film, and then openings for connecting the source and drain electrodes to the second
1. A method for manufacturing a semiconductor device, comprising the step of forming an insulating film.