JPH04360580A - Field-effect transistor and manufacture thereof - Google Patents

Field-effect transistor and manufacture thereof

Info

Publication number
JPH04360580A
JPH04360580A JP16244491A JP16244491A JPH04360580A JP H04360580 A JPH04360580 A JP H04360580A JP 16244491 A JP16244491 A JP 16244491A JP 16244491 A JP16244491 A JP 16244491A JP H04360580 A JPH04360580 A JP H04360580A
Authority
JP
Japan
Prior art keywords
film
aluminum
region
gate electrode
effect transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16244491A
Other languages
Japanese (ja)
Inventor
Tatsuya Miyagawa
達也 宮川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP16244491A priority Critical patent/JPH04360580A/en
Publication of JPH04360580A publication Critical patent/JPH04360580A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To reduce the number of manufacturing steps, and to efficiently form a micro-offset gate region by providing an anodized film at least on the side face of a gate electrode, and making the side of the film correspond to the boundary face between a channel region of a semiconductor layer and a source/ drain region. CONSTITUTION:With an aluminum film 4 formed on a gate insulating film 3 of a part of a semiconductor layer 2, corresponding to a channel region 2a as a mask an ion implantation is conducted to form a source/drain region 2b. A surface of the film 4 is anodized to form an aluminum oxide film 5, and a gate electrode 6 is formed of the film 4 which is not anodized. Thus, the side of the film 5 corresponding to a boundary between the region 2a of the layer 2 and the region 2b, the thickness of the film 5 becomes a length L of an offset gate region 2c, and the region 2c can be efficiently formed.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】この発明は電界効果型トランジス
タおよびその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and a method of manufacturing the same.

【0002】0002

【従来の技術】電界効果型トランジスタには、リーク電
流の低減を図った素子として、オフセットゲート構造と
呼ばれるものがある。このような電界効果型トランジス
タでは、ポリシリコン等からなる半導体層のチャネル長
さよりもゲート電極の長さを小さくすることにより、ゲ
ート電極の両側におけるチャネル領域をオフセットゲー
ト領域とした構造となっている。従来のこのような電界
効果型トランジスタを製造する場合には、まずセラミッ
クやガラス等からなる絶縁基板の上面にポリシリコン層
をパターン形成し、このポリシリコン層をゲート絶縁膜
で覆い、ポリシリコン層のチャネル領域に対応する部分
のゲート絶縁膜の上面にフォトレジスト膜をパターン形
成し、このフォトレジスト膜をマスクとしてイオン注入
を行うことにより、フォトレジスト膜の両側におけるポ
リシリコン層にソース・ドレイン領域を形成し、この後
フォトレジスト膜を除去し、活性化を行ってイオンを拡
散し、次いでポリシリコン層のチャネル領域の中央部に
対応する部分のゲート絶縁膜の上面にチャネル領域より
も幅狭のゲート電極をパターン形成し、これによりゲー
ト電極の両側におけるチャネル領域をオフセットゲート
領域としている。
2. Description of the Related Art Among field effect transistors, there is a type called an offset gate structure as an element designed to reduce leakage current. In such a field effect transistor, the length of the gate electrode is made smaller than the channel length of a semiconductor layer made of polysilicon or the like, so that the channel regions on both sides of the gate electrode are made into offset gate regions. . When manufacturing such a conventional field effect transistor, first a polysilicon layer is patterned on the top surface of an insulating substrate made of ceramic, glass, etc., this polysilicon layer is covered with a gate insulating film, and then a polysilicon layer is formed. A photoresist film is patterned on the upper surface of the gate insulating film in a portion corresponding to the channel region, and ions are implanted using this photoresist film as a mask to form source/drain regions in the polysilicon layer on both sides of the photoresist film. After that, the photoresist film is removed and activated to diffuse ions, and then a layer narrower than the channel region is formed on the upper surface of the gate insulating film in a portion of the polysilicon layer corresponding to the center of the channel region. The gate electrode is patterned so that the channel regions on both sides of the gate electrode are offset gate regions.

【0003】0003

【発明が解決しようとする課題】しかしながら、従来の
このような電界効果型トランジスタの製造方法では、通
常の電界効果型トランジスタを製造する場合と比較して
、すなわち例えばポリシリコンからなるゲート電極をマ
スクとしてイオン注入を行う場合と比較して、イオン注
入マスク用のフォトレジスト膜をパターン形成する工程
およびその除去工程の分だけ製造工程数が多く、コスト
高になるという問題があった。また、オフセットゲート
領域の長さ(L;図3参照)が大きいと、電界効果型ト
ランジスタのオン電流が低下してしまうので、オフセッ
トゲート領域の長さが1μ以下と小さい方が望ましいが
、フォトレジスト膜形成工程とゲート電極形成工程とが
別々であるので、オフセットゲート領域を効率的に形成
することができず、このため高い加工精度が要求され、
より一層コスト高になるという問題があった。この発明
の目的は、製造工程数を少なくすることができ、また微
小なオフセットゲート領域を効率的に形成することので
きる電界効果型トランジスタおよびその製造方法を提供
することにある。
[Problems to be Solved by the Invention] However, in the conventional manufacturing method of such a field effect transistor, compared to manufacturing a normal field effect transistor, it is difficult to mask the gate electrode made of, for example, polysilicon. Compared to the case where ion implantation is performed as an ion implantation method, there is a problem that the number of manufacturing steps is increased due to the step of patterning a photoresist film for an ion implantation mask and the step of removing it, resulting in higher costs. Furthermore, if the length of the offset gate region (L; see Figure 3) is large, the on-current of the field effect transistor will decrease, so it is desirable that the length of the offset gate region be as small as 1μ or less. Since the resist film forming process and the gate electrode forming process are separate, it is not possible to form the offset gate region efficiently, and therefore high processing accuracy is required.
There was a problem that the cost became even higher. An object of the present invention is to provide a field effect transistor and a method for manufacturing the same, which can reduce the number of manufacturing steps and efficiently form a minute offset gate region.

【0004】0004

【課題を解決するための手段】請求項1記載の発明は、
半導体層のチャネル長さよりもゲート電極の長さを小さ
くした電界効果型トランジスタにおいて、前記ゲート電
極の少なくとも長さ方向の側面に陽極酸化膜を設けると
共に、この陽極酸化膜の側面を前記半導体層のチャネル
領域とソース・ドレイン領域との境界面と対応するよう
にしたものである。請求項4記載の発明は、半導体層上
にゲート絶縁膜を形成し、前記半導体層のチャネル領域
に対応する部分の前記ゲート絶縁膜上にアルミニウム膜
を形成し、前記アルミニウム膜をマスクとしてイオン注
入を行うことにより、前記アルミニウム膜の両側におけ
る前記半導体層にソース・ドレイン領域を形成し、前記
アルミニウム膜の表面を陽極酸化することにより、前記
アルミニウム膜の表面に酸化アルミニウム膜を形成する
と共に、陽極酸化されない前記アルミニウム膜によって
ゲート電極を形成するようにしたものである。
[Means for solving the problem] The invention according to claim 1 includes:
In a field effect transistor in which the length of the gate electrode is smaller than the channel length of the semiconductor layer, an anodic oxide film is provided on at least the longitudinal side of the gate electrode, and the side of the anodic oxide film is formed on the side of the semiconductor layer. This corresponds to the interface between the channel region and the source/drain region. The invention according to claim 4 provides a method of forming a gate insulating film on a semiconductor layer, forming an aluminum film on the gate insulating film in a portion corresponding to a channel region of the semiconductor layer, and performing ion implantation using the aluminum film as a mask. By performing this step, source/drain regions are formed in the semiconductor layer on both sides of the aluminum film, and by anodizing the surface of the aluminum film, an aluminum oxide film is formed on the surface of the aluminum film, and an anode is formed on the surface of the aluminum film. The gate electrode is formed of the aluminum film that is not oxidized.

【0005】[0005]

【作用】この発明によれば、ゲート電極の少なくとも側
面に陽極酸化膜を設けると共に、この陽極酸化膜の側面
を半導体層のチャネル領域とソース・ドレイン領域との
境界面と対応するようにしているので、ゲート電極の少
なくとも側面に陽極酸化膜を設ければよく、従来のよう
にイオン注入マスク用のフォトレジスト膜をパターン形
成した後除去する場合と比較して、製造工程数を少なく
することができ、また陽極酸化膜の膜厚をそのままオフ
セットゲート領域とすることができ、陽極酸化膜の膜厚
を制御することにより、オフセットゲート領域を効率的
に形成することができる。
[Operation] According to the present invention, an anodic oxide film is provided on at least the side surface of the gate electrode, and the side surface of the anodic oxide film is made to correspond to the interface between the channel region and the source/drain region of the semiconductor layer. Therefore, it is sufficient to provide an anodic oxide film on at least the side surfaces of the gate electrode, and the number of manufacturing steps can be reduced compared to the conventional case where a photoresist film for an ion implantation mask is patterned and then removed. Furthermore, the thickness of the anodic oxide film can be used as it is for the offset gate region, and by controlling the thickness of the anodic oxide film, the offset gate region can be efficiently formed.

【0006】[0006]

【実施例】まず、図4はこの発明の一実施例における電
界効果型トランジスタの構造を示したものである。この
電界効果型トランジスタでは、セラミックやガラス等か
らなる絶縁基板1の上面にポリシリコン層(半導体層)
2が設けられ、ポリシリコン層2の上面等に酸化シリコ
ン等からなるゲート絶縁膜3が設けられ、ポリシリコン
層2のチャネル領域2aの中央部(両側のオフセットゲ
ート領域2cとなる部分を除く部分)に対応する部分の
ゲート絶縁膜3の上面にアルミニウムからなるゲート電
極6が設けられ、ゲート電極6の表面に酸化アルミニウ
ム膜(陽極酸化膜)5が設けられ、そして酸化アルミニ
ウム膜5の両側におけるポリシリコン層2にソース・ド
レイン領域2bが形成され、ゲート電極6の両側におけ
るチャネル領域2aがオフセットゲート領域2cとされ
、さらに層間絶縁膜7、コンタクトホール8およびソー
ス・ドレイン電極9が設けられた構造となっている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS First, FIG. 4 shows the structure of a field effect transistor according to an embodiment of the present invention. In this field effect transistor, a polysilicon layer (semiconductor layer) is formed on the top surface of an insulating substrate 1 made of ceramic, glass, etc.
A gate insulating film 3 made of silicon oxide or the like is provided on the upper surface of the polysilicon layer 2, and a gate insulating film 3 made of silicon oxide or the like is provided on the upper surface of the polysilicon layer 2. ) A gate electrode 6 made of aluminum is provided on the upper surface of the gate insulating film 3 in a portion corresponding to 1.), an aluminum oxide film (anodized film) 5 is provided on the surface of the gate electrode 6, and Source/drain regions 2b are formed in the polysilicon layer 2, channel regions 2a on both sides of the gate electrode 6 are used as offset gate regions 2c, and an interlayer insulating film 7, a contact hole 8, and a source/drain electrode 9 are provided. It has a structure.

【0007】次に、このような構造の電界効果型トラン
ジスタを製造する場合について説明すると、まず図1に
示すように、セラミックやガラス等からなる絶縁基板1
の上面にポリシリコン層2をパターン形成する。次に、
図2に示すように、全表面に酸化シリコン等からなるゲ
ート絶縁膜3を形成し、このゲート絶縁膜3でポリシリ
コン層2を覆う。次に、ポリシリコン層2のチャネル領
域2aに対応する部分のゲート絶縁膜3の上面にゲート
電極等を形成するためのアルミニウム膜4をパターン形
成する。次に、アルミニウム膜4をマスクとしてイオン
注入を行うことにより、アルミニウム膜4の両側におけ
るポリシリコン層2にソース・ドレイン領域2bを形成
し、次いでエキシマレーザの照射等により活性化を行っ
てイオンを拡散する。
Next, to explain the case of manufacturing a field effect transistor having such a structure, first, as shown in FIG. 1, an insulating substrate 1 made of ceramic, glass, etc.
A polysilicon layer 2 is patterned on the top surface. next,
As shown in FIG. 2, a gate insulating film 3 made of silicon oxide or the like is formed on the entire surface, and the polysilicon layer 2 is covered with this gate insulating film 3. Next, an aluminum film 4 for forming a gate electrode and the like is patterned on the upper surface of the gate insulating film 3 in a portion of the polysilicon layer 2 corresponding to the channel region 2a. Next, by performing ion implantation using the aluminum film 4 as a mask, source/drain regions 2b are formed in the polysilicon layer 2 on both sides of the aluminum film 4, and then activation is performed by excimer laser irradiation or the like to implant ions. Spread.

【0008】次に、図3に示すように、アルミニウム膜
4の表面を陽極酸化することにより、アルミニウム膜4
の表面に酸化アルミニウム膜5を形成すると共に、陽極
酸化されないアルミニウム膜4によってゲート電極6を
形成する。この場合、酸化アルミニウム膜5は、陽極酸
化液の選択により多孔質あるいは無孔質となり、いずれ
であってもよいが、緻密で表面荒れのない無孔質の方が
好ましい。また、印加電圧等の陽極酸化条件を選定する
ことにより、酸化アルミニウム膜5の膜厚を0.1μ程
度とすることが可能である。かくして、ポリシリコン層
2のチャネル領域2aの中央部に対応する部分のゲート
絶縁膜3の上面にチャネル領域2aよりも幅狭のゲート
電極6が形成されると共に、ゲート電極6の両側におけ
るチャネル領域2aがオフセットゲート領域2cとなる
Next, as shown in FIG. 3, the surface of the aluminum film 4 is anodic oxidized.
An aluminum oxide film 5 is formed on the surface of the aluminum film 4, and a gate electrode 6 is formed from the aluminum film 4 which is not anodized. In this case, the aluminum oxide film 5 may be porous or non-porous depending on the selection of the anodic oxidation solution, but it is preferable that it be dense and non-porous with no surface roughness. Further, by selecting the anodic oxidation conditions such as the applied voltage, it is possible to set the thickness of the aluminum oxide film 5 to about 0.1 μm. In this way, a gate electrode 6 narrower than the channel region 2a is formed on the upper surface of the gate insulating film 3 in a portion of the polysilicon layer 2 corresponding to the center of the channel region 2a, and the channel regions on both sides of the gate electrode 6 are formed. 2a becomes an offset gate region 2c.

【0009】次に、図4に示すように、全表面に窒化シ
リコン等からなる層間絶縁膜7を形成する。この場合、
酸化アルミニウム膜5は層間絶縁膜7と共に層間絶縁膜
を形成することになる。次に、層間絶縁膜7およびゲー
ト絶縁膜3をエッチングしてソース・ドレイン領域2b
と対応する部分にコンタクトホール8を形成する。次に
、コンタクトホール8を介してソース・ドレイン領域2
bと接続されるアルミニウムからなるソース・ドレイン
電極9を層間絶縁膜7の上面に形成する。かくして、オ
フセットゲート構造の電界効果型トランジスタが製造さ
れる。
Next, as shown in FIG. 4, an interlayer insulating film 7 made of silicon nitride or the like is formed on the entire surface. in this case,
The aluminum oxide film 5 forms an interlayer insulating film together with the interlayer insulating film 7. Next, the interlayer insulating film 7 and the gate insulating film 3 are etched to form the source/drain regions 2b.
A contact hole 8 is formed in a portion corresponding to . Next, the source/drain region 2 is connected through the contact hole 8.
A source/drain electrode 9 made of aluminum and connected to b is formed on the upper surface of the interlayer insulating film 7. In this way, a field effect transistor with an offset gate structure is manufactured.

【0010】このようにして製造された電界効果型トラ
ンジスタでは、ゲート電極6等を形成するためのアルミ
ニウム膜4をマスクとしてイオン注入を行っているので
、従来のようにイオン注入マスク用のフォトレジスト膜
をパターン形成した後除去する場合と比較して、製造工
程数を少なくすることができる。また、アルミニウム膜
4の表面を陽極酸化することにより、アルミニウム膜4
の表面に酸化アルミニウム膜5を形成すると共に、陽極
酸化されないアルミニウム膜4によってゲート電極6を
形成しているので、酸化アルミニウム膜5の側面がポリ
シリコン層2のチャネル領域2aとソース・ドレイン領
域2bとの境界面と対応すると共に、酸化アルミニウム
膜5の膜厚がそのままオフセットゲート領域2cの長さ
L(但し、アニールによる拡散量は考慮していない。)
となる。したがって、オフセットゲート領域2cを効率
的に形成することができ、またイオン注入後の拡散量を
配慮すれば酸化アルミニウム膜5の膜厚を制御すること
により、オフセットゲート領域2cの長さLを自動的に
制御することも可能である。さらに、酸化アルミニウム
膜5が層間絶縁膜7と共に層間絶縁膜を形成することに
なるので、層間絶縁膜が2層となり、層間ショートの低
減に寄与することができる。
In the field effect transistor manufactured in this manner, ions are implanted using the aluminum film 4 for forming the gate electrode 6 etc. as a mask. The number of manufacturing steps can be reduced compared to the case where the film is patterned and then removed. In addition, by anodizing the surface of the aluminum film 4, the aluminum film 4
Since the aluminum oxide film 5 is formed on the surface of the polysilicon layer 2 and the gate electrode 6 is formed by the aluminum film 4 which is not anodized, the side surfaces of the aluminum oxide film 5 are connected to the channel region 2a and the source/drain region 2b of the polysilicon layer 2. The length L of the offset gate region 2c corresponds to the boundary surface with the aluminum oxide film 5, and the thickness of the aluminum oxide film 5 remains unchanged (however, the amount of diffusion due to annealing is not taken into consideration).
becomes. Therefore, the offset gate region 2c can be formed efficiently, and if the amount of diffusion after ion implantation is considered, the length L of the offset gate region 2c can be automatically adjusted by controlling the thickness of the aluminum oxide film 5. It is also possible to control the Furthermore, since the aluminum oxide film 5 forms an interlayer insulating film together with the interlayer insulating film 7, there are two interlayer insulating films, which can contribute to reducing interlayer short circuits.

【0011】なお、上記実施例では、この発明を半導体
薄膜を用いたTFT(薄膜トランジスタ)に適用した場
合について説明したが、これに限定されず、単結晶半導
体基板を用いた電界効果型トランジスタスタに適用する
こともできる。また、コプラナ型のみならず、スタガ型
にも適用することができる。この場合、ゲート電極を陽
極酸化した後、イオン注入および拡散をするようにして
もよい。
[0011] In the above embodiment, the present invention is applied to a TFT (thin film transistor) using a semiconductor thin film, but the present invention is not limited to this, and can be applied to a field effect transistor star using a single crystal semiconductor substrate. It can also be applied. Moreover, it can be applied not only to the coplanar type but also to the staggered type. In this case, ion implantation and diffusion may be performed after the gate electrode is anodized.

【0012】0012

【発明の効果】以上説明したように、この発明によれば
、ゲート電極の少なくとも側面に陽極酸化膜を設けると
共に、この陽極酸化膜の側面を半導体層のチャネル領域
とソース・ドレイン領域との境界面と対応するようにし
ているので、ゲート電極の少なくとも側面に陽極酸化膜
を設ければよく、従来のようにイオン注入マスク用のフ
ォトレジスト膜をパターン形成した後除去する場合と比
較して、製造工程数を少なくすることができ、また陽極
酸化膜の膜厚をそのままオフセットゲート領域とするこ
とができ、陽極酸化膜の膜厚を制御することにより、オ
フセットゲート領域を効率的に形成することができ、ひ
いてはコストダウンを図ることができる。
As explained above, according to the present invention, an anodic oxide film is provided on at least the side surface of the gate electrode, and the side surface of the anodic oxide film is used as the boundary between the channel region and the source/drain region of the semiconductor layer. Since it is made to correspond to the surface, it is only necessary to provide an anodic oxide film on at least the side surfaces of the gate electrode, compared to the conventional case where a photoresist film for an ion implantation mask is patterned and then removed. The number of manufacturing steps can be reduced, and the thickness of the anodic oxide film can be used as is for the offset gate region, and by controlling the thickness of the anodic oxide film, the offset gate region can be efficiently formed. This can lead to cost reductions.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】この発明の一実施例における電界効果型トラン
ジスタの製造に際し、絶縁基板の上面にポリシリコン層
を形成した状態の断面図。
FIG. 1 is a cross-sectional view of a state in which a polysilicon layer is formed on the upper surface of an insulating substrate during manufacturing of a field effect transistor according to an embodiment of the present invention.

【図2】同電界効果型トランジスタの製造に際し、ゲー
ト絶縁膜およびアルミニウム膜を形成した後アルミニウ
ム膜をマスクとしてイオンを注入した状態の断面図。
FIG. 2 is a cross-sectional view of a state in which ions are implanted using the aluminum film as a mask after forming a gate insulating film and an aluminum film in manufacturing the same field effect transistor.

【図3】同電界効果型トランジスタの製造に際し、陽極
酸化により酸化アルミニウム膜およびゲート電極を形成
した状態の断面図。
FIG. 3 is a cross-sectional view of an aluminum oxide film and a gate electrode formed by anodic oxidation during manufacture of the same field-effect transistor.

【図4】同電界効果型トランジスタの製造に際し、層間
絶縁膜、コンタクトホールおよびソース・ドレイン領域
を形成した状態の断面図。
FIG. 4 is a cross-sectional view of a state in which an interlayer insulating film, contact holes, and source/drain regions are formed during manufacturing of the same field-effect transistor.

【符号の説明】[Explanation of symbols]

1  絶縁基板 2  ポリシリコン層(半導体層) 2a  チャネル領域 2b  ソース・ドレイン領域 2c  オフセットゲート領域 3  ゲート絶縁膜 4  アルミニウム膜 5  酸化アルミニウム膜(陽極酸化膜)6  ゲート
電極
1 Insulating substrate 2 Polysilicon layer (semiconductor layer) 2a Channel region 2b Source/drain region 2c Offset gate region 3 Gate insulating film 4 Aluminum film 5 Aluminum oxide film (anodized oxide film) 6 Gate electrode

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】  半導体層のチャネル長さよりもゲート
電極の長さを小さくした電界効果型トランジスタにおい
て、前記ゲート電極の少なくとも長さ方向の側面に陽極
酸化膜を設けると共に、この陽極酸化膜の側面を前記半
導体層のチャネル領域とソース・ドレイン領域との境界
面と対応するようにしたことを特徴とする電界効果型ト
ランジスタ。
1. In a field effect transistor in which the length of the gate electrode is smaller than the channel length of the semiconductor layer, an anodic oxide film is provided on at least the side surfaces of the gate electrode in the length direction, and the side surfaces of the anodic oxide film are provided with an anodic oxide film. A field effect transistor characterized in that: corresponds to an interface between a channel region and a source/drain region of the semiconductor layer.
【請求項2】  TFT構造であることを特徴とする請
求項1記載の電界効果型トランジスタ。
2. The field effect transistor according to claim 1, which has a TFT structure.
【請求項3】  前記ゲート電極はアルミニウムからな
り、前記陽極酸化膜は酸化アルミニウムからなることを
特徴とする請求項1または2記載の電界効果型トランジ
スタ。
3. The field effect transistor according to claim 1, wherein the gate electrode is made of aluminum, and the anodic oxide film is made of aluminum oxide.
【請求項4】  半導体層上にゲート絶縁膜を形成し、
前記半導体層のチャネル領域に対応する部分の前記ゲー
ト絶縁膜上にアルミニウム膜を形成し、前記アルミニウ
ム膜をマスクとしてイオン注入を行うことにより、前記
アルミニウム膜の両側における前記半導体層にソース・
ドレイン領域を形成し、前記アルミニウム膜の表面を陽
極酸化することにより、前記アルミニウム膜の表面に酸
化アルミニウム膜を形成すると共に、陽極酸化されない
前記アルミニウム膜によってゲート電極を形成すること
を特徴とする電界効果型トランジスタの製造方法。
4. Forming a gate insulating film on the semiconductor layer,
An aluminum film is formed on the gate insulating film in a portion corresponding to the channel region of the semiconductor layer, and ions are implanted using the aluminum film as a mask, thereby injecting a source into the semiconductor layer on both sides of the aluminum film.
An electric field characterized in that an aluminum oxide film is formed on the surface of the aluminum film by forming a drain region and anodizing the surface of the aluminum film, and a gate electrode is formed by the aluminum film that is not anodized. A method of manufacturing an effect type transistor.
JP16244491A 1991-06-07 1991-06-07 Field-effect transistor and manufacture thereof Pending JPH04360580A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16244491A JPH04360580A (en) 1991-06-07 1991-06-07 Field-effect transistor and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16244491A JPH04360580A (en) 1991-06-07 1991-06-07 Field-effect transistor and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH04360580A true JPH04360580A (en) 1992-12-14

Family

ID=15754733

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16244491A Pending JPH04360580A (en) 1991-06-07 1991-06-07 Field-effect transistor and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH04360580A (en)

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