KR0148292B1 - Method of junction forming of semiconductor device - Google Patents
Method of junction forming of semiconductor device Download PDFInfo
- Publication number
- KR0148292B1 KR0148292B1 KR1019940039099A KR19940039099A KR0148292B1 KR 0148292 B1 KR0148292 B1 KR 0148292B1 KR 1019940039099 A KR1019940039099 A KR 1019940039099A KR 19940039099 A KR19940039099 A KR 19940039099A KR 0148292 B1 KR0148292 B1 KR 0148292B1
- Authority
- KR
- South Korea
- Prior art keywords
- junction
- forming
- oxide film
- gate
- semiconductor device
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000001590 oxidative effect Effects 0.000 claims abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 125000006850 spacer group Chemical group 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 230000007547 defect Effects 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
본 발명은 반도체 소자의 접합 형성방법에 관한 것으로서, 특히 게이트가 형성될 영역을 산화 공정에 의해 함몰시킨 다음 종래의 접합 형성방법을 이용하여 접합을 형성함으로써 접합의 깊이를 감소시킬 수 있는 접합 형성방법에 관한 것으로서, 반도체 기판 상에 웰을 형성한 후 필드 산화막으로 소자간을 격리하고 소정의 패턴으로 산화막을 형성시키는 단계, 게이트가 형성될 영역을 열처리로 산화시키는 단계, 상기 게이트가 형성될 영역과 산화막을 식각하는 단계, 소정의 패턴으로 게이트 전극을 형성하는 단계 및 스페이서 산화막과 접합을 형성하는 단계로 이루어져서, 접합의 깊이는 얕게함과 동시에 전체적인 접합의 두께는 두꺼워져서 낮은 면 저항을 가지게 되며, 또한 고온 열처리 공정에 의해 이온주입시의 결함이 제거되어 접합 누설전류가 감소될 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a junction of a semiconductor device. In particular, a junction formation method capable of reducing the depth of a junction by recessing a region where a gate is to be formed by an oxidation process and then forming a junction using a conventional junction formation method. A method of manufacturing a semiconductor device, comprising: forming a well on a semiconductor substrate, isolating elements between the field oxide film and forming an oxide film in a predetermined pattern; oxidizing a region where a gate is to be formed by heat treatment; Etching the oxide film, forming a gate electrode in a predetermined pattern, and forming a junction with the spacer oxide film, while the depth of the junction is shallow and the thickness of the entire junction is thickened to have a low surface resistance, In addition, the high temperature heat treatment process eliminates defects during ion implantation, resulting in a junction leakage current. It can be reduced.
Description
제1도는 종래의 반도체 소자의 접합 형성방법의 각 공정을 순차적으로 설명하기 위한 단면도.1 is a cross-sectional view for sequentially explaining each step of a conventional method for forming a junction of a semiconductor element.
제2도의 (a) 내지 (f)는 본 발명에 따른 접합 형성방법의 각 공정을 순차적으로 설명하기 위한 단면도.(A)-(f) is sectional drawing for demonstrating each process of the junction formation method which concerns on this invention sequentially.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 웰1 semiconductor substrate 2 well
3 : 필드 산화막 4 : 게이트 산화막3: field oxide film 4: gate oxide film
5 : 폴리실리콘 6 : 접합5: polysilicon 6: bonding
7 : 스페이서 산화막 8 : 산화막7: spacer oxide film 8: oxide film
9 : 포토레지스트9: photoresist
본 발명은 반도체 소자의 접합 형성방법에 관한 것으로서, 특히 게이트가 형성될 영역을 산화 공정에 의해 함몰시킨 다음 종래의 접합 형성방법을 이용하여 접합을 형성함으로써 접합의 깊이를 감소시킬 수 있는 접합 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a junction of a semiconductor device. In particular, a junction formation method capable of reducing the depth of a junction by recessing a region where a gate is to be formed by an oxidation process and then forming a junction using a conventional junction formation method. It is about.
현재의 고집적 소자의 유효 채널 길이의 감소화와 더불어 소자의 수직 구조, 즉 접합 깊이의 감소 또한 필연적으로 요구되게 되었다.In addition to reducing the effective channel length of current highly integrated devices, the vertical structure of the devices, i.e., the reduction of the junction depth, is also inevitably required.
예를 들어, 모오스 소자의 채널 길이가 0.8㎛ 이하에서 구성됨에 따라 소오스, 드레인과 같은 접합영역의 깊이는 250㎚ 이하로 구성되어야 한다. 이러한 얕은 접합을 형성하기 위하여 이온 주입시 에너지를 조절하고, 어닐링 공정을 진행하고 있다.For example, as the channel length of the MOS device is configured to 0.8 μm or less, the depth of the junction region such as the source and drain should be 250 nm or less. In order to form such a shallow junction, energy is controlled during an ion implantation and an annealing process is performed.
종래에는 상기와 같은 얕은 접합을 형성하기 위하여 제1도에 도시된 바와 같이 반도체 기판(1) 상에 웰(2)을 형성한 후, 필드 산화막(3)으로 소자간을 격리하고, 상기 웰(2)에 게이트 산화막(4)을 형성한 후, 게이트 전극으로 도핑된 폴리실리콘(5)을 형성시킨다. 그 다음에 상기 폴리실리콘(5) 양측에 낮은 에너지로 이온을 주입한 후, 850℃이하의 온도에서 30∼90분 정도 열공정에 의해 접합층(6)을 형성한다. 그 다음에 상기 폴리실리콘(5)에 스페이서 산화막(7)을 형성하여 MOSFET 구조를 완성한다.Conventionally, in order to form a shallow junction as described above, as shown in FIG. 1, the wells 2 are formed on the semiconductor substrate 1, and the elements are separated by the field oxide film 3, and the wells ( After the gate oxide film 4 is formed in 2), the polysilicon 5 doped with the gate electrode is formed. Thereafter, ions are injected to both sides of the polysilicon 5 at low energy, and then the bonding layer 6 is formed by a thermal process for about 30 to 90 minutes at a temperature of 850 캜 or lower. A spacer oxide film 7 is then formed on the polysilicon 5 to complete the MOSFET structure.
그러나 이와 같은 종래의 접합 형성방법은 접합의 깊이, 즉 반도체 기판과 접합층의 기저면 사이의 거리는 작게 형성시킬 수 있으나, 대신에 면 저항, 접합 누설전류가 크게 증가하여 반도체 소자의 성능이 열화되는 문제점이 있었다.However, the conventional junction formation method can reduce the depth of the junction, that is, the distance between the semiconductor substrate and the base surface of the junction layer, but instead, the surface resistance and the junction leakage current increase greatly, thereby degrading the performance of the semiconductor device. There was this.
상기와 같은 문제점을 해결하기 위해 안출된 본 발명은, 접합의 깊이는 작게 형성시키면서 면 저항, 접합 누설전류의 증가를 억제할 수 있는 접합 형성방법을 제공하는데 목적이 있다.The present invention devised to solve the above problems is an object of the present invention to provide a method for forming a junction that can suppress the increase in surface resistance and junction leakage current while forming a small depth of junction.
상기와 같은 목적을 달성하기 위해 본 발명은, 반도체 소자의 게이트 및 소오스, 드레인 접합을 형성함에 있어서, 게이트가 형성될 기판 영역을 함몰하고 게이트 전극 및 소오스, 드레인 접합을 형성하여, 소오스 드레인 접합의 깊이는 증가시키고, 게이트 산화막과 접합부 하단까지의 실제적인 접합 깊이를 감소시킨 것을 특징으로 한다.In order to achieve the above object, the present invention, in forming the gate, source, and drain junction of a semiconductor device, by recessing the substrate region on which the gate is to be formed and forming the gate electrode, source, and drain junction, The depth is increased, and the actual junction depth to the gate oxide film and the bottom of the junction is reduced.
이하, 본 발명의 바람직한 실시예를 첨부도면에 의거하여 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제2도의 (a) 내지 (f)는 본 발명에 따른 접합 형성방법의 공정도이다.(A)-(f) of FIG. 2 is process drawing of the junction formation method which concerns on this invention.
우선, (a)에 도시된 바와 같이, 반도체 기판(1) 상부에 웰(2)을 형성한 후, 필드 산화막(3)으로 소자간을 격리하고 전체 구조의 상부에 산화막(8) 및 포토 레지스트(9)를 증착한 다음, 소정의 패턴에 따라 식각한다.First, as shown in (a), after the wells 2 are formed on the semiconductor substrate 1, the elements are separated by the field oxide film 3, and the oxide film 8 and the photoresist are formed on top of the entire structure. (9) is deposited and then etched according to a predetermined pattern.
그 후, (b)에 도시된 바와 같이, 게이트가 형성될 영역의 산화막(8)을 식각한 후, 포토 레지스트(9)를 제거한다.Thereafter, as shown in (b), after etching the oxide film 8 in the region where the gate is to be formed, the photoresist 9 is removed.
그 다음, (c)에 도시된 바와 같이, 상기 웰(2) 부분의 게이트가 형성될 영역(2a)을 고온, 열처리하여 산화시킨다.Then, as shown in (c), the region 2a in which the gate of the well 2 is to be formed is oxidized by high temperature and heat treatment.
그 후, (d)에 도시된 바와 같이, 상기 산화막(8) 및 공정에서 산화된 게이트가 형성될 영역(2a)을 식각한다.Thereafter, as shown in (d), the oxide film 8 and the region 2a in which the gate oxidized in the process are to be formed are etched.
그 다음, (e)에 도시된 바와 같이, 상기 영역(2a)에 게이트 산화막(4)과 폴리실리콘(5)을 순차적으로 증착한다.Next, as shown in (e), the gate oxide film 4 and the polysilicon 5 are sequentially deposited in the region 2a.
그리고 나서 (f)에 도시된 바와 같이, 스페이서 산화막(7)을 형성한 다음 이온을 주입하여 접합(6)을 형성시킨다. 이때, 상기 접합(6)의 두께(B)는 종래의 접합의 두께보다 두꺼워졌으나, 실제의 접합의 깊이는 반도체 기판(1)과 접합의 기저면 사이의 거리(A)이므로 상기 접합(6)의 깊이(A)는 종래보다 얕아지게 된다.Then, as shown in (f), the spacer oxide film 7 is formed and then ions are implanted to form the junction 6. At this time, the thickness B of the junction 6 is thicker than the thickness of the conventional junction, but the depth of the junction is the distance A between the semiconductor substrate 1 and the base surface of the junction, so that the junction 6 Depth A becomes shallower than before.
이와 같이 본 발명은 반도체 기판의 일부를 고온 열처리 공정으로 함몰시킨 부위에 게이트 전극을 형성하고 접합을 형성함으로써 접합의 깊이는 얕게 함과 동시에 전체적인 접합의 두께는 두꺼워져서 낮은 면 저항을 가지게 되며, 또한 고온 열처리 공정에 의해 이온주입시의 결함이 제거되어 접합 누설전류가 감소될 수 있다는 장점이 있다.As described above, the present invention forms a gate electrode at a portion in which a part of the semiconductor substrate is recessed by a high temperature heat treatment process and forms a junction, so that the depth of the junction is shallow and the overall thickness of the junction is low, resulting in low surface resistance. By the high temperature heat treatment process, the defects at the time of ion implantation are eliminated, and there is an advantage that the junction leakage current can be reduced.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940039099A KR0148292B1 (en) | 1994-12-30 | 1994-12-30 | Method of junction forming of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940039099A KR0148292B1 (en) | 1994-12-30 | 1994-12-30 | Method of junction forming of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960026440A KR960026440A (en) | 1996-07-22 |
| KR0148292B1 true KR0148292B1 (en) | 1998-12-01 |
Family
ID=19405280
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940039099A KR0148292B1 (en) | 1994-12-30 | 1994-12-30 | Method of junction forming of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0148292B1 (en) |
-
1994
- 1994-12-30 KR KR1019940039099A patent/KR0148292B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR960026440A (en) | 1996-07-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH04360580A (en) | Field-effect transistor and manufacture thereof | |
| JPH023269A (en) | Manufacture of integrated circuit | |
| US5567965A (en) | High-voltage transistor with LDD regions | |
| KR0148292B1 (en) | Method of junction forming of semiconductor device | |
| KR101099560B1 (en) | Method for manufacturing high voltage transistor | |
| KR100624961B1 (en) | Method for manufacturing transistor adopted metal gate | |
| JPH0831601B2 (en) | Method for manufacturing semiconductor device | |
| KR100244789B1 (en) | Method for manufacturing semiconductor device | |
| JPS63275179A (en) | Mis type semiconductor integrated circuit device | |
| KR19980057879A (en) | Method of manufacturing a semiconductor device having an asymmetric LDD structure | |
| KR100260366B1 (en) | Method for fabricating semiconductor device | |
| KR100325445B1 (en) | Method for forming junction in semiconductor device | |
| KR100192364B1 (en) | Method of manufacturing mosfet | |
| KR100325444B1 (en) | Method for fabricating metal oxide semiconductor transistor of low doping drain structure | |
| KR960002083B1 (en) | Making method of mosfet | |
| KR100206864B1 (en) | Moa field effect transistor and a method of fabricating the same | |
| KR100317332B1 (en) | Method for fabricating of semiconductor device | |
| KR0152936B1 (en) | Method of fabricating semiconductor device | |
| KR100247170B1 (en) | Tr fabricating method having tranch | |
| KR940010923B1 (en) | Mosfet and manufacturing method thereof | |
| JPS6016469A (en) | Manufacture of mis semiconductor device | |
| KR100506878B1 (en) | Manufacturing method of MOS field effect transistor | |
| KR100225383B1 (en) | Method of manufacturing semiconductor device | |
| KR0125296B1 (en) | Fabrication method of mosfet | |
| KR0157910B1 (en) | Method of forming mosfet having ldd structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20050422 Year of fee payment: 8 |
|
| LAPS | Lapse due to unpaid annual fee |