KR100325445B1 - Method for forming junction in semiconductor device - Google Patents
Method for forming junction in semiconductor device Download PDFInfo
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- KR100325445B1 KR100325445B1 KR1019950025351A KR19950025351A KR100325445B1 KR 100325445 B1 KR100325445 B1 KR 100325445B1 KR 1019950025351 A KR1019950025351 A KR 1019950025351A KR 19950025351 A KR19950025351 A KR 19950025351A KR 100325445 B1 KR100325445 B1 KR 100325445B1
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- forming
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- gate
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 26
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000003870 refractory metal Substances 0.000 claims abstract description 11
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 8
- 239000010936 titanium Substances 0.000 claims abstract description 8
- 150000002500 ions Chemical class 0.000 claims abstract description 4
- 238000010438 heat treatment Methods 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 238000000137 annealing Methods 0.000 abstract description 2
- 230000006911 nucleation Effects 0.000 description 5
- 238000010899 nucleation Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 소자의 접합 형성방법에 관한 것으로서, 특히 게이트가 형성될 영역을 산화 공정에 의해 함몰시킨다음, 얕은 접합 영역을 형성하고, 접합 영역상에 열안정성이 우수한 양질의 실리사이드를 구비함으로써 접촉 저항을 감소시킬 수 있는 접합 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a junction of a semiconductor device. In particular, a region in which a gate is to be formed is recessed by an oxidation process, and then a shallow junction region is formed, and a good silicide having excellent thermal stability is provided on the junction region. The present invention relates to a method for forming a junction capable of reducing resistance.
현재의 고집적 소자의 유효 채널 길이의 감소화와 더불어 소자의 수직구조, 즉 접합 영역 깊이의 감소 또한 필연적으로 요구되게 되었다.In addition to reducing the effective channel length of current highly integrated devices, the vertical structure of the device, i.e., the reduction of the junction area depth, is also inevitably required.
예를 들어, 모오스 소자의 채널 길이가 0.8㎛ 이하에서 구성됨에 따라 소오스, 드레인과 같은 접합영역의 깊이는 250nm 이하로 구성되어야 한다. 이러한 얕은 접합을 형성하기 위하여 이온 주입시 에너지를 조절하고, 어닐링 공정을 진행하고 있다. 이와 더불어, 접합 영역 형성후의 배선 공정시 접합 영역 및 게이트 전극 상부의 접촉 저항을 감소시키기 위하여 금속 실리사이드를 구비하는 공정이 진행중이다. 이러한 실리사이드막은 대체적으로 C54구조일때, 가장 작은 결정립계를 구비하여 열안정성에 우수한 특성을 갖는다.For example, as the channel length of the MOS device is configured to 0.8 μm or less, the depth of the junction region such as the source and drain should be 250 nm or less. In order to form such a shallow junction, energy is controlled during an ion implantation and an annealing process is performed. In addition, in order to reduce the contact resistance between the junction region and the gate electrode in the wiring process after forming the junction region, a process including a metal silicide is in progress. When the silicide layer has a C 54 structure, the silicide layer has the smallest grain boundary and has excellent thermal stability.
종래의 얕은 접합 형성방법 및 상기 접합 영역의 접촉 저항 감소를 위한 실리사이드 형성 방법은 첨부한 도면 제 1 도에 도시된 바와같이, 반도체 기판(1) 상에 웰(2: well)을 형성한 후, 필드 산화막(3)으로 소자간을 격리하고, 상기 웰(2)에 게이트 산화막(4)을 형성한다음, 도핑된 폴리실리콘층을 증착하고, 소정 부분을 식각하여 게이트 전극(5) 형성한다. 그런다음, 상기 게이트 전극(5) 양측에 노출된 부위에 낮은 에너지로서 불순물을 이온 주입한 후, 850℃ 이하의 온도에서 30 ∼ 90분 정도의 열 공정에 의해 상기 이온 주입된 불순물을 확산시킴으로써 접합 영역(6)을 형성한다. 그후, 상기 전제 구조상에 내화성 금속 예를들어, 티타늄 금속등을 증착시키고, 고온의 열 공정을 진행하여 게이트 전극 상부 및 접합 영역 상부에 티타늄 실리사이드막(12)을 형성하여 접합 영역 사이에 발생하는 접촉 저항을 감소시킴으로써 RC 지연 시간을 낮추는 역할을 한다.Conventional shallow junction formation method and silicide formation method for reducing contact resistance of the junction region, as shown in Figure 1 of the accompanying drawings, after forming a well (2) on the semiconductor substrate 1, Isolation between the elements is performed by the field oxide film 3, the gate oxide film 4 is formed in the well 2, the doped polysilicon layer is deposited, and a predetermined portion is etched to form the gate electrode 5. Then, after implanting impurities with low energy into the exposed portions on both sides of the gate electrode 5, the ion implanted impurities are diffused by a thermal process of about 30 to 90 minutes at a temperature of 850 ° C. or less. The region 6 is formed. Thereafter, a refractory metal such as titanium metal is deposited on the entire structure, and a high temperature thermal process is performed to form a titanium silicide film 12 on the gate electrode and the junction region to form a contact between the junction regions. Reducing the resistance serves to lower the RC delay time.
그러나, 종래와 같이 이온 주입 에너지를 감소시켜 접합 영역의 깊이를 얕게 형성하면, 얕은 접합은 구성할 수 있으나, 대신에 면 저항, 접합 누설전류가 크게 증가하여 반도체 소자의 성능이 열화되는 문제점이 있었을 뿐만 아니라, 상기 접합 영역의 접촉 저항을 감소시키기 위한 실리사이드 형성은 금속막을 증착한 후, 고온의 열공정에 의하여 형성된 실리사이드막은 핵생성 장소의 수가 부족하게 되어 결정립계의 크기가 커지게 되고, 이로 인하여, 열안정성이 퇴화되어 실리사이드를 형성하는 본연의 문제를 달성하지 못하는 문제점이 발생하였다.However, if the depth of the junction region is made shallower by reducing the ion implantation energy as in the related art, the shallow junction can be formed, but instead there is a problem that the performance of the semiconductor device deteriorates due to the large increase in the surface resistance and the junction leakage current. In addition, the silicide formation to reduce the contact resistance of the junction region is deposited after the metal film is deposited, the silicide film formed by the high temperature thermal process, the number of nucleation sites are insufficient, the grain size becomes large, thereby, There was a problem in that the thermal stability was degraded and the inherent problem of forming silicide was not achieved.
따라서, 상기와 같은 문제점을 해결하지 위해 안출된 본 발명은, 반도체 소자의 접합 영역상에 띤 저항 및 접합 누설 전류를 감소시킬 수 있는 얕은 접합 영역을 형성함과 동시에 결정립계가 조밀하여 열안정성이 우수한 양질의 실리사이드를 접합 영역 및 게이트 전극 상부에 형성시킴으로서 접촉 저항을 감소시킬 수 있는 반도체 소자의 접합 형성방법을 제공하는데 그 목적이 있다.Accordingly, the present invention devised to solve the above-described problems forms a shallow junction region capable of reducing the resistance and junction leakage current on the junction region of the semiconductor device, and at the same time has a high grain stability due to the compact grain boundary. An object of the present invention is to provide a method for forming a junction of a semiconductor device capable of reducing contact resistance by forming a high quality silicide on the junction region and the gate electrode.
상기와 같은 목적을 달성하기 위해 본 발명은, 반도체 기판의 게이트 예정 영역을 함몰시키는 단계; 상기 소정 부분이 함몰된 기판상에 게이트 전극 및 접합 영역을 형성하는 단계; 전체 구조 상부에 내화성 금속막을 형성하는 단계; 상기 내화성 금속막을 저온 열처리하여 게이트 전극 및 접합 영역 상부에 실리사이드막을 형성하는 단계; 상기 반응이 이루어지지 않은 내화성 금속막을 제거하고, 소정의원자를 이온 주입하는 단계; 상기 이온 주입이 이루어진 실리사이드를 고온 열치리 하는 단계를 포함한다.In order to achieve the above object, the present invention comprises the steps of recessing the gate predetermined region of the semiconductor substrate; Forming a gate electrode and a junction region on the substrate where the predetermined portion is recessed; Forming a refractory metal film on the entire structure; A low temperature heat treatment of the refractory metal film to form a silicide film on the gate electrode and the junction region; Removing the refractory metal film which has not been reacted, and ion implanting a predetermined atom; Heat-treating the silicide in which the ion implantation is made.
바람직하게는, 상기 게이트 기판 영역을 함몰하는 단계는 먼저, 기판상에 소정 두께의 산화막을 형성하는 단계와, 게이트 예정 영역의 산화막을 식각하여 게이트 예정 기판부를 노출시키는 단계와, 상기 노출된 기판부를 산화시키는 단계와, 기판 상부의 산화막을 제거하여 함몰 영역을 형성하는 것을 특징으로 한다.Preferably, the recessing of the gate substrate region may include forming an oxide layer having a predetermined thickness on the substrate, etching the oxide layer of the gate predetermined region to expose the gate predetermined substrate portion, and exposing the exposed substrate portion. Oxidizing and removing the oxide film on the substrate to form a recessed region.
이하, 본 발명의 바람직한 실시예를 첨부도면에 의거하여 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도면 제 2 도 (가) 내지 (바)는 본 발명의 일실시예에 따른 접합 형성방법을 나타낸 공정도이다,Figure 2 (a) to (bar) is a process chart showing a method for forming a junction according to an embodiment of the present invention,
우선, 제 2 도 (가)에 도시된 바와같이, 반도체 기판(1) 상부에 웰(2)을 형성한 후, 필드 산화막(3)으로 소자간을 격리하고 전체 구조의 상부에 산화막(8)을 소정 두께로 형성한 다음, 게이트 전극 예정 영역의 산화막(8)만이 노출되도록 포토레지스트 패턴(9)을 형성한다.First, as shown in FIG. 2A, after the wells 2 are formed on the semiconductor substrate 1, the elements are separated by the field oxide film 3, and the oxide film 8 is formed on top of the entire structure. Is formed to a predetermined thickness, and then the photoresist pattern 9 is formed so that only the oxide film 8 of the predetermined region of the gate electrode is exposed.
그런다음, 제 2 도 (나)에 도시된 바와같이, 상기 포토레지스트 패턴(9)의 형태로 하부의 산화막(8)을 식각하여 웰(2) 영역의 일정 부분을 노출시킨 다음, 상기 포토레지스트 패턴(9)을 통상의 제거 방법에 의해 제거한다.Then, as shown in FIG. 2B, the lower oxide film 8 is etched in the form of the photoresist pattern 9 to expose a portion of the well 2 region and then the photoresist. The pattern 9 is removed by a normal removal method.
그 후, 제 2 도 (다)에 도시긴 바와같이, 상기 노출된 웰(2) 영역을 고온 열처리하여 소정 깊이만큼 산화하여 부분 산화 영역(2A)을 구축한다.Thereafter, as shown in FIG. 2 (C), the exposed well 2 region is subjected to high temperature heat treatment to oxidize to a predetermined depth to form a partial oxidation region 2A.
상기와 같이 부분 산화 영역(2A)을 산화막을 제거하는 통상의 공정에 의하여 제거하면, 제 2 도 (라)에 도시된 도면과 같이, 부분 산화 영역(2A) 및 웰(2) 영역상부의 산화막(8) 또한 제거되어, 소정 부분이 함몰된 형태의 기판 구조를 얻게된다.When the partial oxide region 2A is removed by the usual process of removing the oxide film as described above, as shown in FIG. 2 (D), the oxide film on the partial oxide region 2A and the well 2 region is as shown in FIG. (8) Also removed, to obtain a substrate structure in which a predetermined portion is recessed.
그 다음, 제 2 도 (마)에 도시된 바와같이, 상기 전체 구조 상부에 게이트 산화막(4)과 도핑된 폴리실리콘(5)을 순차적으로 증착한다음, 제 2 도 (바)에 도시된 바와 같이, 함몰된 영역을 제외한 부분의 폴리실리콘 및 게이트 산화막(4)을 제거하여 게이트 전극(5)를 형성하고, 상기 게이트 전극(5)의 양측벽에 스페이서(7)를 형성한다. 그후, 통상의 모스 트랜지스터의 접합 영역을 형성하기 위한 이온 주입 에너지로, 불순물을 이온 주입하고, 열처리하여 접합 영역(6)을 형성한다. 이때, 상기 접합 영역(6)을 형성하기 위한 이온 주입 에너지는 기존의 얕은 접합을 이룩하기 위한 이온 주입 에너지 범위보다는 깊게 투사하여 얕은 접합에 의한 면저항 및 누설 전류의 증가를 억제하였고, 상기 게이트 구조가 함몰형 게이트 구조이기 때문에, 접합 영역의 깊이는 사실상 함몰된 게이트 구조의 기저면에서 접합 영역의 하단부까지의 거리 A가 실제적인 접합 영역의 깊이가 되어 면저항 및 누설 전류를 억제할 수 있는 얕은 접합을 형성한다.Then, as shown in FIG. 2 (e), the gate oxide film 4 and the doped polysilicon 5 are sequentially deposited on the entire structure, and then as shown in FIG. 2 (bar). Likewise, the gate electrode 5 is formed by removing the polysilicon and the gate oxide film 4 except the recessed region, and the spacers 7 are formed on both sidewalls of the gate electrode 5. Thereafter, impurities are ion-implanted with an ion implantation energy for forming a junction region of a normal MOS transistor, and then the junction region 6 is formed by heat treatment. At this time, the ion implantation energy for forming the junction region 6 is projected deeper than the ion implantation energy range for achieving the conventional shallow junction, thereby suppressing the increase of sheet resistance and leakage current due to the shallow junction. Because of the recessed gate structure, the depth of the junction region is substantially the distance A from the base surface of the recessed gate structure to the lower end of the junction region becomes the depth of the actual junction region to form a shallow junction that can suppress sheet resistance and leakage current. do.
그리고나서, 제 2 도 (사)에 도시된 바와 같이, 상기와 같이 형성된 얕은 접합 영역의 접촉 저항을 개선하기 위하여, 결과물 상부에 티타늄 금속층(11)을 소정 두께로 형성한다음, 저온 열처리 공정을 실시한다. 상기와 같이 저온의 열처리 공정을 진행하면, 상기 티타늄 금속층(11)은 하단의 접합 영역과 게이트 전극 상부의 폴리실리콘 부분과 반응되어 실리사이드(12)를 형성하게 되고, 그후, 상기 반응이 이루어지지 않은 티타늄 금속층을 제거한다. 그러나, 상기 저온에서 열공정만으로형성된 실리사이드는 핵생성수가 적게되어, 결국 결정립계의 크기가 커지게 된다. 따라서, 상기 저온 열처리된 실리사이드의 핵 생성수를 증가시켜 결정립게의 크기를 줄이기 위하여, 제 2 도 (아)도에 나타낸 바와 같이, 상기 실리사이드막(12) 상부에 게르마늄 또는 실리콘, 티타늄 원자등을 이온 주입하여 실리사이드막상에 인위적인 이온 주입 데미지(damage)를 형성시킨다. 상기와 같이 인위적 데미지를 형성하는 이유는 상기 데미지 부위가 핵 생성 장소를 제공하므로, 이후 열처리 공정에 의하여 조밀한 결정립계를 구비한 실리사이드막을 형성하게 된다.Then, as shown in Fig. 2 (g), in order to improve the contact resistance of the shallow junction region formed as described above, the titanium metal layer 11 is formed to a predetermined thickness on top of the resultant, and then a low temperature heat treatment process is performed. Conduct. When the low temperature heat treatment process is performed as described above, the titanium metal layer 11 reacts with the junction region at the bottom and the polysilicon portion above the gate electrode to form silicide 12, and then, the reaction is not performed. Remove the titanium metal layer. However, the silicide formed only by the thermal process at the low temperature has a low nucleation number, resulting in a large grain boundary. Therefore, in order to reduce the size of the crystal grains by increasing the nucleation number of the low-temperature heat-treated silicide, as shown in FIG. 2 (a), germanium, silicon, titanium atoms, etc. are placed on the silicide layer 12. Ion implantation forms artificial ion implantation damage on the silicide film. The reason for forming the artificial damage as described above is that the damage site provides a nucleation site, thereby forming a silicide film having a dense grain boundary by a heat treatment process.
그런다음, 제 2 도 (자)도에 도시된 바와 같이, 상기와 같이 소정의 원자가 이온 주입된 실리사이드막을 고온에서 열처리 공정을 진행하게 되면 핵생성 장소의 증가에 의하여 결정립계의 크기가 조밀한 C54구조의 열안정성이 우수한 양질의 실리사이드막을 형성하게 된다.Then, as shown in FIG. 2 (i), when the silicide film implanted with a predetermined atom is subjected to a heat treatment process at a high temperature as described above, the grain size of C 54 is dense due to the increase of nucleation sites. It is possible to form a high quality silicide film having excellent thermal stability of the structure.
이와같이 본 발명은, 반도체 기판의 일부를 고온 열처리 공정으로 함몰시킨 부위에 게이트 전극을 형성하고 접합을 형성함으로써, 접합의 깊이는 얕게 함과 동시에 전체적인 접합의 두께는 두꺼워져서, 얕은 접합시 낮으면 저항과 누설 전류를 억제할 수 있으며, 접합 영역 및 게이트 전극 상부에 결정립계의 크기가 적은 실리사이드막을 형성하므로써, 이후의 배선 공정시 접촉 저항을 개선할 수 있다.Thus, in the present invention, by forming a gate electrode and forming a junction in a portion where a part of the semiconductor substrate is recessed by a high temperature heat treatment process, the depth of the junction is shallow and the overall thickness of the junction is thick. Over leakage current can be suppressed, and by forming a silicide film having a small size of grain boundaries on the junction region and the gate electrode, the contact resistance can be improved during the subsequent wiring process.
제 1 도는 종래의 반도체 소자의 접합 형성방법 의해 형성된 반도체 소자를 개략적으로 나타낸 단면도1 is a sectional view schematically showing a semiconductor device formed by a conventional method for forming a junction of semiconductor devices.
제 2 도 (a) 내지 (i)는 본 발명에 따른 접합 형성방법의 각 공정을 순차적으로 설명하기 위한 단면도2 (a) to (i) are cross-sectional views for sequentially explaining each step of the junction forming method according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 : 반도체 기판 2 : 웰1 semiconductor substrate 2 well
2A :부분 산화 영역 3 : 필드 산화막2A: partial oxidation region 3: field oxide film
4 : 게이트 산화막 5 : 게이트 전극4 gate oxide film 5 gate electrode
6 : 접합 영역 7 : 스페이서 산화막6: junction region 7: spacer oxide film
8 : 산화막 9 : 포토레지스트 패턴8: oxide film 9: photoresist pattern
11 : 티타늄 금속막 12 : 티타늄 실리사이드11: titanium metal film 12: titanium silicide
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