JPS58212162A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To relatively simply perform an isolated region to obtain a semiconductor device in which a circuit function element is formed in the isolated region by providing the isolated region having less crystal defects on the prescribed surface of a semiconductor substrate which has many crystal defects. CONSTITUTION:An oxygen precipitated uncleus region 1-D is transformed by heat treating in an oxygen gas into a crystal defect region 1-A, and the region 1-D becomes a no-defect region 1-B as it is. An oxidized silicon film 18 is formed on the part which is not covered with a nitrided silicon film 17 on a silicon substrate. Stepwise shape is formed at the grown part and the part in which oxidized silicon is masked with the film 17, and a photomask used in the later manufacturing steps is positioned with the stepwise shape as a reference. A memory cell 6 and an MOS transistor 10 as circuit active element are respectively formed in the region 1-B, minority carried generated in the drain region 9 is effectively recombined and removed in the matrix region of a defect layer 1-A, and does not reach the isolated region of the memory cell 6 at all.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device capable of ultra-high density and a method for manufacturing the same.

In a memory that is used as a single functional element in a very highly integrated circuit device (VLSI), the memory cell area and the functional elements of its peripheral circuits are extremely close to each other, and the amount of data stored in the same memory cell increases. For example, since the amount of charge caused by the
When a transistor is operated in the saturation region, minority carriers are generated from its drain region due to impact ionization, and these carriers diffuse to reach the memory cell region, causing abnormal operation in which the memory state changes. . Since this appears as a memory malfunction, measures to prevent this malfunction are one of the important issues for VLSI memory devices. Conventionally, the memory device shown in the cross-sectional view of FIG. 1 is known as a semiconductor device that has taken measures to prevent such malfunction. It is being This device consists of a p-type silicon substrate 1
A crystal defect region 1-A is built in a layered manner inside the substrate 1, the surface portion of the substrate 1 is separated by a local oxidation film (LOGO3 film) 2, and a first polycrystalline gate layer 3. A memory capacitor (memory cell) 6 having a source region consisting of a second polycrystalline gate layer 4 and an n+ type scattering layer 5 is formed.
At the same time, a polycrystalline gate layer 7 is formed on the other surface region.
．． A MOS transistor 10 having a source region and a drain region made of an n+ type scattering layer 89 is formed. Note that the shallowest part of this device is made of phosphosilicate glass (PS).
G) A second gate electrode 12 and a source electrode 13 made of an aluminum film connected to a protective layer 11 made of a film and an external electrode wiring layer. The drain electrode 14 is provided by a well-known formation method, and the presence of a thin gate insulating film and a thin gate interlayer insulating film under each gate layer is also a common method for forming cells or MOS transistors. It's the same as that evening. In this device, the minority carriers generated in the surface region on the MO3) transistor 10 side are transferred to the crystal defect region below. The aim is to eliminate it with A, but in the current situation where it is difficult to control the thickness of the surface layer portion 1-B, for example, if the thickness becomes 10 μm or more, the effect will be incomplete, and the above MO8) The carriers generated on the run raster 1o side diffused and reached the memory cell 6 region as shown by the arrow in FIG. 9, and the malfunction caused by this could not be completely eliminated.

Furthermore, as shown in the cross-sectional view of FIG. 2, in addition to the structure shown in the first diagram, an isolation region of a p+ type scattering layer 15 is provided between the memory cell 6 and the MOS transistor o, thereby eliminating unnecessary Prevention of carrier diffusion has also been implemented, but in this case, what is the above? 1 type diffusion layer 16
The effect cannot be fully obtained unless the depth is about 0 μm, and in VLSI technology, which is based on forming active elements with a shallow diffusion layer, such a deep diffusion process is a bottleneck in manufacturing. . In FIG. 2, the same numbers as in FIG. 1 indicate the same parts.

An object of the present invention is to solve the above-mentioned problem J in the conventional device.Firstly, an isolation region with few crystal defects is provided in a predetermined surface portion of a semiconductor substrate having a large number of crystal defects, and a separation region within the isolation region is provided. Second, to provide a useful manufacturing method that can relatively easily realize the region having a large amount of crystal defects and the separation region having few crystal defects. It is in.

The semiconductor device of the present invention has a crystal defect layer 1-A having a large amount of crystal defects on the surface of a p-type silicon substrate 1, and a crystal defect layer 1-A having a large amount of crystal defects on the surface of a p-type silicon substrate 1, as shown in the main part cross-sectional view of FIG. An isolation region 1-B with few crystal defects is provided at a predetermined portion in the layer 1, and a memory cell 6 and a MOS transistor 10 as circuit active elements are provided in the isolation region 1-B, respectively.
- It is built into B. Note that each structure reference numeral in FIG. 3 represents a structure corresponding to that of the semiconductor device shown in FIGS. 1 and 2 above.

That is, according to the semiconductor device of the present invention, both circuit active elements disposed close to each other, for example, the memory cell 6 and the MO transistor 10, are located in the crystal defect layer. Since it exists in the separation region 1-B completely surrounded by the matrix region of A, the MO8I
- The minority carriers generated in the drain region 9 of the transistor 10 are also surely recombined and annihilated in the matrix region of the defect layer 1-A, so that they do not reach the isolation region of the adjacent memory cell 6 at all, and therefore , the disadvantage of impairing the characteristics of the memory cell 6 is completely eliminated.

The structure of the embodiment shown in FIG. 3 is a typical example showing the structure of the main parts of the memory cell part of the dynamic RAM and the MOS transistor part of the peripheral circuit.
The details will be described in detail with reference to the manufacturing process diagram of the dynamic RAM shown in the figure.

For example, on a p-type silicon substrate 1-C with a carbon concentration of 3×16 cm + oxygen concentration of 10×18 cm, a silicon oxide film 16 to a thickness of 500 mm is grown by heat treatment in oxygen. A silicon nitride film 17 is deposited on the film 16 to a thickness of 1000. Next, using a photoresist mask, the silicon nitride film 17 and the silicon oxide film 16 are etched to form openings in a predetermined shape [FIG. 3(a)].

Thereafter, heat treatment is performed at 1100° C. for 4 hours in an argon-oxygen mixed gas with an oxygen concentration of 01. At this time, the oxygen contained in the silicon substrate 1-C is diffused outward from the opening of the film, so that the inside of the silicon substrate 1-C and the portion covered with the silicon nitride film 17 are exposed to the initial oxygen. The oxygen concentration is maintained, but the rest of the area near the surface of the silicon substrate 1-C becomes a low oxygen concentration region 1-B [Figure 3(b)]
Subsequently, heat treatment is performed at 700° C. for 16 hours in oxygen gas. At this time, there is no precipitation of oxygen in the low oxygen concentration region 1-B because the oxygen concentration is low, but in the high oxygen concentration region 1-C
Then, oxygen precipitate nuclei are generated [Figure 3 (C)]. Furthermore, by applying heat treatment at 1000°C for 6 hours in oxygen gas, the previously generated oxygen precipitates grow into crystal defects. Oxygen precipitation nucleus region 1-D is crystal defect region 1-A
Defect-free region 1-
It becomes B. By this heat treatment, about 4,000 silicon oxide films 18 grow on the parts of the silicon substrate not covered with the silicon nitride film 17, that is, the exposed parts of the substrate [FIG. 3(d)]. After this, the silicon nitride coating 17
is etched with phosphoric acid at 150° C., and the silicon oxide film 16.1B is further removed with a hydrofluoric acid aqueous solution. At this time, on the main surface of the silicon substrate, a step shape is generated at the part where the silicon oxide film 18 was grown in the previous step and the part where silicon oxidation was masked by the silicon nitride film 17 [FIG. 3(e)]. A photomask used in a subsequent manufacturing process is aligned based on this step shape. The subsequent manufacturing process is similar to that of a normal dynamic RAM.

LOCO8 membrane 2. Gate oxide film 19. First polysilicon gate layer 3. First interlayer insulating film 20. Second polycrystalline silicon gate layer 4. The source diffusion layer 6 of the memory cell section and the source of the MOS) run sister.

Drain and diffusion layers 8 and 9 are sequentially formed [Fig. 3(f)]
]0 Furthermore, after implanting the PSG film 11, a contact window is opened and a PSG flow is performed to form electrode layers 12, 13, and 14 of aluminum film to complete the process (Fig. 3).
.

In the case of this example, the distance between the drain of the MOS transistor 10 and the capacitor of the memory cell 6 was 70 μm, and when the drain voltage was set to 6 V, the charge retention time of the memory cell was 40 seconds. 0 In the case of the structure shown in FIG. 1 manufactured by the conventional method, the charge retention time was 26 seconds when measured under the same conditions, and it is clear that the structure using this example has a longer charge retention time in the memory cell. It's a long time.

In this example, MOS) Runsister 10
Since the crystal defects contained in the crystal defect region completely surrounding the crystal defect region become carrier recombination centers, all the minority carriers generated by the innocent ionization phenomenon in the MOS) run sister 1o pass through this crystal defect region. It is observed that the light disappears due to recombination and does not reach neighboring memory cells.

As described above, according to the present invention, memory malfunctions due to impact ionization in peripheral transistors can be prevented. Furthermore, since the crystal defects surround the MOS (MOS) run sister, efficient gettering is possible against the intrusion of contaminants such as heavy metals that may occur during the device process. If the area is surrounded by this crystal defect region, it is expected that memory malfunctions caused by alpha rays will also be improved. Incidentally, in the embodiment of the present invention, the crystal defect region surrounding the MOS (MOS) run sister was formed by precipitation of oxygen contained in the silicon substrate, but the same effect can be obtained by using crystal defects formed by ion implantation such as Ar+ ions. You can get the following effect.

Although the present invention has been described by exemplifying the structure of a dynamic RAM and its manufacturing method, the present invention can also be applied to COD image sensors, OMO3, and other semiconductor devices.

[Brief explanation of the drawing]

1 and 2 are structural sectional views of main parts of a conventional semiconductor device (RAM), and FIG. 3 is a semiconductor device (RA) according to an embodiment of the present invention.
FIGS. 4(a) to 4(f) are sectional views of main parts of M) and sectional views of manufacturing steps according to an embodiment of the present invention. 1...Silicon substrate (p type), 1-Ao...
・Crystal defect region, 1-B...Defect-free region, 1-
C...High oxygen concentration area? D...Oxygen precipitation nucleus region, 20...LOCO8 film, 6...
・N tens of scattered layers, 11@…-PSG film, 15116111
11111 p raw mineral dispersion layer, 600000. Memory Senope 10---MO3 transistor. Name of agent: Patent attorney Toshio Nakao (1st person)
Figure 3 Figure 4 (C) Figure 4

Claims (4)

[Claims] (1) A semiconductor device characterized in that an isolation island region with few crystal defects is provided on a predetermined surface portion of a semiconductor substrate having a large amount of crystal defects, and a circuit active element is configured in the isolation island region. (2) The semiconductor device according to claim 1, wherein a large amount of crystal defects are crystal defects generated from oxygen precipitation nuclei. (3) The semiconductor device according to claim 1, wherein a large number of crystal defects are crystal defects formed by argon ion implantation. (4) After forming an inert film on the surface of a semiconductor substrate containing oxygen, selecting a predetermined opening in the inert film and heat-treating the semiconductor substrate to eliminate oxygen in the semiconductor substrate. A method for manufacturing a semiconductor device, comprising the steps of: extracting oxygen precipitate nuclei from an opening by outward diffusion; and generating crystal defects from the oxygen precipitate nuclei by heat treating the semiconductor substrate.