JPS5661139A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5661139A
JPS5661139A JP13805579A JP13805579A JPS5661139A JP S5661139 A JPS5661139 A JP S5661139A JP 13805579 A JP13805579 A JP 13805579A JP 13805579 A JP13805579 A JP 13805579A JP S5661139 A JPS5661139 A JP S5661139A
Authority
JP
Japan
Prior art keywords
mask
well
sio2
type
matching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13805579A
Other languages
Japanese (ja)
Other versions
JPS6315744B2 (en
Inventor
Toshihiko Mano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP13805579A priority Critical patent/JPS5661139A/en
Publication of JPS5661139A publication Critical patent/JPS5661139A/en
Publication of JPS6315744B2 publication Critical patent/JPS6315744B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

Abstract

PURPOSE:To attempt the high integration of elements by forming a P type stopper in a P type well by self-matching for self matching P type and N type wells. CONSTITUTION:SiO2 14 and Si3N4 15 are placed on an Si substrate 13 for opening. An N well 17 is made by applying a resist mask 16 on the Si3N4 15 and by ion implantation. The mask 16 is removed and SiO2 18 is made by performing selective oxidation by the mask 15. The mask 15 is eliminated and the removal of etching is applied to the SiO2 14 to leave SiO2 19. A P well 20 is made by ion implantation by the mask 19. The P well 20 is covered with SiO2 21 and a resist mask 22 is applied to the P well 20 to make a P type stopper 24 by selectively opening. In this composition, the P stopper will be formed by self-matching in addition to self matching P and N wells. So, the provision of mask alignment margin is unnecessary. Therefore, well area will be reduced by about 30 percent.
JP13805579A 1979-10-25 1979-10-25 Manufacture of semiconductor device Granted JPS5661139A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13805579A JPS5661139A (en) 1979-10-25 1979-10-25 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13805579A JPS5661139A (en) 1979-10-25 1979-10-25 Manufacture of semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP644889A Division JPH01230247A (en) 1989-01-13 1989-01-13 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5661139A true JPS5661139A (en) 1981-05-26
JPS6315744B2 JPS6315744B2 (en) 1988-04-06

Family

ID=15212921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13805579A Granted JPS5661139A (en) 1979-10-25 1979-10-25 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5661139A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56118366A (en) * 1980-02-22 1981-09-17 Hitachi Ltd Preparation of semiconductor device
US5019526A (en) * 1988-09-26 1991-05-28 Nippondenso Co., Ltd. Method of manufacturing a semiconductor device having a plurality of elements
US5132241A (en) * 1991-04-15 1992-07-21 Industrial Technology Research Institute Method of manufacturing minimum counterdoping in twin well process
US5219768A (en) * 1989-05-10 1993-06-15 Oki Electric Industry Co., Ltd. Method for fabricating a semiconductor device
US5350491A (en) * 1992-09-18 1994-09-27 Advanced Micro Devices, Inc. Oxide removal method for improvement of subsequently grown oxides for a twin-tub CMOS process

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4979189A (en) * 1972-11-01 1974-07-31
JPS51113476A (en) * 1975-03-31 1976-10-06 Fujitsu Ltd Semiconductor device manufacturing system
JPS5292489A (en) * 1976-01-30 1977-08-03 Hitachi Ltd Manufacture of c-mis semiconductor
JPS52119085A (en) * 1976-03-10 1977-10-06 Nec Corp Semiconductor memory element
JPS5323557A (en) * 1976-08-18 1978-03-04 Hitachi Ltd Electronic lens
JPS5485976U (en) * 1977-11-30 1979-06-18

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4979189A (en) * 1972-11-01 1974-07-31
JPS51113476A (en) * 1975-03-31 1976-10-06 Fujitsu Ltd Semiconductor device manufacturing system
JPS5292489A (en) * 1976-01-30 1977-08-03 Hitachi Ltd Manufacture of c-mis semiconductor
JPS52119085A (en) * 1976-03-10 1977-10-06 Nec Corp Semiconductor memory element
JPS5323557A (en) * 1976-08-18 1978-03-04 Hitachi Ltd Electronic lens
JPS5485976U (en) * 1977-11-30 1979-06-18

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56118366A (en) * 1980-02-22 1981-09-17 Hitachi Ltd Preparation of semiconductor device
JPS6360549B2 (en) * 1980-02-22 1988-11-24
US5019526A (en) * 1988-09-26 1991-05-28 Nippondenso Co., Ltd. Method of manufacturing a semiconductor device having a plurality of elements
US5219768A (en) * 1989-05-10 1993-06-15 Oki Electric Industry Co., Ltd. Method for fabricating a semiconductor device
US5132241A (en) * 1991-04-15 1992-07-21 Industrial Technology Research Institute Method of manufacturing minimum counterdoping in twin well process
US5350491A (en) * 1992-09-18 1994-09-27 Advanced Micro Devices, Inc. Oxide removal method for improvement of subsequently grown oxides for a twin-tub CMOS process

Also Published As

Publication number Publication date
JPS6315744B2 (en) 1988-04-06

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