JPS6465876A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6465876A
JPS6465876A JP22208787A JP22208787A JPS6465876A JP S6465876 A JPS6465876 A JP S6465876A JP 22208787 A JP22208787 A JP 22208787A JP 22208787 A JP22208787 A JP 22208787A JP S6465876 A JPS6465876 A JP S6465876A
Authority
JP
Japan
Prior art keywords
layer
opening
etching
insulating layer
manufacture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22208787A
Other languages
Japanese (ja)
Inventor
Takehiro Takayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP22208787A priority Critical patent/JPS6465876A/en
Publication of JPS6465876A publication Critical patent/JPS6465876A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To manufacture a MES-FET easily which is provided with a gate small in length by a method wherein a first insulating layer is subjected to etching through an opening of a resist layer, and a second insulating layer is formed on the exposed face. CONSTITUTION:An opening 5 is provided to a resist layer 3 laminated on a SiO2 layer 2 of a first insulating layer on a GaAs substrate 1, and the layer 2 is removed by etching using the layer 3 as a mask. Next, a SiO2 layer 6 of a second insulating layer is formed on the exposed face, the layer 6 is removed through a dry etching performed from the top, and then a metal layer 7 of Ti-Pt-Au is evaporated. Then, the unremoved part of the layer 6 is removed through a wet etching and the layer 7 on the layer 3 is removed through a lift-off, so that a gate electrode 7a corresponding to the size of the opening 5 is formed, and thus a MES-FET with a gate small in length can be easily manufactured.
JP22208787A 1987-09-07 1987-09-07 Manufacture of semiconductor device Pending JPS6465876A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22208787A JPS6465876A (en) 1987-09-07 1987-09-07 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22208787A JPS6465876A (en) 1987-09-07 1987-09-07 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6465876A true JPS6465876A (en) 1989-03-13

Family

ID=16776923

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22208787A Pending JPS6465876A (en) 1987-09-07 1987-09-07 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6465876A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4981809A (en) * 1987-08-10 1991-01-01 Sumitomo Electric Industries, Ltd. Method of forming a mask pattern for the production of transistor
US6890447B2 (en) 2001-08-03 2005-05-10 Yamaha Corporation Method of forming noble metal thin film pattern

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4981809A (en) * 1987-08-10 1991-01-01 Sumitomo Electric Industries, Ltd. Method of forming a mask pattern for the production of transistor
US6890447B2 (en) 2001-08-03 2005-05-10 Yamaha Corporation Method of forming noble metal thin film pattern
KR100490575B1 (en) * 2001-08-03 2005-05-17 야마하 가부시키가이샤 Method of forming noble metal thin film pattern

Similar Documents

Publication Publication Date Title
JPS6451665A (en) Semiconductor device
JPS6465876A (en) Manufacture of semiconductor device
JPS57103364A (en) Preparation of field-effect trasistor
JPS5669843A (en) Manufacture of semiconductor device
JPS57145340A (en) Manufacture of semiconductor device
JPS5661139A (en) Manufacture of semiconductor device
JPS6472567A (en) Manufacture of semiconductor device
JPS6424466A (en) Manufacture of semiconductor device
JPS56111264A (en) Manufacture of semiconductor device
JPS57176767A (en) Manufacture of semiconductor device
JPS5534492A (en) Semiconductor integrated circuit device having mis field effect type transistor and its manufacture
JPS5372474A (en) Manufacture for field effect transistor
JPS5370769A (en) Production of semiconductor device
JPS559415A (en) Semiconductor manufacturing method
JPS6459963A (en) Manufacture of field-effect transistor
JPS57188883A (en) Formation of recess-type micro-multilayer gate electrode
JPS5291382A (en) Insulating gate type field effect transistor
JPS6420624A (en) Manufacture of semiconductor device
JPS5648150A (en) Manufacture of semiconductor device
JPS56104450A (en) Manufacture of semiconductor device
JPS57124443A (en) Forming method for electrode layer
JPS57106124A (en) Wiring electrode
JPS5683972A (en) Manufacture of semiconductor device
JPS56167331A (en) Manufacture of semiconductor device
KR940010203A (en) Method for forming contact hole inclined surface in semiconductor device