JPS5587482A - Mis type semiconductor device - Google Patents

Mis type semiconductor device

Info

Publication number
JPS5587482A
JPS5587482A JP16264378A JP16264378A JPS5587482A JP S5587482 A JPS5587482 A JP S5587482A JP 16264378 A JP16264378 A JP 16264378A JP 16264378 A JP16264378 A JP 16264378A JP S5587482 A JPS5587482 A JP S5587482A
Authority
JP
Japan
Prior art keywords
film
layers
window
produced
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16264378A
Other languages
Japanese (ja)
Inventor
Hideki Oka
Koichi Nishiuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16264378A priority Critical patent/JPS5587482A/en
Publication of JPS5587482A publication Critical patent/JPS5587482A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To accomplish a shorter channel by increasing the space of the source and drain layers facing each other along with depth.
CONSTITUTION: A p+-channel cut is provided on the p-type Si substrate 30 beforehand. A window 31a is eteched on the SiO2 film 31. n+-layer 32 is produced by slant ion implantation and similarly an n+-layer 33 produced. Then these layers are annealed. Subsequently, the film 31 is removed from the gate region to form a gate oxide film 34 where a gate electrode 35 is formed so as no to overlap the layers 32 and 33. With the electrode 35 as mask, the film 34 is removed, and covered with PSG36, a window is selectively etched to make a wiring pattern 37. With such an arrangement, improved punch through dielectric strength allows application of a high voltage to the source and drain thereby accomplishing shorter channel. In addition, less parastic capacitance enables a high speed action.
COPYRIGHT: (C)1980,JPO&Japio
JP16264378A 1978-12-25 1978-12-25 Mis type semiconductor device Pending JPS5587482A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16264378A JPS5587482A (en) 1978-12-25 1978-12-25 Mis type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16264378A JPS5587482A (en) 1978-12-25 1978-12-25 Mis type semiconductor device

Publications (1)

Publication Number Publication Date
JPS5587482A true JPS5587482A (en) 1980-07-02

Family

ID=15758512

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16264378A Pending JPS5587482A (en) 1978-12-25 1978-12-25 Mis type semiconductor device

Country Status (1)

Country Link
JP (1) JPS5587482A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08204189A (en) * 1995-01-30 1996-08-09 Rohm Co Ltd Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08204189A (en) * 1995-01-30 1996-08-09 Rohm Co Ltd Manufacture of semiconductor device

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