JPS57128067A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS57128067A JPS57128067A JP13181381A JP13181381A JPS57128067A JP S57128067 A JPS57128067 A JP S57128067A JP 13181381 A JP13181381 A JP 13181381A JP 13181381 A JP13181381 A JP 13181381A JP S57128067 A JPS57128067 A JP S57128067A
- Authority
- JP
- Japan
- Prior art keywords
- film
- source
- region
- drain
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 238000000137 annealing Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
PURPOSE:To obtain the FET with a shallow source and drain region for the subject semiconductor device by a method wherein the source and drain region which constitutes an IGFET is formed by performing an ion implantation using a mask with a hole in such a manner that said region is deeply formed at the hole part and shallowly formed at the section surrounding the hole part. CONSTITUTION:An SiO2 film 2 is coated on an N type Si substrate 1, the part 3 corresponding to a source, a drain and a gate regions are removed by performing an etching, and a thin SiO2 film 5 is coated between the remaining film 2. Then, two holes 6 are bored corresponding to the source and drain regions which are positioned between said regions, and a short photoresist film 4 is formed. Subsequently, a P type impurity ion is implanted in such a manner that the ion implanted region is deeply formed at the hole 6 section and shallowly at the section where the ion is penetrating the film 5 using the film 4 as a mask. Then, a part of the bottom face is protruted into the substrate 1 and a shallow P type source region 7 and a drain region 8 are formed by performing an anneal ing in N2 gas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13181381A JPS57128067A (en) | 1981-08-21 | 1981-08-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13181381A JPS57128067A (en) | 1981-08-21 | 1981-08-21 | Manufacture of semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9594874A Division JPS5124185A (en) | 1974-08-21 | 1974-08-21 | HANDOTA ISOCHI |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57128067A true JPS57128067A (en) | 1982-08-09 |
Family
ID=15066702
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13181381A Pending JPS57128067A (en) | 1981-08-21 | 1981-08-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57128067A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5120668A (en) * | 1991-07-10 | 1992-06-09 | Ibm Corporation | Method of forming an inverse T-gate FET transistor |
| US5292676A (en) * | 1992-07-29 | 1994-03-08 | Micron Semiconductor, Inc. | Self-aligned low resistance buried contact process |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4827506A (en) * | 1971-08-19 | 1973-04-11 |
-
1981
- 1981-08-21 JP JP13181381A patent/JPS57128067A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4827506A (en) * | 1971-08-19 | 1973-04-11 |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5120668A (en) * | 1991-07-10 | 1992-06-09 | Ibm Corporation | Method of forming an inverse T-gate FET transistor |
| US5292676A (en) * | 1992-07-29 | 1994-03-08 | Micron Semiconductor, Inc. | Self-aligned low resistance buried contact process |
| USRE36735E (en) * | 1992-07-29 | 2000-06-13 | Micron Technology Inc. | Self-aligned low resistance buried contact process |
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