USRE36735E - Self-aligned low resistance buried contact process - Google Patents

Self-aligned low resistance buried contact process Download PDF

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Publication number
USRE36735E
USRE36735E US08/613,189 US61318996A USRE36735E US RE36735 E USRE36735 E US RE36735E US 61318996 A US61318996 A US 61318996A US RE36735 E USRE36735 E US RE36735E
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layer
window
buried contact
implanting
substrate
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US08/613,189
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Monte Manning
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Micron Technology Inc
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Micron Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/103—Mask, dual function, e.g. diffusion and oxidation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special

Definitions

  • This invention relates to semi-conductor integrated circuits, and more specifically to the creation of reliable buried contacts between a transistor element and a remote diffusion area.
  • the invention has particular applicability to the fabrication of integrated memory circuits.
  • Buried contacts are used in the fabrication of integrated circuits in order to establish current pathways through the underlying substrate rather than on the top surface of the circuit. Buried contacts ensure electrical isolation from other parts of the circuit, and leave the top surface free for use in establishing other connections and outside contacts giving access to the circuit.
  • a buried contact is used to link the gate of one transistor to the drain of another in a paired transistor memory cell, as explained in U.S. Pat. No. 5,064,776 Roberts.
  • DRAMs Dynamic Random Access Memories
  • a buried contact must retain a low resistive path minimal current leakage to other parts of the circuit, and reduce the volume.
  • Buried contacts are typically created by diffusion or implantation of ions in the upper region of the circuit substrate through an opening in an insulating silicon oxide layer laid over the upper surface of the substrate.
  • the diffusion or implantation of the buried contact must extend beyond the periphery of the window open near or under a gate or storage capacitor structure in order to reach the source or drain region to which the gate or capacitor must be connected. Insufficient diffusion or implantation leaving too large a spacing between the edge of the buried contact and the outer edge of the polysilicon defining the source or drain may result in the creation of a parasitic MOS device having a relatively high threshold voltage (Vt) between the buried contact and the remote source or drain location. This parasitic MOS device may increase the buried contact resistance and degrade the circuit performance.
  • Vt threshold voltage
  • the diffusion of the buried contact into the substrate is usually controlled by the size of the window, the type and duration of the diffusion or implantation process, and the judicious selection of doping elements.
  • the principal and secondary objects of this invention are to provide a reliable technique for diffusing buried contacts through a relatively small window while avoiding the formation of parasitic MOS devices between the buried contact and the remote source or drain diffusion area; and to do so with a limited number of masking steps.
  • FIG. 1 is a cross-sectional view of the initial layer deposition process
  • FIG. 2 is a cross-sectional view of the buried contact window etching
  • FIG. 3 is a cross-sectional view of the buried contact window enlargement, and implantation processes.
  • FIG. 4 is a cross-sectional view of the polysilicon layering
  • FIG. 5 is a cross-sectional view of the final buried contact structure.
  • FIG. 1 illustrates a section 11 of an integrated circuit including the end section 12 of a dogbone-shaped wafer formed by a lateral bulge in the silicon oxide layer 13 grown over a P-doped substrate 14.
  • the end section 12 is to be used in forming a storage capacitor to be linked by a buried contact to a remote N+diffused area associated with the source or drain of a controlling transistor.
  • a thin first layer 15 of polysilicon may first be deposited over the insulating oxide layer 13. The wafer is then covered with a photoresist 16. The photoresist is exposed through a mask, then developed to create a void 17 over the area where the buried contact is to be formed.
  • the void is used to etch a window 18 through the thin polysilicon layer 15 and the oxide layer 13.
  • the periphery of the void 17 in the photoresist 16 is descumed or cut back to expose a peripheral margin 19 of polysilicon around the window 18 as illustrated in FIG. 3.
  • Phosphorous or arsenic is then implanted as indicated by the arrows 20 by a punch-through implant process or other appropriate technique creating a N+doped zone 21 that extends under the entire descumed width of the photoresist.
  • a second layer 22 of polysilicon is deposited then doped and patterned to create the storage capacitor plate, and the source, gate and drain of the transistor.
  • FIG. 5 illustrates the buried contact 23 after its diffusion and the diffusion 24 of the transistor source or drain area.
  • any parasitic MOS device which may have been created between the buried contact 23 and the source or drain zone 24 is bridged by the peripheral area 26 of the phosphorous or arsenic implant. This extension of the implant greatly reduces the threshold voltage of the parasitic MOS device. Typically, a 0.2 micrometer etch back of the photoresist around the buried contact opening will be adequate in order to create a low threshold MOS device zone bridging arsenic-doped diffusions of the buried contact and source/drain structure.
  • the window enlargement process may be used without depositing the first layer 15 of polysilicon.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

A buried contact is formed in a substrate implantation of phosphorous or arsenic through a window cut into the insulating silicon oxide layer and a superimposed thin silicon layer. The photoresist used to etch the window is cut back a limited amount prior to implantation. The peripheral margin of the buried contact implanted through the exposed part of the thin layer of silicon lowers the threshold voltage of any parasitic MOS device which may be created between the buried contact and the remote N+source or drain structure.

Description

FIELD OF THE INVENTION
This invention relates to semi-conductor integrated circuits, and more specifically to the creation of reliable buried contacts between a transistor element and a remote diffusion area. The invention has particular applicability to the fabrication of integrated memory circuits.
BACKGROUND OF THE INVENTION
Buried contacts are used in the fabrication of integrated circuits in order to establish current pathways through the underlying substrate rather than on the top surface of the circuit. Buried contacts ensure electrical isolation from other parts of the circuit, and leave the top surface free for use in establishing other connections and outside contacts giving access to the circuit.
For instance, in the fabrication of Static Random Access Memories (SRAMs), a buried contact is used to link the gate of one transistor to the drain of another in a paired transistor memory cell, as explained in U.S. Pat. No. 5,064,776 Roberts.
In the fabrication of Dynamic Random Access Memories (DRAMs), a buried contact is used between a storage capacitor and the source or drain of its controlling transistor.
Integrated circuit designers are forever trying to improve the conductive quality of buried contacts under the constraint of ever-increasing circuit complexity and demand for miniaturization.
A buried contact must retain a low resistive path minimal current leakage to other parts of the circuit, and reduce the volume.
Buried contacts are typically created by diffusion or implantation of ions in the upper region of the circuit substrate through an opening in an insulating silicon oxide layer laid over the upper surface of the substrate.
The diffusion or implantation of the buried contact must extend beyond the periphery of the window open near or under a gate or storage capacitor structure in order to reach the source or drain region to which the gate or capacitor must be connected. Insufficient diffusion or implantation leaving too large a spacing between the edge of the buried contact and the outer edge of the polysilicon defining the source or drain may result in the creation of a parasitic MOS device having a relatively high threshold voltage (Vt) between the buried contact and the remote source or drain location. This parasitic MOS device may increase the buried contact resistance and degrade the circuit performance. The diffusion of the buried contact into the substrate is usually controlled by the size of the window, the type and duration of the diffusion or implantation process, and the judicious selection of doping elements.
Various techniques based on successive diffusion or punch-through implantations which have been used in the past require multiple masking steps which increase the fabrication complexity, processing time and cost.
SUMMARY OF THE INVENTION
The principal and secondary objects of this invention are to provide a reliable technique for diffusing buried contacts through a relatively small window while avoiding the formation of parasitic MOS devices between the buried contact and the remote source or drain diffusion area; and to do so with a limited number of masking steps.
These and other objects are achieved by the buried contact by the creation of phosphorous or arsenic implantation through a relatively narrow window cut in the insulating silicon oxide layer and a thin layer of silicon laid over it. The edge of the photoresist used to etch the window are descumed back a small amount in order to allow implantation of a marginal zone through the exposed section of the silicon layer.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 is a cross-sectional view of the initial layer deposition process;
FIG. 2 is a cross-sectional view of the buried contact window etching;
FIG. 3 is a cross-sectional view of the buried contact window enlargement, and implantation processes; and
FIG. 4 is a cross-sectional view of the polysilicon layering; and
FIG. 5 is a cross-sectional view of the final buried contact structure.
DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION
Referring now to the drawing, the invention will be described in connection with the fabrication of a DRAM die.
FIG. 1 illustrates a section 11 of an integrated circuit including the end section 12 of a dogbone-shaped wafer formed by a lateral bulge in the silicon oxide layer 13 grown over a P-doped substrate 14. The end section 12 is to be used in forming a storage capacitor to be linked by a buried contact to a remote N+diffused area associated with the source or drain of a controlling transistor. A thin first layer 15 of polysilicon may first be deposited over the insulating oxide layer 13. The wafer is then covered with a photoresist 16. The photoresist is exposed through a mask, then developed to create a void 17 over the area where the buried contact is to be formed.
As shown in FIG. 2, the void is used to etch a window 18 through the thin polysilicon layer 15 and the oxide layer 13. The periphery of the void 17 in the photoresist 16 is descumed or cut back to expose a peripheral margin 19 of polysilicon around the window 18 as illustrated in FIG. 3. Phosphorous or arsenic is then implanted as indicated by the arrows 20 by a punch-through implant process or other appropriate technique creating a N+doped zone 21 that extends under the entire descumed width of the photoresist.
As shown in FIG. 4, a second layer 22 of polysilicon is deposited then doped and patterned to create the storage capacitor plate, and the source, gate and drain of the transistor.
FIG. 5 illustrates the buried contact 23 after its diffusion and the diffusion 24 of the transistor source or drain area. It should be noted that any parasitic MOS device which may have been created between the buried contact 23 and the source or drain zone 24 is bridged by the peripheral area 26 of the phosphorous or arsenic implant. This extension of the implant greatly reduces the threshold voltage of the parasitic MOS device. Typically, a 0.2 micrometer etch back of the photoresist around the buried contact opening will be adequate in order to create a low threshold MOS device zone bridging arsenic-doped diffusions of the buried contact and source/drain structure. The window enlargement process may be used without depositing the first layer 15 of polysilicon.
It should be noted that the above-described process can be used in connection with other types of buried contacts such as those in use in connecting the gate of one transistor to the drain of another in a SRAM circuit.
While the preferred embodiments of the invention have been described, modifications can be made and other embodiments may be devised without departing from the spirit of the invention and the scope of the appended claims.

Claims (6)

What is claimed is:
1. A process for forming a buried contact between a transistor element at the surface of a substrate and a remote diffusion region which comprises the steps of:
growing an insulation layer of silicon oxide over said surface;
depositing a first layer of polysilicon over said insulation layer;
depositing a photoresist over said first polysilicon layer;
patterning a window in said photoresist;
etching said first polysilicon layer and oxide layer through said window;
descuming the edges of said photoresist window to expose a peripheral width of said first polysilicon layer;
implanting a doping element into said substrate through said descumed window and peripheral width to form a central zone of buried contact aligned with said window and a peripheral zone of buried contact substantially aligned with said peripheral width, wherein said peripheral width receives a lesser amount of doping element than said central zone;
removing said photoresist after said implanting;
depositing a second layer of polysilicon over said first layer; and
patterning said second layer to form the source, drain and other parts of said transistor, and access to said buried contact.
2. The process of claim 1, wherein the step of implanting comprises implanting into said substrate a doping element selected from a group consisting of arsenic and phosphorous. .Iadd.
3. A process for forming a buried contact between a transistor element at the surface of a substrate and a remote diffusion region which comprises the steps of:
growing an insulation layer of silicon oxide over said surface;
depositing a first layer of polysilicon over said insulation layer;
selectively forming an etch resist over said first polysilicon layer to define a window;
etching said first polysilicon layer and oxide layer exposed by said window;
exposing a peripheral width of said first polysilicon layer adjacent said window;
implanting a doping element into said substrate through said window and peripheral width to form a central zone of buried contact aligned with said window and a peripheral zone of buried contact substantially aligned with said peripheral width, wherein said peripheral zone receives a lesser amount of doping element than said central zone;
removing said etch resist after said implanting;
depositing a second layer of polysilicon over said first layer; and
patterning said second layer to form the source, drain and other parts of said transistor, and access to said buried contact..Iaddend..Iadd.4. The process of claim 3, wherein the step of implanting comprises implanting into said substrate a doping element selected from a group consisting of
arsenic and phosphorous..Iaddend..Iadd.5. A process for forming a buried contact between a transistor element at the surface of a substrate and a remote diffusion region which comprises the steps of:
growing an insulation layer of silicon oxide over said surface;
depositing a first layer of polysilicon over said insulation layer;
selectively forming a resist over said first polysilicon layer to define a window;
removing said first polysilicon layer and oxide layer exposed by said window;
exposing a peripheral width of said first polysilicon layer adjacent said window;
implanting a doping element into said substrate through said window and peripheral width to form a central zone of buried contact aligned with said window and a peripheral zone of buried contact substantially aligned with said peripheral width, wherein said peripheral zone receives a lesser amount of doping element than said central zone;
removing said resist after said implanting;
forming a selectively patterned second layer of polysilicon over said first layer to form source, drain and other parts of said transistor, and access to said buried contact..Iaddend..Iadd.6. The process of claim 5, wherein the step of implanting comprises implanting into said substrate a doping element selected from a group consisting of arsenic and
phosphorous..Iaddend..Iadd.7. A process for forming a buried contact between a transistor element at the surface of a substrate and a remote diffusion region which comprises the steps of:
forming an insulation layer over said surface;
depositing a polysilicon layer over said insulation layer;
selectively defining a window on said polysilicon layer;
removing said polysilicon layer and underlying insulation layer exposed by said window;
defining a peripheral width of said polysilicon layer adjacent said window;
implanting a doping element into said substrate through said window and peripheral width to form a central zone of buried contact aligned with said window and a peripheral zone of buried contact substantially aligned with said peripheral width, wherein said peripheral zone receives a lesser amount of doping element than said central zone; and
forming a selectively patterned conductive layer over said polysilicon layer to form source, drain and other parts of said transistor, and access to said buried contact..Iaddend..Iadd.8. The process of claim 7, wherein the step of implanting comprises implanting into said substrate a doping element selected from a group consisting of arsenic and phosphorous..Iaddend..Iadd.9. A process for forming a buried contact between a transistor element at the surface of a substrate and a remote diffusion region which comprises the steps of:
forming an insulation layer over said surface;
depositing a polysilicon layer over said insulation layer;
selectively removing said polysilicon layer and underlying insulation layer to expose said substrate through a window;
defining a peripheral width of said polysilicon layer adjacent said window for implantation of a doping element therethrough;
implanting said doping element into said substrate through said window and peripheral width to form a central zone of buried contact aligned with said window and a peripheral zone of buried contact substantially aligned with said peripheral width, wherein said peripheral zone receives a lesser amount of doping element than said central zone; and
forming a selectively patterned conductive layer over said polysilicon layer to form parts of said transistor, and access to said buried
contact..Iaddend..Iadd.10. The process of claim 9, wherein the step of implanting comprises implanting into said substrate a doping element selected from a group consisting of arsenic and phosphorous..Iaddend.
US08/613,189 1992-07-29 1996-03-08 Self-aligned low resistance buried contact process Expired - Lifetime USRE36735E (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060258164A1 (en) * 2004-04-27 2006-11-16 Manning H M Method and apparatus for fabricating a memory device with a dielectric etch stop layer
US20060264056A1 (en) * 2004-04-27 2006-11-23 Manning H M Method and apparatus for fabricating a memory device with a dielectric etch stop layer

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100189964B1 (en) * 1994-05-16 1999-06-01 윤종용 High voltage transistor and method of manufacturing the same
US5506172A (en) * 1994-08-29 1996-04-09 Micron Technology, Inc. Semiconductor processing method of forming an electrical interconnection between an outer layer and an inner layer
US6740573B2 (en) * 1995-02-17 2004-05-25 Micron Technology, Inc. Method for forming an integrated circuit interconnect using a dual poly process
US5550085A (en) * 1995-09-07 1996-08-27 Winbond Electronics Corp. Method for making a buried contact
US5926706A (en) * 1997-04-09 1999-07-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method for making a trench-free buried contact with low resistance on semiconductor integrated circuits
US6150687A (en) 1997-07-08 2000-11-21 Micron Technology, Inc. Memory cell having a vertical transistor with buried source/drain and dual gates
US6191470B1 (en) 1997-07-08 2001-02-20 Micron Technology, Inc. Semiconductor-on-insulator memory cell with buried word and body lines
US5909618A (en) 1997-07-08 1999-06-01 Micron Technology, Inc. Method of making memory cell with vertical transistor and buried word and body lines
US6072209A (en) 1997-07-08 2000-06-06 Micro Technology, Inc. Four F2 folded bit line DRAM cell structure having buried bit and word lines
US5973356A (en) * 1997-07-08 1999-10-26 Micron Technology, Inc. Ultra high density flash memory
US6066869A (en) 1997-10-06 2000-05-23 Micron Technology, Inc. Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor
US6025225A (en) * 1998-01-22 2000-02-15 Micron Technology, Inc. Circuits with a trench capacitor having micro-roughened semiconductor surfaces and methods for forming the same
US5963469A (en) 1998-02-24 1999-10-05 Micron Technology, Inc. Vertical bipolar read access for low voltage memory cell
US6304483B1 (en) 1998-02-24 2001-10-16 Micron Technology, Inc. Circuits and methods for a static random access memory using vertical transistors
US6097242A (en) 1998-02-26 2000-08-01 Micron Technology, Inc. Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits
US5991225A (en) 1998-02-27 1999-11-23 Micron Technology, Inc. Programmable memory address decode array with vertical transistors
US6124729A (en) 1998-02-27 2000-09-26 Micron Technology, Inc. Field programmable logic arrays with vertical transistors
US6080647A (en) * 1998-03-05 2000-06-27 Taiwan Semiconductor Manufacturing Company Process to form a trench-free buried contact
US6043527A (en) 1998-04-14 2000-03-28 Micron Technology, Inc. Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device
US6208164B1 (en) 1998-08-04 2001-03-27 Micron Technology, Inc. Programmable logic array with vertical transistors
US6265256B1 (en) * 1998-09-17 2001-07-24 Advanced Micro Devices, Inc. MOS transistor with minimal overlap between gate and source/drain extensions
US6136633A (en) * 1998-12-28 2000-10-24 Taiwan Semiconductor Manufacturing Company Trench-free buried contact for locos isolation
US9029956B2 (en) 2011-10-26 2015-05-12 Global Foundries, Inc. SRAM cell with individual electrical device threshold control
US9048136B2 (en) 2011-10-26 2015-06-02 GlobalFoundries, Inc. SRAM cell with individual electrical device threshold control

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4231811A (en) * 1979-09-13 1980-11-04 Intel Corporation Variable thickness self-aligned photoresist process
JPS57128067A (en) * 1981-08-21 1982-08-09 Nec Corp Manufacture of semiconductor device
US4573257A (en) * 1984-09-14 1986-03-04 Motorola, Inc. Method of forming self-aligned implanted channel-stop and buried layer utilizing non-single crystal alignment key
JPH0254935A (en) * 1988-08-19 1990-02-23 Sony Corp Manufacture of mis transistor
US4966865A (en) * 1987-02-05 1990-10-30 Texas Instruments Incorporated Method for planarization of a semiconductor device prior to metallization
US5064776A (en) * 1990-10-03 1991-11-12 Micron Technology, Inc. Method of forming buried contact between polysilicon gate and diffusion area
US5147814A (en) * 1989-03-28 1992-09-15 Seiko Epson Corporation Method of manufacturing an lddfet having an inverted-t shaped gate electrode
US5187122A (en) * 1990-02-23 1993-02-16 France Telecom Establissement Autonome De Droit Public Process for fabricating an integrated circuit using local silicide interconnection lines
US5266523A (en) * 1991-11-14 1993-11-30 Micron Technology, Inc. Method of forming self-aligned contacts using the local oxidation of silicon

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4231811A (en) * 1979-09-13 1980-11-04 Intel Corporation Variable thickness self-aligned photoresist process
JPS57128067A (en) * 1981-08-21 1982-08-09 Nec Corp Manufacture of semiconductor device
US4573257A (en) * 1984-09-14 1986-03-04 Motorola, Inc. Method of forming self-aligned implanted channel-stop and buried layer utilizing non-single crystal alignment key
US4966865A (en) * 1987-02-05 1990-10-30 Texas Instruments Incorporated Method for planarization of a semiconductor device prior to metallization
JPH0254935A (en) * 1988-08-19 1990-02-23 Sony Corp Manufacture of mis transistor
US5147814A (en) * 1989-03-28 1992-09-15 Seiko Epson Corporation Method of manufacturing an lddfet having an inverted-t shaped gate electrode
US5187122A (en) * 1990-02-23 1993-02-16 France Telecom Establissement Autonome De Droit Public Process for fabricating an integrated circuit using local silicide interconnection lines
US5064776A (en) * 1990-10-03 1991-11-12 Micron Technology, Inc. Method of forming buried contact between polysilicon gate and diffusion area
US5266523A (en) * 1991-11-14 1993-11-30 Micron Technology, Inc. Method of forming self-aligned contacts using the local oxidation of silicon

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
S. Wolf, Silicon Processing for the VLSI Era vol. II, pp. 544 545 (Lattice Press 1990). *
S. Wolf, Silicon Processing for the VLSI Era--vol. II, pp. 544-545 (Lattice Press 1990).

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060258164A1 (en) * 2004-04-27 2006-11-16 Manning H M Method and apparatus for fabricating a memory device with a dielectric etch stop layer
US20060264057A1 (en) * 2004-04-27 2006-11-23 Manning H M Method and apparatus for fabricating a memory device with a dielectric etch stop layer
US20060264056A1 (en) * 2004-04-27 2006-11-23 Manning H M Method and apparatus for fabricating a memory device with a dielectric etch stop layer
US7141511B2 (en) 2004-04-27 2006-11-28 Micron Technology Inc. Method and apparatus for fabricating a memory device with a dielectric etch stop layer
US7659211B2 (en) 2004-04-27 2010-02-09 Micron Technology, Inc. Method and apparatus for fabricating a memory device with a dielectric etch stop layer
US9064728B2 (en) 2004-04-27 2015-06-23 Micron Technology, Inc. Method and apparatus for fabricating a memory device with a dielectric etch stop layer
US9236383B2 (en) 2004-04-27 2016-01-12 Micron Technology, Inc. Method and apparatus for fabricating a memory device with a dielectric etch stop layer

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