JPH01192131A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable a semiconductor device to be highly integrated while preventing any erroneous operation due to day as well as a latch up in a MOS element from occurring by a method wherein impurities are ion-implanted with high energy capable of reaching from the surface of a semiconductor substrate to the position to form buried layers. CONSTITUTION:A buried collector 2 comprising bipolar element and a low resistance well layer 3 comprising PMOS element are respectively formed as buried layers below a medium concentration n type region 8 by selectively ion-implanting a high concentration n type impurity at accelerating voltage with high energy exceeding 1MeV using resist 23 as masks. Successively, an isolating layer 4 which PN junction isolates the buried electrode 2 and the low resistance well layer 3 is formed to reach an inversion preventive implanted layer 11 below the medium concentration n type region 8 corresponding to boundary part between the bipolar element and PMOS element by selectively ion-implanting a high concentration p type impurity at accelerating voltage exceeding 1MeV using resist 24 as masks while another low resistance well layer 5 as a buried layer is formed in a part to reach inversion preventing implanted layer formed on the region 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device having a buried layer.

[Conventional technology]

FIGS. 4(a) to 4(k) show a conventional example of the manufacturing method of this type of semiconductor device (Nikkei [Microdevice J, November 1986).
It is a sectional view showing a) listed in the monthly issue, and is performed by the following steps.

This conventional manufacturing method is for manufacturing an integrated semiconductor device having a bipolar element and an MO8 adjacent to each other. First, p-type impurities are removed from the surface of a p-type semiconductor substrate 1 using a resist as a mask. By selectively implanting ions, an implantation layer 2a that will become the buried collector of the bipolar element and an implantation layer 3a that will become the low resistance well layer of the PMO8 element among the 0MO8 elements are formed, and p-type impurities are similarly selectively implanted. By implanting ions into
Implantation 14a and 0MO to serve as a separation layer for PN junction isolation between the buried collector (n-type region) of the bipolar element and the low-resistance well layer (n-type region) of the PMO8 element adjacent thereto.
An injection layer 5a which becomes a low-resistance well layer of the NMO8 element among the NMO8 elements is formed (FIG. 4(a)).

Next, on the surface of the semiconductor substrate 1, 1014 to 1017
By epitaxially growing a semiconductor layer 6 containing an n-type impurity of /co+3, each of the above-mentioned injection layers 2a, 3
a, 4a, and 5a are buried collectors 2 of bipolar elements interposed at the boundary between the p-type semiconductor substrate 1 and the semiconductor layer 6, respectively.
9 separation layer 4. It is used as a buried layer such as the low resistance well layers 3 and 5 of CMO8 (FIG. 4(b)).

Subsequently, using a resist as a mask, the buried collector 2 . By ion-implanting n-type impurities from a region corresponding to the low-resistance well layer 3 and performing heat treatment to diffuse the n-type impurities into the semiconductor layer 6, a medium concentration n-type region 8a of the bipolar element is formed on the buried collector 2. However, the medium concentration n-type region 8 of the PMO8 element is placed on the low resistance well layer 3.
Similarly, n-type impurities are added to the semiconductor layer 6.
Separation layer 4. By implanting ions from a region corresponding to the low-resistance well layer 5 and performing heat treatment to diffuse n-type impurities into the semiconductor M6, the medium-concentration n-type impurities reach the above-described isolation layer 4 and form a medium-concentration n-type impurity of the bipolar element. Area 8a
An isolation region 9 for separating the medium-concentration n-type region 8b of the PMO8 element by a PN junction is also provided on the low-resistance well layer 5.
Medium concentration n-type regions 10 of O8 elements are formed (
Figure 4(C)).

Next, an n-type impurity is selectively implanted into a portion of the isolation region 9 and medium concentration n-type region 10 to form an inversion prevention implantation layer 11 (FIG. 4(d)), and these implantation layers 11 and medium concentration n-type region 8 of bipolar element
A thick insulating film 12 is selectively formed on a portion of a by an oxidation process (FIG. 4(e)).

Next, using the insulating film 12 formed in the medium concentration n-type region 8a of the bipolar element as a mask, the medium concentration n-type head 1ii! 8
By selectively ion-implanting n-type impurities from the surface of a and performing a thermal diffusion process, a collector 13 made of an n-type impurity layer that reaches the buried collector 2 is formed (FIG. 4(f)).
).

Next, in order to set the threshold voltage of the PMO8 elements high and the NMO8 elements low, n-type impurity ions are implanted into the medium concentration n-type region 8b and the medium concentration n-type region 10 to form an implanted layer. (not shown), PM is formed on the surfaces of the medium concentration n-type region 8b and the medium concentration n-type region 10.
Insulating film 14 serving as the gate of the O8 element and the NMO8 element
．． N-type semiconductor layers 15 are deposited, and high-concentration n-type impurities are selectively ion-implanted into the medium-concentration p-type head 110 and subjected to thermal diffusion treatment to form high-concentration n-type impurities.
A source/drain region 16, which is a type region, is formed, and thereby an NMO3 element is formed on the 0MO8 side (FIG. 4(g)).

Next, a base region 17 is formed by selectively ion-implanting a medium concentration n-type impurity into the medium concentration n-type region 8a of the bipolar element (FIG. 4(h)). By selectively ion-implanting a high IIa n-type impurity into the middle-concentration n-type region 8b on the MO8 side and performing heat treatment, a high-concentration base region 17a and a source/drain region which is a high-concentration p-type head region are formed. 18 was formed,
As a result, a PMO8 element is formed on the 0MO8 side (
Figure 4(i)).

Subsequently, a thin oxide 1119 is formed on the entire surface of the semiconductor substrate,
After that, a part of the oxide film 19 corresponding to the base region 17 of the bipolar element is removed, and an emitter region 20 made of a highly doped n-type semiconductor layer reaching the base region 17 is patterned (FIG. 4(j)). ).

Finally, interlayer insulation 11121 is formed on the entire surface of the semiconductor substrate, and wiring 22 that contacts each element is formed through openings selectively formed in this interlayer insulation film 21 (see FIG. 4).
k)).

(Problems to be Solved by the Invention) Since the conventional manufacturing method of a semiconductor device is performed by the above steps, a high concentration buried layer such as a low resistance well layer 3.5 of a bipolar buried collector 2°0 MO8 is Figure 4(b)
During epitaxial growth at high temperatures (950 to 1,100°C) as shown in Figure 4 (C) and thermal diffusion treatment at high temperatures and for a long time as shown in Figure 4 (C), it spreads laterally. Collector 2 (n-type region) and separation layer 4
(p-type head region), the junction capacitance between them increases and the PN junction withstand voltage deteriorates, resulting in a problem that high integration cannot be achieved.

Also, during the epitaxial growth and thermal diffusion treatment mentioned above,
Embedded collector 2. Since the low resistance well 113.5 also diffuses in the depth direction, the epitaxial layer must be formed sufficiently thick so that the diffusion does not affect the electrical characteristics such as the threshold voltage of 0MO8. In addition to being subject to manufacturing constraints, the spread of the impurity distribution in the low resistance wells 3 and 5 also reduces the potential barrier effect of these low resistance well layers 3 and 5 against minority carriers generated with α rays. There were also problems.

This invention was made to solve these problems, and it enables high integration and prevents malfunctions caused by alpha rays and M
An object of the present invention is to obtain a method for manufacturing a semiconductor device that is also effective in preventing latch-up in O8 elements.

[Means to solve the problem]

A method for manufacturing a semiconductor device according to the present invention forms a buried layer by implanting impurity ions from the surface of a semiconductor substrate with an island energy that can reach the position where the buried layer is to be formed.

[Effect]

In this invention, since the buried layer is formed by high-energy ion implantation, there is no need for high-temperature and long-term heat treatment during the ion implantation, and lateral diffusion of the buried layer is suppressed, and deep Since diffusion in the horizontal direction is also suppressed, it is possible to form a buried layer that is effective in preventing malfunctions and latch-ups caused by alpha rays.

〔Example〕

FIGS. 1(a) to 1(d) are cross-sectional views showing some steps of an embodiment of the method for manufacturing a semiconductor device according to the present invention, which is performed by the following steps.

The manufacturing method of this embodiment is for manufacturing an integrated semiconductor device having bipolar elements and 0MO8 adjacent to each other as in the conventional example described above. By selectively ion-implanting and diffusing p-type impurities and p-type impurities, a medium concentration n-type region 8 is also formed in the bipolar element and the part where the PMO8 element of the 0MO8 is planned to be formed.
Medium concentration n-type regions 10 are formed in the portions of MO8 where NMO8 elements are planned to be formed (see FIG. 1(a)).
).

Next, a p-type impurity is ion-implanted into a part of the medium-concentration n-type region 8 and medium-concentration n-type region 10 using a low-energy accelerating voltage, thereby forming the inversion prevention implantation layer 11. are formed respectively, and then a thick insulating layer 112 is selectively formed on these injection layers 11 and a part of the medium concentration n-type region 8 on the bipolar element side by an oxidation process (FIG. 1(b)).

Next, using the resist 23 as a mask, high concentration n-type impurities are selectively ion-implanted at a high-energy acceleration voltage of 1 Mev or more, thereby forming bipolar elements and PM.
A buried collector 2 of the bipolar element and a low resistance well layer 3 of the PMO8 element are buried under the medium concentration n-type head 1i18 where the O8 element is planned to be formed (a region deeper than 1 μm from the surface of the semiconductor substrate 1). (Fig. 1(C)).

Subsequently, using the resist 24 as a mask, a high concentration n-type impurity is selectively ion-implanted at an accelerating voltage of 1 MeV or higher to form a medium-concentration n-type region 8 corresponding to the boundary between the bipolar element and the PMO8 element. The m layer 4 for separating the buried collector 2 (n-type head [) and the low-resistance well layer 3 (n-type region) by PN junction] is formed in the lower part, and an injection layer 11 for preventing inversion is formed thereon. The medium concentration p-type head t, in which the NMO8 element is planned to be formed, will be formed to reach the
A low resistance well layer 5 is formed as a buried layer under the aio (FIG. 1(d)). By forming the separation layer 4, the medium concentration n-type region 8 is separated into a region 8a on the bipolar element side and a region 8b on the PMO8 element side.

From now on, (f) to ( in FIG. 3 showing the conventional manufacturing method) will be explained.
By following the same steps as k), an integrated semiconductor device having a bipolar element and 0MO8 can be obtained.

According to such a manufacturing method, it is possible to omit high-temperature and long-term heat treatment such as when forming an epitaxial layer.
Diffusion of the buried layer is effectively prevented.

Further, even if the buried layer is subjected to a certain degree of heat treatment after formation, there is almost no diffusion of the buried layer (see experimental example below). Furthermore, when high-energy ion implantation is used, relatively few defects are generated in the single crystal silicon forming the semiconductor substrate 1.

Figure 2 shows an acceleration voltage of 1.2 MeV and a dose of 1X1013.
This shows the impurity concentration distribution in the depth direction when boron of /C1112 is ion-implanted into a silicon substrate.
The figure shows the impurity concentration distribution in the depth direction when boron ions were implanted into a silicon substrate under the same conditions and then heat treatment was performed at 1000° C. for 100 minutes.

As is clear from the impurity concentration distribution shown in Figure 2, the first
A buried collector 2, low resistance well layers 3, 5, by ion implantation under high energy in the steps shown in FIGS. (c) and (d),
It can be seen that in forming the separation layer 4, these buried layers are formed in a sufficiently deep region with high concentration and a steep concentration gradient. Therefore, during the formation of these buried layers, impurities do not affect the surface layer portion of p-type semiconductor substrate 1.

Further, the impurity concentration distribution shown in FIG. 3 shows that the buried layer formed by ion implantation under high energy is not significantly affected by heat treatment for activation.

(Effects of the Invention) As explained above, the present invention can form a buried layer with a steep concentration gradient by high-energy ion implantation.
High-temperature and long-term heat treatment can be omitted, diffusion of the buried layer in the lateral and depth directions can be suppressed, and high integration of semiconductor devices can be achieved. This has the effect of reliably preventing malfunctions and latch-ups due to

[Brief explanation of the drawing]

FIGS. 1(a) to (d) are cross-sectional views showing some steps of an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIGS. 2 and 3 show impurity concentration by ion implantation under high energy. Graphs showing the distribution and FIGS. 4(a) to 4(k) are cross-sectional views showing a conventional method of manufacturing a semiconductor device. In the figure, 1 is a p-type semiconductor substrate, 2 is a buried collector (
3.5 is a low resistance well layer (buried layer), and 4 is a separation layer (buried layer). Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) In a method for manufacturing a semiconductor device having a buried layer,
A method for manufacturing a semiconductor device, characterized in that the buried layer is formed by implanting impurity ions with high energy that can reach the position where the buried layer is to be formed from the surface of the semiconductor substrate.