JPS62291164A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62291164A
JPS62291164A JP13666886A JP13666886A JPS62291164A JP S62291164 A JPS62291164 A JP S62291164A JP 13666886 A JP13666886 A JP 13666886A JP 13666886 A JP13666886 A JP 13666886A JP S62291164 A JPS62291164 A JP S62291164A
Authority
JP
Japan
Prior art keywords
region
emitter
regions
cathode
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13666886A
Other languages
Japanese (ja)
Inventor
Hiroshi Yoshida
弘 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP13666886A priority Critical patent/JPS62291164A/en
Publication of JPS62291164A publication Critical patent/JPS62291164A/en
Pending legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To reduce the leakage current of a semiconductor device by ion implanting twice a reverse conductivity type impurity to a substrate to an emitter region in a base region and a cathode region in an anode region by altering the conditions of a high acceleration voltage and a low acceleration voltage. CONSTITUTION:Reverse conductivity type impurity to a substrate 10 is implanted twice to emitter regions 21, 22 in a transistor base region 20 and cathode regions 31, 32 in an anode region 30 by altering the conditions of high and low accelcration voltages. Then, it is heat treated to form the junction of the cathode regions shallower than that of the emitter regions and at high density. Since the ion implantations are divided into two in this manner and the second implantation is to near the surface by avoiding the first deep implantation, a crystal defect is suppressed as compared with a conventional method for ion implanting a large quantity of ions, resulting in a decrease in the current leakage of a constant-voltage diode.

Description

【発明の詳細な説明】 発明の詳細な説明 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特にバイポーラ
型集積回路のトラジスタのエミッタ及び定電圧ダイオー
ドのカソードをイオン注入法で、同時に形成する半導体
装置の製造方法に関する。
Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and in particular, to a method of manufacturing a semiconductor device, in particular, the emitter of a transistor of a bipolar integrated circuit and the cathode of a constant voltage diode are formed by ion implantation. The present invention relates to a method for manufacturing semiconductor devices that are simultaneously formed.

〔従来の技術〕[Conventional technology]

従来、バイポーラ型集積回路のトランジスタのエミッタ
形成は、ガス拡散が主であった。最近ウェーハの大口径
化に伴ない、面内バラツキの少ないイオン注入方式が使
用される様になってきた。
Conventionally, emitter formation of transistors in bipolar integrated circuits has been mainly performed by gas diffusion. Recently, as wafers have become larger in diameter, ion implantation methods with less in-plane variation have come into use.

集積回路に定電圧ダイオードを含む場合、トラジスタの
ベース領域より高い不純物濃度のアノード領域上に、エ
ミ・ツタ形成と同時にイオン注入し、カソード領域を形
成する。
When an integrated circuit includes a constant voltage diode, ions are implanted onto an anode region having a higher impurity concentration than the base region of the transistor at the same time as emitter vines are formed to form a cathode region.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところが、−ト述した従来の製造方法では、イオン注入
は1回でしかも高濃度で打込むため、表面近くで結晶欠
陥を誘発する。このためトランジスタより浅い表面近く
の接合を利用する定電圧ダイオードは、電流リークを生
ずる欠点がある。結晶欠陥をなくすためにはイオン注入
量を減らす方法があるが、不純物量の低下により、トラ
ンジスタのhPEの低下、及び定電圧ダイオードの電圧
の上昇を招くため解決策とならない。結局定電圧ダイオ
ードを含む集積回路のイオン注入化は不可能という状況
であった。
However, in the conventional manufacturing method described above, ions are implanted once and at a high concentration, which induces crystal defects near the surface. For this reason, a constant voltage diode that uses a junction near the surface that is shallower than a transistor has the disadvantage of causing current leakage. One way to eliminate crystal defects is to reduce the amount of ion implantation, but this is not a solution because the reduction in the amount of impurities causes a decrease in the hPE of the transistor and an increase in the voltage of the constant voltage diode. In the end, it was impossible to implement ion implantation into integrated circuits containing constant voltage diodes.

本発明の目的は、1ヘランジスタと定電圧ダイオードを
有する半導体装置の製造方法において、定電圧ダイオー
ドのカソード領域がトランジスタのエミッタ領域より浅
く、かつ高濃度に形成され、定電圧ダイオードの電圧上
昇を招くことがなく、かつリーク電流を生ぜず、一方ト
ランジスタのhFEの低下を生ずることがないイオン注
入法によるカソード並びにエミッタ領域を形成する半導
体装置の製造方法を提供することにある。
An object of the present invention is to provide a method for manufacturing a semiconductor device having a helangistor and a constant voltage diode, in which the cathode region of the constant voltage diode is formed to be shallower and more concentrated than the emitter region of the transistor, which causes an increase in the voltage of the constant voltage diode. It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a cathode and an emitter region are formed by ion implantation, which does not cause leakage current, and does not cause a decrease in hFE of a transistor.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置の製造方法は、半導体基板内に基板
と同導電型で、互いに表面不純物濃度の異なる2つの領
域を形成し、形成された前記領域の内気濃度領域をトラ
ンジスタのベース領域、高濃度領域を定電圧ダイオード
のアノード領域なする半導体装置の製造方法において、
前記ベース領域内のエミッタ領域及びアノード領域内の
カソード領域に前記基板と反対導電型の不純物を高加速
電圧と低加速電圧との条件を変えて2回に分けてイオン
注入する工程と、ひき続き熱処理する工程とを含み、前
記カソード領域の接合を前記エミッタ領域の接合より浅
く、がっ高濃度に形成することにより構成される。
The method for manufacturing a semiconductor device of the present invention includes forming two regions in a semiconductor substrate that are of the same conductivity type as the substrate and have different surface impurity concentrations, and a region with an internal concentration of the formed regions is used as a base region of a transistor and a high concentration region. In a method of manufacturing a semiconductor device in which a concentration region is an anode region of a constant voltage diode,
a step of ion-implanting an impurity of a conductivity type opposite to that of the substrate into the emitter region in the base region and the cathode region in the anode region in two steps under different conditions of high acceleration voltage and low acceleration voltage; and a step of heat treatment, and the junction in the cathode region is formed to be shallower and more highly concentrated than the junction in the emitter region.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。第1図は本発明の一実施例により形成された半導体装
置の断面図である。第1図において、気相成長層10内
にコレクタコンタクト領域23.24、ベース領域20
.エミッタ領域21゜22からなるNPN)ラジスタを
形成する。一方定電圧ダイオードは絶縁アノードとし、
31,32をカソードとして形成されている。第2図(
a>、(b)は本発明の一実施例を説明するために工程
順に示した。第1−図の破線部分の拡大断面図である。
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a semiconductor device formed according to an embodiment of the present invention. In FIG. 1, collector contact regions 23, 24 and base regions 20 are included in the vapor growth layer 10.
.. An NPN) radiator consisting of emitter regions 21° and 22 is formed. On the other hand, the voltage regulator diode has an insulated anode,
31 and 32 are formed as cathodes. Figure 2 (
a> and (b) are shown in order of steps to explain one embodiment of the present invention. FIG. 1 is an enlarged sectional view of the broken line portion in FIG. 1;

第2図<a)で加速電圧50にeV 〜150feV、
ドーズ量5X101S〜2X10’6の高加速エネルギ
、高ドーズ量のリンを注入しN+領域2131を形成す
る。このときベース領域20とアノード領域30は不純
物濃度が異なるので形成される第1のイオン注入エミッ
タ領域は第1イオン注入カード領域より深く形成される
。ひきつづき、打込み条件を変えてイオン注入を行なう
。即ち加速電圧を40にeVに下げ、ドース量も2X1
0’5以下に下げ、第2図(b)に示す様に領域22゜
32を形成する。領域22.23は加速電圧が低いため
不純物濃度の最大値は表面近くになる。その後熱処理を
し、所定の深さに押込み、完成する。
In Fig. 2 <a), the acceleration voltage is 50 eV ~ 150 feV,
Phosphorus is implanted at a high acceleration energy and a high dose of 5X101S to 2X10'6 to form an N+ region 2131. At this time, since the base region 20 and the anode region 30 have different impurity concentrations, the first ion-implanted emitter region is formed deeper than the first ion-implanted card region. Subsequently, ion implantation is performed by changing the implantation conditions. That is, the accelerating voltage was lowered to 40 eV, and the dose was also reduced to 2X1.
0'5 or less to form a region 22°32 as shown in FIG. 2(b). Since the accelerating voltage is low in the regions 22 and 23, the maximum impurity concentration is near the surface. After that, it is heat treated and pressed to a predetermined depth to complete it.

なお上記実施例では1回目に高加速電圧、2回目は低加
速電圧でイオン注入したがこれを逆にしても本発明の目
的を達成できるこは言うまでもない。
In the above embodiments, ions were implanted at a high accelerating voltage for the first time and at a low accelerating voltage for the second time, but it goes without saying that the object of the present invention can be achieved even if this is reversed.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明では、イオン注入を2回に
分け、かつ2回目のイオン注入を、1回目のイオン注入
の深さを避は表面近くに打ち込むため、1度に多量のイ
オン注入をする従来の方法に比べ、結晶欠陥を抑制し、
その結果定電圧ダイオードの電流リークが減少する効果
がある。
As explained above, in the present invention, ion implantation is divided into two steps, and the second ion implantation is implanted close to the surface to avoid the depth of the first ion implantation, so a large amount of ions are implanted at one time. Compared to conventional methods, crystal defects are suppressed,
As a result, current leakage from the constant voltage diode is reduced.

また、イオン注入後の熱処理により、1回目のイオン注
入時の不純物が」1方にも拡散し、2回目のイオン注入
不純物に加わり定電圧ダイオード領域を形成する。従っ
て所定の定電圧を得るのに必要な不純物濃度を得ること
ができる。
Further, due to the heat treatment after the ion implantation, the impurities from the first ion implantation are also diffused in one direction, and are added to the impurities from the second ion implantation to form a constant voltage diode region. Therefore, the impurity concentration necessary to obtain a predetermined constant voltage can be obtained.

一方、トランジスタのエミッタ領域は深く打ち込んだ1
回目のイオン注入と2回目のイオン注入の合計不純物量
が、エミッタ濃度になり、希望のhPRを得ることがで
きる。
On the other hand, the emitter region of the transistor is deeply implanted.
The total amount of impurities from the first ion implantation and the second ion implantation becomes the emitter concentration, and the desired hPR can be obtained.

工程の増加については、イオン注入が1回増加するが、
濃度制御性の良いイオン注入による特性バラツキ減少の
利点が大きく、結局総合的に改善になる。
Regarding the increase in the number of steps, ion implantation increases by one time, but
Ion implantation with good concentration control has the great advantage of reducing variation in characteristics, resulting in an overall improvement.

6一61

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例により形成された半導体装置
の断面図、第2図(a>、(b)は本発明の一実施例を
説明するために工程順に示した第1図の破線部分の拡大
断面図である。 10・・・半導体基販、11・・・絶縁膜、20・・・
トランジスタベース領域、21・・第1イオン注入エミ
タ領域、22・・第2イオン注入エミツタ領域、23・
・・第1イオン注入コレクタコンタクト領域、24・・
第2イオン注入コレクタコンタクト領域、30・・・定
電圧ダイオードアノード領域、31・・・第1イオン注
入コレクタコンタクI−領域、31・第1イオン注入カ
ソード領域、32・・・第2イオン注入カソード領域。 華 2 田
FIG. 1 is a cross-sectional view of a semiconductor device formed according to an embodiment of the present invention, and FIGS. 2(a) and 2(b) are diagrams of FIG. It is an enlarged sectional view of the broken line part. 10... Semiconductor sales, 11... Insulating film, 20...
Transistor base region, 21..First ion implantation emitter region, 22..Second ion implantation emitter region, 23.
...First ion implantation collector contact region, 24...
Second ion implantation collector contact region, 30... Constant voltage diode anode region, 31... First ion implantation collector contact I- region, 31. First ion implantation cathode region, 32... Second ion implantation cathode region. Flower 2 field

Claims (1)

【特許請求の範囲】[Claims] 半導体基板内に基板と同導電型で、互いに表面不純物濃
度の異なる2つの領域を形成し、形成された前記領域の
内低濃度領域をトランジスタのベース領域、高濃度領域
を定電圧ダイオードのアノード領域とする半導体装置の
製造方法において、前記ベース領域内のエミッタ領域及
び前記アノード領域内のカソード領域に、前記基板と反
対導電型の不純物を、高加速電圧と、低加速電圧との条
件を変えて2回に分けてイオン注入する工程と、ひき続
き熱処理する工程とを含み、前記カソード領域の接合を
前記エミッタ領域の接合より、浅く、かつ高濃度に形成
することを特徴とする半導体装置の製造方法。
Two regions of the same conductivity type as the substrate but with different surface impurity concentrations are formed in the semiconductor substrate, and of the formed regions, the low concentration region is used as a base region of a transistor, and the high concentration region is used as an anode region of a constant voltage diode. In the method for manufacturing a semiconductor device, an impurity having a conductivity type opposite to that of the substrate is added to an emitter region in the base region and a cathode region in the anode region under different conditions of high acceleration voltage and low acceleration voltage. Manufacturing a semiconductor device, comprising a step of ion implantation in two steps and a step of subsequent heat treatment, and forming a junction in the cathode region to be shallower and more concentrated than a junction in the emitter region. Method.
JP13666886A 1986-06-11 1986-06-11 Manufacture of semiconductor device Pending JPS62291164A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13666886A JPS62291164A (en) 1986-06-11 1986-06-11 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13666886A JPS62291164A (en) 1986-06-11 1986-06-11 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62291164A true JPS62291164A (en) 1987-12-17

Family

ID=15180695

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13666886A Pending JPS62291164A (en) 1986-06-11 1986-06-11 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62291164A (en)

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