JPH02262372A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To manufacture SBD in reduced parasitic series-resistance structure regardless of the thickness and impurity concentration of an epitaxial layer by a method wherein the second buried region in the same conductivity type as that of an element formation layer and higher impurity concentration than that of the same layer is provided between the surface of a substrate and the first buried layer. CONSTITUTION:A buried layer 2 in the same conductivity type as that of an element formation layer 3 and higher impurity concentration than that of the layer 3 is provided on the position at the first distance from the surface of a substrate 1 in the depth direction within the semiconductor substrate 1 wherein the element formation layer 3 in the first impurity concentration is formed; a buried region 7 (n<+> region) in the same conductivity type as that of the said element formation layer 3 and higher impurity concentration than that of the layer 3 is provided on the position at the second distance from the surface of the substrate 1 shorter than the first distance; and then Schottky barrier diodes are formed on the surface of the substrate 1 opposite to the said buried region 7 holding the said element formation layer 3. For example, a part of an n<-> epitaxial layer 3 is implanted with As<+> at high energy level and heat- treated for activation to form the n<+>region 7.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a structure and method for forming a Schottky barrier diode (SBD) in an integrated circuit mainly composed of bipolar elements, and is independent of constraints on the design of other elements. With the aim of reducing the parasitic series resistance of the SBD, the SBD formation head area of the semiconductor substrate is set such that the impurity concentration at the surface portion of the area is a value that matches the desired device characteristics, and the inside of the area is A high impurity concentration buried region of the same conductivity type is provided, and an SBD is formed on the surface.

In addition, in the above structure, the high impurity concentration region provided inside the SBD formation region is formed by implanting a large amount of impurity deeper than the central plane of the element formation layer using a high energy ion implantation device with an acceleration voltage of MeV class. formed by

[Industrial application field]

The present invention relates to the structure of an SBD provided in a bipolar integrated circuit and a method of forming the structure, and in particular to a process for reducing the parasitic series resistance of the SBD.

Among integrated circuits (ICs) formed on semiconductor substrates, in those whose main constituent elements are bipolar transistors, an epitaxial layer with an impurity concentration through which transistor shadow formation is grown is grown on a substrate of the opposite conductivity type, and various types of It is usual to form elements. Therefore, in order to reduce the parasitic collector series resistance of the Tr, a heavily doped buried layer is provided under the epitaxial layer. Further, the impurity concentration and thickness of the epitaxial layer are set according to the characteristics of the bipolar transistor.

In recent years, there has been an increasing demand for higher speed ICs, and as a measure to meet this demand, SBDs that do not accumulate minority carriers have been used. SBDs are of course high-speed when utilizing their rectifying properties, but they are also used to increase the speed of bipolar transistors by clamping the collector/base of the transistor with the SBD.

[Prior Art and Problems to be Solved by the Invention] When an SBD is effectively used to speed up an IC, it is required that the parasitic series resistance of the SBD itself be low. S.B.
D is usually formed on a semiconductor substrate configured for IC formation as shown in FIG. The generation of parasitic series resistance in an SBD having such a structure will be explained with reference to the drawings. In the figure, 1 is a p-type Si substrate, 2 is an n-layer buried layer, and 3 is an n-type epitaxial layer, where n- is, for example, lXIO"am-', and the n layer is 1
The concentration is 0 cm-' or more.

A Schottky barrier (SB) 8 is present between the n-epitaxial layer and the anode electrode 5, forming a diode. The height of the Schottky barrier is determined by the impurity concentration of the n layer and the material of the anode electrode, and the cathode side of the diode is connected to the wiring via the cathode electrode 6 via the n6 buried layer 2 and the n0 connection diffusion 4.

In addition, the region indicated by the symbol BT in the same figure schematically represents the structure of a bipolar transistor fabricated on the same substrate, and this element consists of an emitter E, a base B, and a collector C, and has an The buried layer 2 is provided for the purpose of reducing the resistance of the connection from the substrate surface to the collector. n
- The epitaxial layer 3 will have a thickness adapted to the formation of this transistor.

In the above SBD structure, the n" buried layer 2 or the n° connection diffusion region 4 has a low resistance, whereas the n- epitaxial layer is thick enough to have a high specific resistance.
The resistance component in this region parasitically exists as a series resistance of the diode. To reduce the parasitic series resistance, it is necessary to lower the resistance of the core layer or reduce its thickness.

However, since the impurity concentration and thickness of this epitaxial layer are selected according to the design of the bipolar transistor formed in the same substrate as mentioned above, it is not allowed to change them without permission. One possibility is to selectively diffuse impurities into the SBD formation region to lower the resistance, but if the impurity concentration in the surface region changes, the height of the Schottky barrier also changes, and the SBD
becomes unsuitable for its intended use. Therefore, such a method cannot be said to be generally effective.

An object of the present invention is to provide an SBD with a structure in which parasitic series resistance is reduced without being restricted by the thickness or impurity concentration of the n-epitaxial layer, and a processing method for forming such a structure. I operate faster due to
An object of the present invention is to provide a method for forming C.

[Means to solve the problem]

In order to achieve the above object, the apparatus of the present invention includes, within a semiconductor substrate having an element formation layer with a first impurity concentration on the surface, a position spaced a first distance from the surface of the substrate in the depth direction;
A buried layer having the same conductivity type as the element formation layer and having a higher impurity concentration is provided, and the buried layer is located between the substrate surface and the buried layer and is smaller than a first distance from the substrate surface in the depth direction. certain second
A buried region having the same conductivity type as the element forming layer and having a higher impurity concentration is provided at a distance of , and a buried region is provided on the substrate surface at a position opposite to the buried region (7) with the element forming layer in between. A method of manufacturing a semiconductor device according to the present invention is characterized in that a Sittke barrier diode is formed. preparing a semiconductor substrate provided with a buried layer of the same conductivity type and higher impurity concentration as the element formation layer at a position separated from the element formation layer by a first distance in the depth direction; The high impurity concentration is achieved by ion-implanting an impurity of the same conductivity type as the element formation layer into the region with an acceleration energy such that the depth of the distribution center is greater than the first distance of 172, and heat-treating the region. forming a buried region;
and forming a Schillatke barrier diode on the surface of the substrate at a position opposite to the buried region with the element formation layer in between.

In the above manufacturing process, according to the embodiment, As and P are implanted deeply and in large quantities into the n-epitaxial layer using a MeV class high energy ion implanter, without changing the impurity concentration in the surface region. , an SBD is formed by lowering the resistance of the internal epitaxial layer.

The cross-sectional structure of the SBD included in the semiconductor device of the present invention is schematically shown in FIG. The difference between this structure and the structure shown in FIG. 3 is that the second embedded region n
``It is located at the point where head area 7 is formed, and n in the upper part of M9M area.
- SBD is formed on the layer surface. Furthermore, when a bipolar transistor is incorporated into the same substrate, its structure becomes the part indicated by the symbol BT, as in FIG.

[For production]

With such a structure, the impurity concentration in the surface region does not change, so the height of the Schottky barrier does not change.However, since the resistance of most of the region that conventionally caused parasitic resistance is reduced, the parasitic series The resistance is significantly reduced and the SBD properties are excellent. Normally, the n-epitaxial layer for bipolar transistor formation is several μm thick.
In order to reduce the resistance over almost the entire depth direction, it is necessary to implant a large amount of impurity ions and to deepen the center of the distribution.

In order to most efficiently reduce the resistance of the element formation layer by such ion implantation, the distribution center of the implanted ions should be 0.1 to 0.2 μm deeper than the central plane in the thickness direction of the element formation layer. However, considering the practical tolerance, the object of the present invention can be achieved by setting the distribution center deeper than the center plane of the element forming layer. become.

When the thickness of the element formation layer of the S+ substrate is 3.0 am,
In order to implant As'' ions to a depth of 1.6 μm, it is necessary to set the accelerating voltage to 2.0 M e V, and such ion implantation is performed using the M
This was made possible for the first time using an eV class injection device.

〔Example〕

FIG. 2 is a schematic cross-sectional view showing steps in an embodiment of the manufacturing method of the present invention. The steps will be described below with reference to the drawings.

(Figure 81 shows the structure of a substrate used to form a conventional bipolar IC, and this structure is formed by the following process.

First, an n'' diffusion region is selectively formed on the surface of the p-type single-crystal Si-based Fil 1, and an n'' epitaxial layer 13 is grown thereon by vapor phase epitaxial growth.At this time, the n'' diffusion region Impurities diffuse upward from 11,
A buried layer 12 is formed.

Furthermore, n' connection region 14 is formed by selective diffusion (a
) The state shown in the figure is obtained. The above processing is carried out according to normal IC manufacturing processes. In addition, the surface of the substrate is a SiO□ film 15.
The membrane is coated with 5 layers.

Next, the process of the present invention begins, and (g) As shown in the figure, a metal mask 16 for selectively performing ion implantation is provided.
is injected with high energy. The accelerating voltage at this time is selected so that the distribution center of the implanted As is at the center of the beam of the epitaxial layer or deeper than that. - For example, if the epitaxial layer has a thickness of 3.0 μm, the accelerating voltage is 2.0 M e V and the depth of the distribution center is 1.6 μm. The ions to be implanted may be any n-type impurity such as P0 or Sb' in addition to As', and selective implantation without a mask may be performed using a focused ion beam.

When this is heat-treated at 900°C for 30 minutes to activate the implanted As, an n'' region 17 is formed inside the SBD formation region as shown in (C), and the impurity concentration in the upper region is n- If an electrode with a Schottky barrier is formed on the surface of this region by normal processing, the structure shown in FIG. 1 will be obtained, and an SBD with reduced parasitic series resistance and excellent diode characteristics can be obtained.

〔Effect of the invention〕

As explained above, the SBD included in the present invention is
Since the parasitic series resistance is greatly reduced by the n465 region which is the buried layer, it greatly contributes to improving the characteristics of (2)c. Further, the method of the present invention using a high-energy ion implantation device enables the formation of an SBD with the above structure.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view showing the structure of the SBD of the present invention. FIG. 2 is a schematic cross-sectional view showing the steps of an embodiment of the present invention. FIG. 1 is a P-type Si substrate, 2 is an n-type buried layer, 3 is an n-type epitaxial layer, 4 is an n-connection diffusion, 5 is an anode electrode, 6 is a cathode electrode, 7 is an n0 region, and 8 is a Schottky barrier. (SB), 11 is a p-type Si substrate, 12 is an n-type buried layer, 13 is an n-type epitaxial layer, 14 is an n1-connected gJI region, 15 is a SiO□ film, 16 is a metal mask, 17 is an n' region BT is a bipolar transistor region. BT Schematic cross-sectional diagram showing the structure of the SBD of the present invention Schematic cross-sectional diagram showing the structure of the conventional SBD Schematic cross-sectional diagram showing the process of the embodiment of the present invention

Claims (2)

[Claims] (1) In a semiconductor substrate (1) having an element formation layer (3) with a first impurity concentration on its surface, at a position separated from the substrate surface by a first distance in the depth direction,
A buried layer (2) having the same conductivity type as the element forming layer (3) and having a higher impurity concentration is provided at a position between the substrate surface and the buried layer (2) and at a depth from the substrate surface. A buried region (7) having the same conductivity type as the element forming layer (3) and having a higher impurity concentration is provided at a position separated from the element forming layer (3) by a second distance that is smaller than the first distance in the direction; The embedded area (7) with (3) in between
A Schottky barrier is placed on the surface of the substrate at a position opposite to
A semiconductor device comprising a diode. (2) A method for manufacturing a semiconductor device according to claim (1), wherein the element forming layer (3) is provided in a surface region, and the element forming layer (3) is provided at a position separated from the surface by a first distance in the depth direction. 3
) with the same conductivity type and higher impurity concentration (2)
a step of preparing a semiconductor substrate (1) provided with a distribution center of a selected region of the element formation layer (3) of the semiconductor substrate (1), the depth of which is 1/2 of the first distance; forming the buried region (7) with a high impurity concentration by ion-implanting an impurity of the same conductivity type as the element forming layer with a higher acceleration energy and performing heat treatment, and the element forming layer (3). The embedded area (7) with
A Schottky barrier is placed on the surface of the substrate at a position opposite to
A method for manufacturing a semiconductor device, comprising a step of forming a diode.