JPH01235367A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the leakage of a Zener diode by forming an element isolation layer, shaping a first region in the Zener diode so that impurity concentration in the first region is made lower than that in the element isolation layer and forming the first region in the Zener diode at the same time as an emitter region in a bipolar transistor through a polycrystalline silicon layer. CONSTITUTION:An N-type epitaxial layer 3 is formed onto a P-type semiconductor substrate 1, and P-type element isolation regions 5 are shaped to the epitaxial layer 3. A P-type cathode region 6, P-type impurity concentration of which is made lower than the element isolation regions 5, in a Zener diode and a P-type base region 11 in a bipolar transistor are formed into the epitaxial layer 3. A polycrystalline silicon layer 12 is shaped onto the whole surface, the ions of an N-type impurity are implanted through the polycrystalline silicon layer 12, and an N-type anode region 16A being in contact with a P-type cathode region 6 is formed while an N-type emitter region 16 is shaped into the P-type base region 11. Accordingly, a junction in a second region in the Zener diode can be formed more deeply, thus preventing the leakage of the constant voltage Zener diode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having a high-speed bipolar transistor and a constant voltage diode.

[Conventional technology]

Conventionally, in a semiconductor device having a bipolar transistor and a constant voltage diode, as shown in FIG.
Then, an N-type impurity was introduced through the polycrystalline silicon layer 12 to form an N-type anode region 16A at the same time as the N-type emitter region 16 of the NPN transistor, thereby forming a PN junction constant voltage diode.

[Problem to be solved by the invention]

When forming the N-type anode region 16A of the constant voltage diode at the same time as the emitter region of the NPN transistor using the conventional semiconductor device manufacturing method described above, since the concentration of P-type impurities in the cathode region is high, the N-type anode region 16A Since the junction is shallower than the N-type emitter vine region 16, there is a drawback in that the constant voltage diode is more likely to cause leakage.

An object of the present invention is to provide a method for manufacturing a semiconductor device having a constant voltage diode with little leakage.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes the steps of: forming an opposite conductivity type epitaxial layer on a -conductivity type semiconductor substrate, and then forming a one conductivity type element isolation region in the epitaxial layer;
forming a first region of a constant voltage diode having a lower impurity concentration of one conductivity type than the element isolation region and a base region of one conductivity type of a bipolar transistor in the epitaxial layer, and forming a polycrystalline silicon layer on the entire surface. Thereafter, the method includes the steps of ion-implanting impurities of opposite conductivity type through the polycrystalline silicon layer to form a second region in contact with the first region, and at the same time forming an emitter region in the base region.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1A to 1G are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1(a), N+
After forming the type buried layer 2, an N type epitaxial layer 3 is grown on the entire surface. Next, an oxide film 4 is formed on the surface by thermal oxidation, and then patterned. Using this oxide film 4 as a mask, a P-type element isolation layer 5 is formed at a temperature of, for example, 1080'C, so that the specific resistance ρS becomes 10Ω/hole. and then 1
Indentation oxidation is carried out at 200°C. Next, after this oxide film 4
After diffusing P-type impurities using the mask as a mask, for example, at 1000°C so that ρS is 30Ω/mouth,
By performing push-in oxidation, a P-type cathode region 6 of a constant voltage diode having a lower concentration than the P-type element isolation layer 5 is formed.

Next, as shown in FIG. 1(b), after removing the oxide film 4, a thin oxide film 7 is formed again, and silicon nitride n8 is grown on this oxide film 7. Next, the silicon nitride film 8 is patterned by dry etching using the photoresist as a mask, and then the photoresist is removed.

Next, as shown in FIG. 1(c), using the silicon nitride film 8 as a mask, the epitaxial layer is oxidized to form a thick field oxide film 9.

Next, as shown in FIG. 1(d), after removing the silicon nitride film 8 and the oxide film 7, using the photoresist film 10 as a mask, a P-type impurity, such as boron, is applied at an accelerating voltage E-=
The P-type base region 1 of the NPN transistor was
form 1.

Next, as shown in FIG. 1(e), the photoresist film 10
After removing, a polycrystalline silicon layer 12 is grown on the entire surface,
After growing a silicon nitride film 8A on this, the silicon nitride film 8A is patterned using a photoresist as a mask. Next, after removing the photoresist, the polycrystalline silicon layer 12 is oxidized using the silicon nitride film 8A as a mask to form an oxide film 14, and the polycrystalline silicon layer 12 is separated by this oxide film 14.

Next, as shown in FIG. 1(f), after removing the silicon nitride film 8A, using the oxide film 14 and the photoresist as a mask, a P-type impurity such as boron is diffused into a P-type impurity layer 15A for contact. .

15B is formed. Similarly, the P-type impurity layer 15A.

An N-type anode region 16 in contact with the P-type cathode region 6 is formed by masking the upper surface of the N-type anode region 15B and diffusing an N-type impurity, for example, phosphorus.
A is formed to form a constant voltage diode, and at the same time, an N-type emitter region 16 of an NPN transistor is formed in the P-type base region 11.

As shown in FIG. 1(g) below, the polycrystalline silicon layer 12
After forming, for example, a platinum film 17 thereon, an oxide film 18 is formed, through holes are formed at desired locations, and then electrodes 19 are formed to complete the semiconductor device.

As described above, according to the first embodiment, by forming the cathode region of the constant voltage diode to have a lower impurity concentration than the element isolation layer, the junction of the anode region becomes deeper.
Leakage from the constant voltage diode becomes extremely low.

FIGS. 2(a) to 2(f) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention.

As shown in FIG. 2 (a), N is added to the P-type semiconductor substrate 1 by processing in the same manner as in the first embodiment shown in FIG. 1 (a).
A + type buried layer 2 is formed, and an N type epitaxial layer 3 is formed.
After growing, an oxide film 4 is formed on the surface by thermal oxidation. Next, after forming an opening in this oxidized PLA4, a P-type impurity is introduced and forced oxidation is performed to form a P-type element isolation layer 5 and a P-type cathode region of a constant voltage diode having an impurity concentration lower than this P-type element isolation layer 5. form 6.

Next, as shown in FIG. 2(b), after removing a part of the oxide film 4 by photolithography, using this oxide film 4 as a mask, a P-type impurity, such as boron, is applied at an accelerating voltage of 30 keV.
Ion implantation is performed at a dose of 8.times.10" cm.sup.-2 to form a P-type base region 11A of an NPN transistor.

Next, as shown in FIG. 2(c), after removing the entire oxide film 4, a thin oxide film 7A and a silicon nitride film 8B are sequentially formed, and then silicon nitride M8B at a desired position is removed by photolithography. do. Next, by photolithography again,
Oxidized M7A under silicon nitride film 8B is removed only in the portion where an N-type impurity region is to be formed.

Next, as shown in FIG. 2(d), a polycrystalline silicon layer 12
After growing A on the entire surface, for example, arsenic is added as an N-type impurity at an acceleration voltage of 70keV and a dose of N I X 101.
Ion implantation is performed under the condition of 6 cm-2.

Next, as shown in FIG. 2(e), heat treatment is performed for 30 minutes in an N2 atmosphere at, for example, 950°C to form the N-type emitter region 26 of the NPN transistor and the N-type anode region 26A of the constant voltage diode. , in a zero-order process in which the polycrystalline silicon layer 12A on these N-type impurity regions is left and the rest is removed.
For example, the oxide film 7A in the portion where the silicon nitride film 8B has been removed is removed using a liquid such as fluorine.

Thereafter, as shown in FIG. 2(f), one electrode is formed on the P-type impurity region and the polycrystalline silicon layer to complete the semiconductor device.

In the second embodiment as well, since the junction in the anode region is deep, leakage from the constant voltage diode is reduced. Furthermore, the first embodiment has the advantage that it is simpler than the first embodiment.

〔Effect of the invention〕

As explained above, in the present invention, after forming the element MJW,
By forming the first region of the constant voltage diode at a lower impurity concentration than the element isolation layer, the junction of the second region of the constant voltage diode, which is formed simultaneously with the emitter region of the bipolar transistor through the polycrystalline silicon layer, can be made deeper. Since it can be formed, it has the effect of eliminating leakage from the constant voltage diode.

[Brief explanation of the drawing]

1 and 2 are cross-sectional views of a semiconductor chip for explaining first and second embodiments of the present invention, and FIG. 3 is a cross-sectional view of a conventional semiconductor device. 1...P type semiconductor substrate, 2...N+ type buried layer 3.
...N-type epitaxial layer, 4...oxide film, 5...
P-type element isolation layer, 6...P-type cathode region, 7, 7A
...Oxide film, 8.8A, 8B...Silicon nitride film, 9
... Field oxide film, 10... Photoresist film, 11° 11A... P-type base region, 12.12A.
...Polycrystalline silicon layer, 14...Oxide film, 15A, 1
5B... P-type impurity layer, 16... N-type emitter region, 16A... N-type anode region, 17... Platinum film,
18... Oxide film, one... electrode, 26... N type emitter region, 26A... N type anode region.

Claims (1)

[Claims] forming an epitaxial layer of opposite conductivity type on a semiconductor substrate of one conductivity type, and then forming an element isolation region of one conductivity type in the epitaxial layer; A step of forming a first region of a voltage diode and a base region of one conductivity type of a bipolar transistor, and a step of forming a polycrystalline silicon layer over the entire surface, and then implanting ions of an opposite conductivity type impurity through the polycrystalline silicon layer; A method of manufacturing a semiconductor device, comprising: forming a second region in contact with the region and simultaneously forming an emitter region in the base region.