JPH01183149A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01183149A JPH01183149A JP875488A JP875488A JPH01183149A JP H01183149 A JPH01183149 A JP H01183149A JP 875488 A JP875488 A JP 875488A JP 875488 A JP875488 A JP 875488A JP H01183149 A JPH01183149 A JP H01183149A
- Authority
- JP
- Japan
- Prior art keywords
- type impurity
- impurity layer
- polysilicon
- oxide film
- voltage diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 239000012535 impurity Substances 0.000 claims abstract description 61
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 229920005591 polysilicon Polymers 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 18
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 238000009413 insulation Methods 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関し、特に高速バイ
ポーラＩＣにおいて定電圧ダイオードに関する製造方法
である。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a constant voltage diode in a high-speed bipolar IC.
従来の技術としては、絶縁分離に用いたＰ型拡散層内に
ポリシリコンを通してＮ型不純物をＮＰＮトランジスタ
のエミッタ拡散と同時に形成してＰＮ接合の定電圧ダイ
オードを作っている。As a conventional technique, a PN junction constant voltage diode is produced by simultaneously forming an N-type impurity through polysilicon in a P-type diffusion layer used for insulation isolation and diffusing the emitter of an NPN transistor.
前述した、従来の定電圧ダイオードの製造方法で、高速
トランジスタのエミッタと同時に定電圧ダイオードを作
る場合、カソードのＰ型不純物層の濃度が高い為、ポリ
シリコンを通してＮＰＮ）ランジスタと同時に作る定電
圧パイオードのアノードのＮ型不純物層は、ＮＰＮ）ラ
ンジスタのエミッタより接合が浅くなり定電圧ダイオー
ドのリークが生じやすくなる欠点が有る。Using the conventional method for manufacturing a constant voltage diode described above, when making a constant voltage diode at the same time as the emitter of a high-speed transistor, because the concentration of the P-type impurity layer at the cathode is high, the constant voltage diode is made at the same time as an NPN transistor through polysilicon. The N-type impurity layer of the anode has a shallower junction than the emitter of the NPN transistor, which has the disadvantage that leakage from the constant voltage diode is likely to occur.
上述した従来の定電圧ダイオードの製造方法で、絶縁分
離のＰ型不純物層内に、ポリシリコンを通してＮＰＮ）
ランジスタとのエミッタと同時にＮ型不純物層を形成す
る場合、絶縁分離のＰ型不純物濃度が高い為、定電圧ダ
イオードのＰ−Ｎ接合が浅く形成されるのに対し、本発
明はエミッタのＮ型不純物層を形成する前に、定電圧ダ
イオードのＮ型不純物層をポリシリコンを通して形成し
た後、再びＮＰＮ）ランジスタのエミッタ形成と同時に
、定電圧ダイオードのＮ型不純物層にＮ型不純物を拡散
するために、定電圧ダイオードのＮ型不純物層を深く形
成でき、Ｐ−Ｎ接合が深い箇所で形成できるため、ダイ
オードのリークが少なくなる製造方法であるという相違
点を有する。Using the conventional method for manufacturing a constant voltage diode described above, NPN (NPN) is passed through polysilicon into the P-type impurity layer for insulation isolation.
When an N-type impurity layer is formed at the same time as the emitter with the transistor, the P-N junction of the voltage regulator diode is formed shallowly due to the high concentration of P-type impurity in the insulation isolation. Before forming the impurity layer, the N-type impurity layer of the constant voltage diode is formed through polysilicon, and then the N-type impurity is diffused into the N-type impurity layer of the constant voltage diode at the same time as forming the emitter of the NPN transistor. Another difference is that the N-type impurity layer of the constant voltage diode can be formed deeply, and the P-N junction can be formed at a deep location, so the manufacturing method reduces leakage of the diode.
本発明は、ＮＰＮ）ランジスタのエミッタ形成前に、ポ
リシリコンを通して定電圧ダイオードのＮ型不純物層を
形成し、再びＮＰＮ）ランジスタのエミッタ形成と同時
に、定電圧ダイオードのＮ型不純物層にＮ型不純物を拡
散することにより、定電圧ダイオードのＮ型不純物層の
濃度を高く、Ｐ−Ｎ接合を深くして、定電圧ダイオード
のリークをなくす製造方法である。In the present invention, an N-type impurity layer of a constant voltage diode is formed through polysilicon before the emitter of the NPN) transistor is formed. In this manufacturing method, the concentration of the N-type impurity layer of the constant voltage diode is increased by diffusing the N-type impurity layer, and the P-N junction is deepened, thereby eliminating leakage of the constant voltage diode.
次に、本発明の製造方法について図面を参照して説明す
る。Next, the manufacturing method of the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.
Ｐ型サブストレート１にＮ＋型埋込層２を形成し、Ｎ型
エピタキシャル３を成長した後、熱酸化により、酸化膜
４を表面に形成し、酸化膜４をマ □スフにＰ型の絶
縁拡散をたとえばボロンを１０８０℃の温度で、ρＳが
１０Ω／口になるように行ない、１２００℃で押込み、
酸化を行なってＰ型絶縁拡散層５ａと定電圧ダイオード
のＰ型不純物層５ｂを形成する。〔第１図（ａ）〕
酸化膜４を除去した後、薄い酸化膜６を成長し、酸化膜
６上に窒化ケイ素膜７を成長する。この後フォトレジス
トをマスクに窒化ケイ素膜７をドライエッチでパターニ
ングした後、フォトレジストを取り除く。〔第１図（ｂ
）〕
この後、窒化ケイ素膜７をマスクに、ウェハーを酸化し
て厚い酸化膜８を形成する。〔第１図（Ｃ）〕
窒化ケイ素膜７．酸化膜６を取り除いた後、フォトレジ
スト９をマスクにしてＰ型不純物たとえば、ボロンをＥ
＝３０ＫｅＶ、Φ＝ ７．５ Ｘ １０”ｃｍ ”でイ
オン注入して１．ＮＰＮ）ランジスタのベースＰ型不純
物層１０を形成する。〔第１図（ｄ）〕この後、フォト
レジスト９を除去した後、全面にポリシリコン１１を約
８０００人成長し、この上に窒化ケイ素膜１２を成長し
た後、フォトレジストをマスクに窒化ケイ素膜１２をパ
ターニングし、フォトレジストを除去した後、窒化ケイ
素膜１２をマスクにポリシリコン１１をたとえば１００
０℃スチームで１２時間酸化して、酸化膜１３にし、酸
化膜１３でポリシリコン１１を分離する。〔第１図（ｅ
）〕
この後、フォトレジストをマスクに、窒化ケイ素膜１２
の一部を取り除き、フォトレジストを除去した後、残っ
た窒化ケイ素膜１２をマスクにＮ型付順物たとえばリン
を１０００℃で４０分拡散して、定電圧ダイオードのＰ
型不純物層５ｂとＰ−Ｎ接合を形成するＮ型不純物層１
４を形成する。After forming an N+ type buried layer 2 on a P type substrate 1 and growing an N type epitaxial layer 3, an oxide film 4 is formed on the surface by thermal oxidation, and the oxide film 4 is used as a mass to form a P type insulation layer. For example, boron is diffused at a temperature of 1080°C so that ρS is 10Ω/mouth, and then pushed at 1200°C.
Oxidation is performed to form a P-type insulating diffusion layer 5a and a P-type impurity layer 5b of a constant voltage diode. [FIG. 1(a)] After removing the oxide film 4, a thin oxide film 6 is grown, and a silicon nitride film 7 is grown on the oxide film 6. Thereafter, the silicon nitride film 7 is patterned by dry etching using the photoresist as a mask, and then the photoresist is removed. [Figure 1 (b
)] Thereafter, using the silicon nitride film 7 as a mask, the wafer is oxidized to form a thick oxide film 8. [Figure 1(C)] Silicon nitride film 7. After removing the oxide film 6, using the photoresist 9 as a mask, a P-type impurity such as boron is added to the E
Ion implantation was performed at =30KeV and Φ=7.5 x 10"cm".1. A base P-type impurity layer 10 of the (NPN) transistor is formed. [FIG. 1(d)] After this, after removing the photoresist 9, about 8,000 layers of polysilicon 11 are grown on the entire surface, and after growing a silicon nitride film 12 on this, a silicon nitride film is grown using the photoresist as a mask. After patterning the film 12 and removing the photoresist, the polysilicon 11 is coated with, for example, 100 nm using the silicon nitride film 12 as a mask.
Oxidation is performed using 0° C. steam for 12 hours to form an oxide film 13, and the polysilicon 11 is separated by the oxide film 13. [Figure 1 (e
)] After this, using the photoresist as a mask, the silicon nitride film 12 is
After removing a part of the photoresist, using the remaining silicon nitride film 12 as a mask, an N-type additive, such as phosphorus, is diffused at 1000°C for 40 minutes to form the P of the constant voltage diode.
N-type impurity layer 1 forming a P-N junction with type impurity layer 5b
form 4.
〔第１図（ｆ）〕
この後、酸化してＮ型不純物層１４上に酸化膜１５を形
成した後、同様にフォトレジストをマスクに窒化ケイ素
膜１２の一部を取り除いた後、フォトレジストを除去し
、窒化ケイ素膜１２と酸化膜１５をマスクにＰ型不純物
たとえばボロンを拡散し、酸化してＰ型不純物層１ｂと
酸化膜１７を形成した後、同様な方法で、窒化ケイ素膜
１３の一部とＮ型不純物層１４上の酸化膜１５を取り除
いた後、Ｎ型不純物たとえばリンを９８０℃で３０分拡
散してＮＰＮ）ランジスタのエミッタであるＮ型不純物
層１８を形成すると供に、定電圧ダイオードの７ノード
であるＮ型不純物層１４にリンを拡散して、Ｎ型不純物
層１４０表面濃度を高くしかつ、接合を深くする。〔第
１図（ｇ）〕この後、窒化ケイ素膜１３を取り除き、所
望のポリシリコン上の酸化膜を取り除き、ポリシリコン
１１上に高融点金属たとえば白金１９を形成した後、Ｃ
ＶＤ法で、酸化膜２０を形成し、所望の箇所にスルーホ
ールを形成した後、電極２１を形成する〔第１図（ｈ）
〕
第２図は、本発明の実施例２の縦断面図である。[FIG. 1(f)] After this, after oxidizing to form an oxide film 15 on the N-type impurity layer 14, a part of the silicon nitride film 12 is similarly removed using the photoresist as a mask, and then the photoresist is removed. After removing the silicon nitride film 12 and the oxide film 15 as a mask, a P-type impurity such as boron is diffused and oxidized to form the P-type impurity layer 1b and the oxide film 17. After removing a part of the oxide film 15 on the N-type impurity layer 14, an N-type impurity such as phosphorus is diffused at 980° C. for 30 minutes to form the N-type impurity layer 18 which is the emitter of the NPN transistor. , phosphorus is diffused into the N-type impurity layer 14, which is the seventh node of the constant voltage diode, to increase the surface concentration of the N-type impurity layer 140 and deepen the junction. [FIG. 1(g)] After this, the silicon nitride film 13 is removed, the desired oxide film on the polysilicon is removed, and a high-melting point metal such as platinum 19 is formed on the polysilicon 11.
After forming an oxide film 20 using the VD method and forming through holes at desired locations, electrodes 21 are formed [Fig. 1 (h)
] FIG. 2 is a longitudinal sectional view of Example 2 of the present invention.
〔第１図（ａ）〕と同様にＰ型サブストレート２２にＮ
＋型埋込層２３を形成し、Ｎ型エピタキシャル２４を成
長した後、熱酸化により酸化膜２５を表面に形成し、酸
化膜２５をマスクに、Ｐ型の絶縁拡散を、たとえばボロ
ンを１０８０℃の温度で、ρＳが１０Ω／口になるよう
に行ない１２００℃で押込み、酸化を行なってＰ型絶縁
拡散層２６ａと定電圧ダイオードのＰ型不純物層２６ｂ
を形成する。〔第２図（ａ）〕
この後、酸化膜２５の一部をフォトリソグラフィで取り
除屋た後、酸化膜２５をマスクに、Ｐ型不純物たとえば
ポロンをＥ＝３０ＫｅＶ、Φ＝８ Ｘ １０１４ｃｍ、
２でイオン注入しＮＰＮ）ランジスタのベースであるＰ
型不純物層２７を形成する。Similarly to [Fig. 1(a)], N is attached to the P-type substrate 22.
After forming the +-type buried layer 23 and growing the N-type epitaxial layer 24, an oxide film 25 is formed on the surface by thermal oxidation, and using the oxide film 25 as a mask, P-type insulation is diffused, for example, by boron at 1080°C. The P-type insulating diffusion layer 26a and the P-type impurity layer 26b of the constant voltage diode are formed by pressing at 1200°C and oxidizing them at a temperature of
form. [FIG. 2(a)] After that, a part of the oxide film 25 is removed by photolithography, and then, using the oxide film 25 as a mask, a P-type impurity, such as poron, is applied at E=30 KeV, Φ=8×1014 cm,
2, the ions are implanted to form the base of the NPN) transistor.
A type impurity layer 27 is formed.
〔第２図（ｂ）〕
この後、酸化膜２５を全面除去した後、薄い酸化膜２８
を形成した後、酸化膜２８上に窒化ケイ素膜２９を成長
し、フォトリソグラフィでコンタクト形成する箇所の窒
化ケイ素膜２９を除去した後、再びフォトリングラフィ
でＮ型不純物層を形成する部分のみ酸化膜２８を取り除
く。〔第２図（Ｃ）〕
この後、ポリシリコン３０を約１５００入金面成長した
後、ポリシリコン３０上にＣＶＤ酸化膜３１を約５００
０人成長する。この後フォトリングラフィで定電圧ダイ
オードのＰ型不純物層２６ｂ上の窒化ケイ素膜２９と酸
化膜２８を取り除いである部分のポリシリコン３０上の
ＣＶＤ酸化膜３１を取り除いた後、ＣＶＤ酸化膜３１を
マスクにＮ型不純物たとえばリンを１０００℃３０分拡
散し定電圧ダイオードのカソードであるＮ型不純物層３
２を形成する。〔第２図（ｄ）〕
この後、ＣＶＤ酸化膜３１を取り除いた後、ポリシリコ
ン３０にＮ型不純物たとえばヒ素を全面にＥ＝７０Ｋｅ
Ｖ、Φ＝ Ｉ Ｘ １０１６ｃｍ−２の条件でイオン注
入した後、たとえば９５０℃Ｎ２雰囲気中で３０分熱処
理して、ＮＰＮ）ランジスタのエミッタであるＮ型不純
物層３３を形成すると供に、定電圧ダイオードのＮ型不
純物層３２にヒ素を拡散するため、Ｎ型不純物層３２０
表面濃度を高くし、かつ接合を深くする。〔第２図（ｅ
）〕この後、フォトリソグラフィでＮ型不純物層３２と
Ｎ型不純物層３３上にポリシリコン３０ａを残す様に、
他のポリシリコン３０を取り除いた後、たとえばフッ酸
等の液で窒化ケイ素膜２９が取り除いである部分の酸化
膜２８を取り除く。[FIG. 2(b)] After that, after removing the entire oxide film 25, a thin oxide film 28 is removed.
After forming the silicon nitride film 29, a silicon nitride film 29 is grown on the oxide film 28, and after removing the silicon nitride film 29 at the location where the contact is to be formed by photolithography, only the part where the N-type impurity layer will be formed is oxidized again by photolithography. Remove membrane 28. [FIG. 2(C)] After this, about 1,500 layers of polysilicon 30 are grown on the deposited surface, and then about 500 layers of CVD oxide film 31 is grown on the polysilicon 30.
0 people grow. Thereafter, the silicon nitride film 29 and oxide film 28 on the P-type impurity layer 26b of the constant voltage diode were removed by photolithography, and the CVD oxide film 31 on the polysilicon 30 in a certain area was removed. An N-type impurity layer 3, which is a cathode of a constant voltage diode, is formed by diffusing an N-type impurity, such as phosphorus, at 1000°C for 30 minutes on a mask.
form 2. [FIG. 2(d)] After that, after removing the CVD oxide film 31, an N-type impurity such as arsenic (E=70Ke) is applied to the entire surface of the polysilicon 30.
After ion implantation under the conditions of V, Φ= I In order to diffuse arsenic into the N-type impurity layer 32 of the diode, the N-type impurity layer 320 is
Increase the surface concentration and deepen the bond. [Figure 2 (e
)] After this, the polysilicon 30a is left on the N-type impurity layer 32 and the N-type impurity layer 33 by photolithography.
After removing the other polysilicon 30, the portion of the oxide film 28 where the silicon nitride film 29 has been removed is removed using a liquid such as hydrofluoric acid.
〔第２図（ｆ）〕
この後、電極３４をＰ型不純物層上とポリシリコン３０
ａ上に形成する。〔第２図（ｇ）〕〔発明の効果〕
以上説明したように本発明は、ＮＰＮ）ランジスタのエ
ミッタのＮ型不純物層を形成する前に、定電圧ダイオー
ドのＮ型不純物層をポリシリコンを通して形成した後、
再びポリシリコンを通してＮＰＮ）ランジスタのエミッ
タ形成と同時に、定電圧ダイオードのＮ型不純物層にＮ
型不純物を拡散するために、定電圧ダイオードのＮ型不
純物層を深く形成でき、Ｐ−Ｎ接合が深い箇所で形成さ
れるため、定電圧ダイオードのリークが少なくなる効果
がある。[FIG. 2(f)] After this, the electrode 34 is connected to the P-type impurity layer and the polysilicon 30.
Form on a. [Figure 2 (g)] [Effects of the Invention] As explained above, the present invention has the advantage of forming the N-type impurity layer of the constant voltage diode through polysilicon before forming the N-type impurity layer of the emitter of the NPN transistor. After forming,
At the same time as forming the emitter of the transistor (NPN) through the polysilicon again, the N-type impurity layer of the constant voltage diode is
In order to diffuse type impurities, the N-type impurity layer of the constant voltage diode can be formed deeply, and the PN junction is formed at a deep location, which has the effect of reducing leakage of the constant voltage diode.
り
第１図（ａ）〜（勇）は、本発明の第１の実施例、第２
図（ａ）〜（ｇ）は、第２の実施例の縦断面図である。
１．２２・・・・・・Ｐ型サブストレート、２．２３・
・・・・・Ｎ＋埋込層、３．２４・・・・・・Ｎ型エピ
タキシャル、４．６，８，１３，２０，２５，２８．３
１・・・・・・酸化膜、５ａ、５ｂ、１０，１６．２６
ａ、２６ｂ、２７・・・・・・Ｐ型不純物層、７，１２
．２９・・・・・・窒化ケイ素膜、１４．１８，３２．
３３・・・・・・Ｎ型不純物層、９・・・・・・フォト
レジスト、１１，３０゜３０ａ・・・・・・ポリシリコ
ン、１９・・・・・・白金、２１゜３４・・・・・・電
極。
代理人 弁理士 内 原 晋Figures 1(a) to 1(b) show the first embodiment and the second embodiment of the present invention.
Figures (a) to (g) are longitudinal sectional views of the second embodiment. 1.22...P-type substrate, 2.23.
...N+ buried layer, 3.24...N type epitaxial, 4.6, 8, 13, 20, 25, 28.3
1... Oxide film, 5a, 5b, 10, 16.26
a, 26b, 27... P-type impurity layer, 7, 12
．． 29...Silicon nitride film, 14.18,32.
33... N-type impurity layer, 9... Photoresist, 11, 30° 30a... Polysilicon, 19... Platinum, 21° 34... ····electrode. Agent Patent Attorney Susumu Uchihara
Claims (1)
を形成する工程と、トランジスタのベースである第２の
第２導電型不純物層を形成する工程とポリシリコンを形
成する工程と、ポリシリコンを通して第１の第２導電型
不純物層内に第１導電型不純物層を形成する工程と、ポ
リシリコンを通して前記第１導電型不純物層と、第２の
第２導電型不純物層内に同時に第１導電型不純物層を形
成する工程を含むことを特徴とする半導体装置の製造方
法。a step of forming a first second conductivity type impurity layer on a first conductivity type semiconductor substrate; a step of forming a second second conductivity type impurity layer serving as a base of the transistor; and a step of forming polysilicon; forming a first conductivity type impurity layer in the first second conductivity type impurity layer through the polysilicon; and simultaneously forming the first conductivity type impurity layer and the second second conductivity type impurity layer through the polysilicon; A method for manufacturing a semiconductor device, comprising the step of forming a first conductivity type impurity layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63008754A JPH07120711B2 (en) | 1988-01-18 | 1988-01-18 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63008754A JPH07120711B2 (en) | 1988-01-18 | 1988-01-18 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01183149A true JPH01183149A (en) | 1989-07-20 |
| JPH07120711B2 JPH07120711B2 (en) | 1995-12-20 |
Family
ID=11701714
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63008754A Expired - Lifetime JPH07120711B2 (en) | 1988-01-18 | 1988-01-18 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07120711B2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59161060A (en) * | 1982-12-20 | 1984-09-11 | レイセオン カンパニ− | Method of producing semiconductor device |
-
1988
- 1988-01-18 JP JP63008754A patent/JPH07120711B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59161060A (en) * | 1982-12-20 | 1984-09-11 | レイセオン カンパニ− | Method of producing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07120711B2 (en) | 1995-12-20 |
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