JPS60137036A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the resistance of a collector without lowering with-standing voltage between a collector and a base, and the collector and an emitter by diffusing a reverse conduction type impurity from first and second impurity diffusing window regions and connecting the diffusion regions through all openings. CONSTITUTION:An SiO2 film 2 is formed extending over the whole region of the surface of a P<-> type silicon substrate 1. A large number of fine striped openings 3 are formed in a region B, and wide openings 4 are shaped in regions C. Phosphorus is evaporated on the surfaces of the silicon substrates exposed into the openings, and phosphorus is diffused in an oxidizing atmosphere. Diffusion regions for phosphorus formed through several opening are all connected. The SiO2 films on the silicon substrate are all removed, and an N<-> type epitaxial layer is grown on the silicon substrate. The whole region on the silicon substrate is coated with an SiO2 film again. An N<+> type collector wall diffusion region, a P type base region and an N<+> type emitter region are thus formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit suitable for manufacturing a semiconductor integrated circuit incorporating a power transistor.

Conventional Structures and Their Problems In recent years, active efforts have been made to increase the power output of semiconductor integrated circuits, and various power semiconductor integrated circuits with built-in power transistors have appeared.

By the way, in order to further improve the output characteristics of this power semiconductor integrated circuit, it is necessary to increase the saturation voltage (VCE sat) between the collector and emitter of the integrated power transistor.
) is important, and therefore the collector resistance of the power transistor needs to be a small value.

One way to reduce the value of this collector resistance is to
There is a method in which a buried collector region with a high impurity concentration is created and a power transistor is formed on top of this. However, when this method is adopted, the epitaxial growth step after forming the buried collector region,
During the heat treatment in the process of forming the contact diffusion region (collector all diffusion region) in the buried collector region V (dj14) or in the process of forming the base and emitter regions, impurities in the buried collector region are diffused deeply into the epitaxial layer, and the effective The thickness of the epitaxial layer decreases.Therefore, in a power transistor that uses this epitaxial layer as a collector region, the collector-base breakdown voltage (Vcno
) and collector-emitter open surface/1 pressure (Vcxo)
The problem of deterioration is derived.

OBJECTS OF THE INVENTION It is an object of the present invention to
11 pressure (Vcao) and collector-emitter surface j
An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit that can reduce the value of collector resistance without reducing the pressure (vCRO) fa=0.Structure of the Invention The method for manufacturing a semiconductor integrated circuit of the present invention includes - A first impurity diffusion window region in which a large number of minute openings are arranged adjacent to each other in a 7'J'r constant portion of an impurity diffusion mask layer covering a conductive type semiconductor substrate, and a first impurity diffusion window region; A second window region for impurity diffusion is formed adjacent to the window region and has a larger opening area than the micro-aperture, and then, from the first and second window regions for impurity diffusion, a window region of the opposite conductivity type is formed. After expanding the impurity and forming a buried collector region in which the diffusion regions formed through all of the openings are connected, an epitaxial layer of the same conductivity type as the Ji14-containing collector region is grown on the semiconductor substrate. Thereafter, the epitaxial layer is separated into islands to form epitaxial island regions, and at least transistors are built into the epitaxial island regions. According to the method for manufacturing a semiconductor integrated circuit of the present invention, the diffusion depth and impurity concentration of the buried collector region are shallow and low in the portion corresponding to the first impurity diffusion window region, while in the second The area corresponding to the impurity diffusion window becomes deeper and higher. Therefore, if the base region of the transistor is connected to the former part and the entire collector-all diffusion region is connected to the latter part, it becomes possible to fabricate a high-performance power transistor.

11. Explanation of the semiconductor integrated circuit according to the present invention, by making the opening formed in the impurity diffusion mask smaller, the diffusion depth of the formed impurity diffusion region becomes shallower. This is based on the knowledge that the concentration decreases, and this fact is applied to the formation of a buried collector region that is embedded in a semiconductor integrated circuit to reduce the concentration by 1/1. The present invention aims to realize a semiconductor integrated circuit having a power transistor with a high capacity.

An example of the method for manufacturing a semiconductor integrated circuit according to the present invention will be described below with reference to all the drawings.

Figures 1 to 5 are manufacturing process diagrams showing only the transistor formation of a semiconductor integrated circuit (15 minutes) in an enlarged manner. Silicon dioxide (Sin) serves as a mask for impurity diffusion.
) A film 2 is formed to a predetermined thickness (FIG. 1).

Next, an opening for diffusing impurities for forming a buried collector region is formed in 510211i4 by a well-known photolithography method, and as shown in FIG. The first region BE is divided into a first region B and a second region C, and the first region BE has a large number of fine stripe-shaped openings 3 with a width of, for example, about 2 μm, while the second region has, Form a wide opening 1 and 4. After forming the openings in this way, phosphorus is evaporated onto the silicon substrate m exposed in these openings by using, for example, phosphorus oxychloride (P4O10) as an impurity source and passing a carrier gas through the impurity source. The phosphorus is applied at a temperature of approximately 925°C, and the phosphorus is further expanded in an oxidizing atmosphere at 1200°C.

FIG. 3 is a diagram showing the state after phosphorus has been diffused. The phosphorus diffusion regions formed through the individual openings are all connected, and the first region B is filled with impurities. The N-type diffusion region 5 has a relatively low impurity concentration and a shallow diffusion depth, and the N-type diffusion region 5 has a relatively high impurity concentration and a deep diffusion depth in the second region C. A diffusion region 6 is formed. That is, N+J cedar diffusion region 5 and N
A buried collector region integrated with the l-+ type diffusion region 6 is formed. Next, after removing all of the 8102 film on the silicon substrate, the epitaxial layer 7 of N)(f) is removed.
is grown on a silicon substrate (Figure 4). This N-type epitaxial layer is selected to have a thickness of 20 μm and a resistivity of 2.0 Ω·C111, for example.

After the above process, the entire area on the silicon substrate is covered with Si.
After spinning with the O□ film, formation of an insulating isolation diffusion region (not shown) for separating the N-type epitaxial layer 7 into island shapes'fJ:
After that, the N type collector all diffusion region 8, the P type base region 9 and the N1 type emitter region 1 shown in FIG. By forming electrodes 11, 12 and 13 in the region, the fabrication of the transistor is completed. In addition, in the figure, 14 is a 5102 film. In the transistor thus formed, the impurity in the N+ type buried collector region portion 6 located directly under the P type base region 9 is
Although it diffuses into the epitaxial layer, its diffusion length is short. Therefore, the amount of decrease in the effective epitaxial layer thickness is small, and the thickness of the collector region directly under the P-type base region 9 becomes sufficient.

Incidentally, in the above embodiments, the shape of the fine openings is exemplified as a stripe shape, but the shape is not limited to this shape, and may be, for example, a lattice shape. It's a trench.
The method of vapor deposition of impurities is not limited to the above example, and may be replaced by a spin-on method or the like.

Effects of the Invention According to the method for manufacturing a semiconductor integrated circuit of the present invention, the amount of back-diffusion from the buried collector region located directly under the base region into the epitaxial layer can be suppressed to a small level, and the required impurity concentration can be reduced. A collector region can be formed. Therefore, in order to reduce collector abrasive resistance and lower collector saturation voltage, collector-base withstand voltage (Vcgo) and collector-emitter #1 voltage (Vcx
It becomes possible to manufacture a transistor that prevents a decrease in o).

Particularly, the production of power transistors - If the manufacturing method of the present invention is used, it is possible to make the power transistors high-performance, and as a result, it is possible to realize high-performance semiconductor integrated circuits. .

[Brief explanation of drawings]

11th to 5 are manufacturing process diagrams showing the process of manufacturing a transistor into a semiconductor integrated circuit by the manufacturing method of the present invention. 1-...P-J cedar silicon substrate, 2.14...
Silicon dioxide film, 3, 4...Opening for impurity diffusion, 6...N-type buried diffusion region, 6...N
++-type buried diffusion region, 7..."type epitaxial layer, 8...N-type collector wall diffusion region, 9.
...P-type base region, 1o...N'') Cedar emitter region, 11-13...electrode. J-!J! Person's name Patent attorney Toshio Nakao and 1 other person Figure 1 Figure 2 Figure 4 Figure 5

Claims (2)

[Claims] (1) A large number of minute openings are arranged adjacent to each other in a predetermined portion of an insulating film covering a semiconductor substrate of one conductivity type, and a first window region for impurity diffusion is adjacent to the first window region for impurity diffusion. At the same time, a second impurity diffusion window region having an opening surface In larger than the minute opening is formed, and impurities of opposite conductivity type are diffused from the first and second impurity diffusion window regions to form the opening. forming a buried collector region in which diffusion regions formed through all of 1. A method of manufacturing a semiconductor integrated circuit, comprising: forming an epitaxial island region, and manufacturing at least a transistor in the epitaxial island region. (2) The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein the micro opening has a stripe shape.