JPH02246223A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To decrease capacitance formed around base region by forming an outer base region only on one side of an inner base region. CONSTITUTION:A reverse conductivity type inner base region 17 is formed in a surface region 13 by ion implantation and the like in self-alignment with a pair of film regions 25 and 29. A pair of insulating regions 21a and 21b are formed on the side wall. Thereafter, an emitter lead-out region 23 containing impurities is formed. Impurities formed by ion implantation is activated by heat treatment. The impurities are diffused into the lower semiconductor surface region from one film region 25 and the emitter lead-out region 23. Thus an outer base region 27 and an emitter region 19 are formed. Therefore, an outer base region 27 is formed only on the right side of the inner base region 17 and is not formed on the left side of the inner base region 17. Since capacitance between the outer base region and a collector can be reduced to about 1/2, the total capacitance around the base region can be reduced to about 1/2.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a bipolar semiconductor device with reduced base-collector capacitance, an object of the present invention is to provide a method for manufacturing a semiconductor device that can further reduce the capacitance associated with the base region. The purpose is to form an extraction electrode layer on the entire surface of a region to become a base on a semiconductor substrate of one conductivity type, and to form an extraction electrode layer on the region to become a base! selectively introducing an opposite conductivity type impurity into a part of the layer, and selectively removing the extraction electrode layer to separate the extraction electrode layer from a region containing the opposite conductivity type impurity to a region not containing the impurity. a step of forming an internal base window separating the internal base region from the internal base window; a step of introducing an impurity of opposite conductivity type from the internal base window to form an internal base region; and a step of introducing an impurity of one conductivity type into the internal base region. forming an emitter region, diffusing an opposite conductivity type impurity from the separated extraction electrode layer containing an opposite conductivity type impurity into the semiconductor substrate, and forming an emitter region between the extraction electrode layer containing the opposite conductivity type impurity and the The structure is configured to form an external base region connecting the internal base regions.

[Industrial Field of Application] The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a bipolar semiconductor device with reduced base-collector capacitance.

In recent years, with the demand for high-speed data processing, there has been a desire to develop computers that perform high-speed arithmetic processing. There is a demand for the development of high-speed bipolar transistors for use in high-speed computers and the like.

[Prior art] Figures 2 (A) and (B) show ESPER (E
mitter-base Self-aligned
with Polysilicon Elect
rodes and Re51st.

rs) shows the main parts of a semiconductor device with a structure.

2(A) shows a cross-sectional structure, and FIG. 2(B) shows a schematic circuit diagram. In FIG. 2(A), an n-type impurity is diffused into the surface of a p-type silicon substrate 115. to form an n+ type buried region, and an n- type epitaxial layer 113 is formed thereon.
grow. A field oxide film 111 is formed on the surface of the n-type epitaxial layer 113 to define an element region.

A base extraction region 125 of polycrystalline silicon (polySt) is formed on the substrate surface to serve as an external base diffusion source.
An opening is provided therein defining an internal base region 117. P-type impurity ions are implanted into this opening to define an internal base region 117. Thereafter, insulator regions 121a and 121b are formed on the side walls of the opening to narrow the opening area and define a region where the emitter region 119 is to be formed.

An emitter lead-out region 123 of polycrystalline silicon, which will serve as an emitter region diffusion source, is deposited on this. Emitter extraction region 123 is doped with n-type impurities, base extraction region 12
5 is doped with a p-type impurity.

Thereafter, heat treatment is performed to activate and diffuse impurities, thereby forming an emitter region 119, an internal base region 117 surrounding it, and an external base region 127 continuous to the outside of the internal base region 117. A polycrystalline silicon emitter lead region 123 is connected to the emitter region 119, and a polycrystalline silicon base lead region 125 is connected to the emitter region 119.
is connected to the top surface of external base region 127. An insulator region 12 is provided between the polycrystalline silicon emitter extraction region 123 and the polycrystalline silicon base extraction region 125.
1 a and 12 l b are interposed to prevent a short circuit between the picture electrodes.

As shown in FIG. 2(B), consider the equivalent circuit of such a structure with respect to the base region.

Considering the resistance, the resistance R3 of the polycrystalline silicon base extraction region 125 on both sides of the emitter is connected to the resistance R2 of the external base region 127, and the resistance R2 of the external base region 127 is connected to the resistance R1 of the internal base region 117. Connected.

If the base electrode is formed on the right side of the figure, the resistor R3 of the base extraction region 125 on the left side will further be connected to the base electrode via a resistor R4. The resistance associated with the base region has become sufficiently low due to the adoption of self-aligned structures, and the capacitance associated with the base region is now becoming more of a problem.

The p-type internal base region 117 and the external base region 127 form a pn junction with the n-'' type epitaxial layer (collector region), and accordingly have a junction capacitance.Bipolar type having an internal base region and an external base region In a semiconductor device, the capacitance associated with the base region is the sum of the capacitance associated with the internal base region and the capacitance associated with the external base region.The junction capacitance between the internal base region 117 and the collector region is assumed to be C6BIN, and the external base region 127 The junction capacitance between the base region and the collector region is expressed as C6BEX, and the internal base region 117 has a small area and a low impurity concentration.
The external base region 127 has a large area and a high impurity concentration, so the capacitance C6 associated with the external base region 127
BEX is the capacitance C6B associated with the internal base region 117
much larger than IN, therefore, the capacitance associated with the base region is mainly the capacitance associated with the external base region CCB
Determined by EX.

The larger capacitance associated with the base area means more time to charge through the load and slower operating speed.

Therefore, it is preferable that the capacitance associated with the base region of a bipolar semiconductor device be as small as possible.

[The problem that invention solves! I! ] As explained above, according to the prior art, a polycrystalline silicon film is buttered to form an internal base region, is used as an impurity diffusion source, an external base region is formed thereunder, and this external base region The capacitance associated with the base region occupies a major portion of the capacitance associated with the base region.

It is desirable to further reduce the total capacitance associated with this base region.

An object of the present invention is to provide a method of manufacturing a semiconductor device that can further reduce the capacitance associated with the base region.

[Measures to Solve the Problem] According to the present invention, a pair of layer regions are formed facing each other on the surface of a semiconductor substrate, self-aligned between them to form an internal base region, and only one of the layer regions is formed. An external base region is formed thereunder by diffusion using as an impurity diffusion source, but no impurity is added to the other layer region, that is, the external base region is provided only on one side of the internal base region.

FIGS. 1A and 1B are diagrams explaining the principle of the present invention. 1A shows a cross-sectional structure, and FIG. 1B shows a schematic perspective view of one state during the manufacturing process. In FIG. 11
is formed, and a field oxide region 11 defines a surface region 13 of one conductivity type.

A pair of layer regions 25 , 29 are arranged oppositely on the surface region 13 and define therebetween a region forming the internal base region 17 . In self-alignment with this pair of layer regions 25 and 29, an internal base region 17 of opposite conductivity type is formed in the surface region 13 by ion implantation or the like.

One of the pair of layer regions 25 and 29 contains impurities and can serve as a diffusion source, while the other 29 does not contain impurities and does not serve as a diffusion source.

After forming a pair of insulator regions 21a and 21b on opposing sidewalls of a pair of layer regions 25 and 29, an emitter extraction region 23 containing impurities is formed thereon. The heat treatment activates the ion-implanted impurities and diffuses the impurities from the one layer region 25 and the emitter extraction region 23 into the underlying semiconductor surface region, thereby forming the external base region 2.
7. Form emitter region 19.

aligned by a pair of insulator regions 21a and 21b,
An emitter region 19 of one conductivity type is formed within the internal base region 17 . The external base region 27 is formed only on the right side of the internal base region 17 and is not formed on the left side of the internal base region 17. Naturally, the external base region 27 is connected to the base extraction region 25 containing impurities, Emitter region 19 is connected to emitter extraction region 23 containing impurities.

Note that above the surface region 13 on the left side of the internal base region 17, there is a layer region 2 made of a high resistivity material that is made of the same main component as the base extraction region 25 but is not doped with impurities.
9 remain.

In the structure of FIG. 1A, since the external base region 27 is formed only on one side, the capacitance associated with the external base region is approximately halved compared to the case where it is formed on both sides. Therefore, the capacitance associated with the base region is reduced by approximately 1/2.

During the manufacturing process for realizing such a structure, a structure as shown in FIG. 1(B) is obtained.

In FIG. 1B, a field oxide region 11 is formed on the surface of a semiconductor substrate 15 to define a surface region 13. In FIG. Above this, a layer region 29 of a high resistivity material made of the same main component and a base extraction region 25 doped with impurities are formed separately from each other. By utilizing such a configuration, an internal base region and an emitter region can be formed between both film regions in a self-aligned manner as in the prior art, and on the other hand, impurities can be diffused into the semiconductor substrate from such a base extraction region 25. By this, the internal base region 17
An external base region 27 is formed only on one side of the .

[Operation] With the structure described above, the internal base region and the emitter region are fabricated in a self-aligned manner, while the external base region exists only on one side of the internal base region, so the external base region exists on both sides of the conventional structure. Since the capacitance C3BEX between the external base region and the collector, which accounts for a large proportion of the collector-base capacitance C68, can be reduced to about 1/2 compared to the case where there is /2 can be achieved.

Therefore, the charge value for charging the base region can be small.

In addition, the reduction in base charge makes it easier to increase the speed.

[Example 1 Examples of the present invention are shown in FIGS. 3(A) to 3(F).

In FIG. 3A, n-type impurities such as As or sb are diffused into the surface of a P-type silicon substrate 31 to form an n"-type buried region 32, and then an n-type layer is epitaxially grown to form an n- A 313N4 film 34 of approximately 1000 layers is grown by CVD to form a mold layer 33 and etched into a desired pattern.Field oxidation is performed using the remaining 513N4 film 34 as a mask to form a thick oxide film 35.

The thickness of the field oxide film is, for example, about 6,000.

Next, a resist layer is formed on the surface and patterned to expose only a desired region, and n-type impurity ions are implanted to form an n+ type diffusion region in the region where the collector extraction region 40 is to be formed. Although not shown, an isolation region is formed around the element region.
The 3N4 film 34 is removed using hot phosphoric acid.

In FIG. 3(B), a polycrystalline silicon film 36 having a thickness of approximately 3000 nm is formed on the surface of the substrate. Polycrystalline SiC or the like may be used instead of polycrystalline silicon.Using a photoresist mask, unnecessary portions of this polycrystalline silicon film 36 are removed by etching. A seven-layer photoresist layer 37 is formed on the remaining polycrystalline silicon film 36 and patterned to expose only a portion of the polycrystalline silicon film 36. Using this resist layer 37 as a mask, impurity ions 38, such as boron ions B+, are applied to the surface of the semiconductor substrate.
, with an acceleration energy of about 30 KeV and a dose of 5.0X
The IO 153-2 is ion-implanted to form a polycrystalline silicon film 36 partially doped with a large amount of impurities. After that, the resist mask 37 is removed.

Note that while the polycrystalline silicon film 36 is separated, it is necessary to ensure that no impurity is added to one layer region. Also, instead of a single layer of polycrystalline silicon,
A composite layer such as a polycrystalline silicon layer that can serve as a diffusion source and a silicide layer that is a low resistance conductive layer may be used.

In FIG. 3C, an 8102 film 39 of approximately 3000 layers is formed over the entire surface of the substrate by CVD. This 810
It is desirable to form the second film 39 at a low temperature so that the impurities added to the polycrystalline silicon film 36 do not diffuse to other parts.

Next, as shown in FIG. 3(D), a photoresist layer 41 is formed over the entire surface of the semiconductor substrate. The photoresist layer 41 is exposed and patterned to form an opening 42 . Using the photoresist layer 41 having the opening 42 as a mask, the CVD 5102 film 39 and the polycrystalline silicon film 36 under the opening 42 are patterned by anisotropic etching.

This etching exposes a portion of surface region 13.

After that, the resist mask layer 41 is removed.

In FIG. 3E, about 500 thermal oxide films 44 are formed on the surface of the exposed surface region 13, and impurity ions, such as boron ions, are implanted to form internal base regions.

Next, CVD5iO□ film 45 and polycrystalline silicon film 46
is deposited continuously. For example, the CVD5102 film 45 is 1
For example, the thickness of the polycrystalline silicon film 46 is 200 mm.
Make it 0 people thick. Thereafter, anisotropic etching is performed on the entire surface to remove the polycrystalline silicon film, CvDSIO2 film, and oxide film 44 on the horizontal plane, and to remove the CVDSIO2 film 45 and polycrystalline silicon film 46 only on the side wall of the opening 42. This state is shown in FIG. 3(E).

CvDSIO2 film 45 and polycrystalline silicon film 46 on the sidewalls
A narrowed opening 42 defines an emitter region.

In FIG. 3(F), the polycrystalline silicon film 47 is
After the deposition, a large amount of arsenic As is ion-implanted into the polycrystalline silicon film 47. The conditions for ion implantation are, for example, acceleration energy of 60 KeV and 1.
OX 10 ”>-2f) dose.

Next, heat treatment is performed at, for example, 900°C for about 30 minutes.
This heat treatment activates the ion-implanted impurities. That is, the boron implanted for forming the internal base region is activated to form a p-type region.

Further, the impurities added into the polycrystalline silicon films 36 and 47 are activated and diffused in the polycrystalline silicon film,
It further diffuses into the semiconductor surface region 13. by this,
External base region 27 and emitter region 19 are formed. External base region 27 is formed deeper than internal base region 17 due to the difference in impurity concentration. Note that since no impurity is added to the polycrystalline silicon region on the left side of the emitter region 19, no external base region is formed thereunder.

Next, the polycrystalline silicon film 47 other than that used as the emitter extraction region is removed by etching.

C above base drawer area and collector drawer area
A contact opening is formed in the VDSiO2 film 39, and the polycrystalline silicon film 36 and n" type region 40 below are formed.
to expose. An aluminum film is deposited on the entire surface and patterned to form each aluminum electrode 49.

In this way, a bipolar semiconductor device is formed in which the emitter and base are self-aligned and the external base region is provided only on one side of the internal base region.

Note that in the above explanation, impurity ions were implanted into only a part of the polycrystalline silicon film 36 and then divided into two parts. Of course, all conductivity types may be reversed.

FIGS. 4(A) to (4) showing other embodiments of the present invention.
In Figure (A), field oxide JI 35 is formed to a thickness of about 6000 on the surface of a semiconductor substrate 33.

In FIG. 4(B), a thermal oxide film 52 is deposited on the surface of a semiconductor substrate 33 by approximately 500 layers, and a CVD Si3 N4 film 5 is deposited on the surface of a semiconductor substrate 33.
4 to a thickness of approximately 1500 mm.

About 3000 people deposited a polycrystalline silicon film 36 on this,
Pattern and remove unnecessary parts. Impurities are added only to a portion of the polycrystalline silicon film 36 by a process similar to that shown in FIG. 3(B). Furthermore, on top of that, CvDS102 film 39
Deposit about 3,000 people thick.

In FIG. 4(C), a photoresist is formed on the surface, a pattern is exposed, and the underlying CVD5102 film 39,
The polycrystalline silicon M36 is patterned to form an opening 42. The CVDSi3N4 film 54 and the thermal oxide film 52 are exposed at the bottom of the opening. The photoresist mask is removed.

Next, as shown in FIG. 4(D), the exposed portion of the polycrystalline silicon film 36 whose sidewalls are exposed is oxidized by thermal oxidation.
A thermal oxide film 56 of about 1,000 to 4,000 layers is formed.

Next, as shown in FIG. 4E, the 513N4 film 54 exposed on the surface of the opening is removed by etching with hot phosphoric acid, and the polycrystalline silicon film 36 is further overetched.
A horizontal hole extending approximately 0.3 to 1.0 μm below is formed. Subsequently, the exposed oxide film 52 is also removed using an etchant for oxide films. The depth of this lateral hole will define the lateral dimensions of the later formed external base region.

Next, as shown in FIG. 4(F), the polycrystalline silicon film 5
8 was deposited by low pressure CVD to fill the horizontal hole formed in FIG. 4(E). The polycrystalline silicon filling the horizontal hole is continuous with the previously formed polycrystalline silicon film 36 on the upper surface.

Next, as shown in FIG. 4(G), the polycrystalline silicon film 58 is etched by wet etching to leave only the portion 58 filling the horizontal hole and remove the rest. That is, on the right side of the opening 42, the polycrystalline silicon 56 remaining in the horizontal hole enters between the impurity-containing polycrystalline silicon film 36 and the surface of the semiconductor substrate, forming an impurity path.

Next, impurities are introduced through the opening 42 to form the internal base region 17.

Next, as shown in FIG. 4(H), the eVDsi02 film 4
5 for about 1,500 people, and polycrystalline silicon film 46 for about 2,000 people.
The layers are successively deposited, and anisotropic etching is performed on each layer to leave only the portion on the side wall of the opening 42 and remove the others. The portion of the semiconductor substrate exposed within the narrowed opening 42 defines an emitter region.

Furthermore, as shown in FIG. 4(I), a polycrystalline silicon film 4
Approximately 2,000 layers of No. 7 are deposited, and impurity ions are implanted.

Thereafter, similar to the embodiments shown in FIGS. 3(A) to 3(F), a heat treatment is performed at, for example, about 900° C. for about 30 minutes to activate the impurities and diffuse the impurities from the polycrystalline silicon film into the semiconductor. , by this heat treatment, the emitter region 19,
An external base region 27 is formed. Thereafter, unnecessary portions of the polycrystalline silicon film 47 are removed by etching.

In this embodiment, photolithography is used to form the opening 42 that defines the internal base region, but after that, the external base region is defined by controlling the etching process, reducing the number of masks and creating a finer structure. can be realized.

Although the present invention has been described with reference to embodiments, it will be obvious to those skilled in the art that the present invention is not limited to these and that, for example, various modifications, changes, combinations, etc. are possible.

[Effects of the Invention] In a semiconductor device in which an opening is provided in a film that can serve as an impurity diffusion source, such as a polycrystalline silicon film, and an internal base region and an emitter region are formed in a self-aligned manner using the opening, A film such as a polycrystalline silicon film is divided into two separate opposing layer regions, and an internal base region is defined between them, while an impurity is added only to one piece S to form an external base region only on one side of the internal base region. As a result, the capacitance associated with the base region of a fine bipolar semiconductor device can be reduced.

As the capacitance associated with the base region is reduced, a semiconductor device that can achieve higher speed and lower power consumption can be obtained.

[Brief explanation of drawings]

1(A) and (B) are diagrams explaining the principle of the present invention, FIG. 1(A) is a sectional view, FIG. 1(B) is a schematic perspective view, and FIG. ) indicates the prior art, and Fig. 2(A)
is a sectional view, FIG. 2(B) is a schematic diagram, and FIGS. 3(A) to (F)
) shows the manufacturing process of a semiconductor device according to an embodiment of the present invention, each of which is a cross-sectional view of a semiconductor substrate, and FIGS. FIG. Field oxidation region Surface region Semiconductor substrate Internal base region Emitter region Insulator region Emitter extraction region Base extraction region (layer region) External base region High resistivity material layer region P-type S1 substrate N+-type buried region N-type shrimp layer Si3N4 film field Oxide film Polycrystalline Si film Resist layer ion c v Ds+o 2 Jl n+ type collector extraction region Resist layer opening Thermal oxide film CVD5i02 film Polycrystalline Si film 121a, 12tb Aluminum electrode a Oxide film CVDSi3N4 film Thermal oxide film Polycrystalline 5ill Field oxide film N-type shrimp layer Silicon substrate Internal base region Emitter region Insulator region Poly S1 Emitter Poly 81 Base External base region Resistance capacitance (A) Cross-sectional structure R & (A) Cross-sectional structure CB) Schematic diagram (B) Schematic perspective view during the manufacturing process Diagram for explaining the principle of the present invention: Figure 1, Figure 2, (B) Formation of partially doped polycrystalline silicon film (C) CV
D S1α1 formation Figure 3 (Part 1) (C) W40 section formation j (D) Polycrystalline Si layer separation (E) Internal base region ion implantation, emitter window B formation (
F) Emitter region, external base region diffusion Figure 3 (Part 2)
) (F) Low pressure CVD CG) Etching (I) CVD, etching Other embodiments of the present invention Fig. 4 (Part 2)

Claims (1)

[Claims] (1) A step of forming an extraction electrode layer on the entire surface of a region that will become a base on a semiconductor substrate of one conductivity type, and selectively introducing an opposite conductivity type impurity into a part of the extraction electrode layer on the region that will become a base. selectively removing the extraction electrode layer to form an internal base window that separates the extraction electrode layer into a region containing the opposite conductivity type impurity and a region not containing the impurity; forming an emitter region by introducing an impurity of one conductivity type into the internal base region, and forming an emitter region by introducing an impurity of one conductivity type into the internal base An opposite conductivity type impurity is diffused into the semiconductor substrate from the extraction electrode layer containing the conductivity type impurity to form an external base region connecting the extraction electrode layer containing the opposite conductivity type impurity and the internal base region. A method for manufacturing a semiconductor device.