JPS5987856A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit the generation of a defect with the diffusion of impurities while forming a shallow junction with excellent controllability by each implanting the ions of P<+> and As<+> to a polycrystalline semiconductor layer in the specific quantities of doses and thermally diffusing P and As while using the polycrystalline semiconductor layer as diffusion source. CONSTITUTION:Sections corresponding to an emitter-region forming prearranged section and a collector-contact region forming prearranged section of a thermal oxide film 5 are removed selectively through etching, and openings 71, 72 are formed. A non-doped polycrystalline silicon layer 8 is deposited on the whole surface through a LPCVD method, and the ions of P<+> are implanted under the conditions of the quantity of a dose of 10<15>-10<16>cm<-2> and the ions of As under the conditions of the quantity of a dose of 10<12>-10<14>cm<-2> respectively. Both elements are thermally diffused in an O2 atmosphere while using the polycrystalline silicon layer 8 as the diffusion source. One part of a thermal oxide film 5 on a P type base region 6 is removed selectively through etching to form an opening 12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a shallow junction.

[Technical background of the invention and its problems]

Shallow junction formation technology is one of the technologies for achieving higher integration and higher speed of semiconductor devices.

When P is used as an impurity to form a junction, P
Since the diffusion coefficient is large, it is difficult to form shallow junctions with good control. Therefore, a shallow junction is generally formed by doping As as an impurity with a diffusion coefficient of /J\< and high solid solubility. However, As
The diffusion of is sensitive to the presence of defects, stress, e.g.
When a thick oxide film is forcibly buried in a semiconductor substrate using selective oxidation technology, arsenic will abnormally diffuse along the defects that occur at the interface between the thick oxide film and the semiconductor substrate, resulting in abnormal diffusion in bipolar transistors. Emitter-collector short circuit may occur.

Alternatively, if a method is adopted in which a polycrystalline semiconductor layer containing 9P and As is deposited on a semiconductor substrate by the CVD method, and P and A8 are simultaneously diffused into the semiconductor substrate using this polycrystalline semiconductor layer as a diffusion source. It is known that defects generated during p diffusion can be suppressed and the diffusion length of p can be suppressed due to the difference in atomic radius between the two. However, with this method, it is difficult to control the As concentration in the polycrystalline semiconductor layer, and it is difficult to form a shallow junction with a uniform junction depth in a well-controlled manner.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and it suppresses the occurrence of defects due to impurity diffusion, forms shallow junctions with good control, and increases speed.

The present invention aims to provide a method for manufacturing a semiconductor device that can achieve high integration.

When diffusing P and As from a polycrystalline semiconductor layer into a semiconductor substrate, it is considered that a shallow junction can be formed with good control if the P and As contained in the polycrystalline semiconductor layer are strictly defined. For this purpose, P+
If As+ is doped by ion implantation, the ion implantation is a method of physically doping impurities, so the location of impurities in the polycrystalline semiconductor layer can be controlled.Therefore, the inventors of the present invention A non-rubuted polycrystalline silicon layer with a thickness of approximately 0.2 μm is formed, and the door is
-As+ at a dose of 016 m-2 to 1011 to 101
After double ion implantation at a dose of 5i2, the junction depth of the N+fj1 impurity region when thermally diffused at 900° C. was investigated, and the depth and As+ dose for forming a shallow junction were investigated.

Figure 1 shows the diffusion length when P+ and As+ are double ion-implanted and thermally diffused. The relationship between the junction depth normalized by the diffusion length and the A8+ dose is shown using the dose as a parameter.

The method for manufacturing a semiconductor device of the present invention was made based on the results of evaluating FIG. 1, and includes forming an insulating film on the surface of a semiconductor substrate for electrically isolating the substrate, After forming a polycrystalline semiconductor layer so as to cover the separated regions of the semiconductor substrate, the polycrystalline semiconductor layer is doped with P+ to a depth of 10” cm−2 over 10 cm−2.
The ions of As (more than 1012 cm-2 and less than 1 Q'' cm-2) are implanted at a dose of less than 2, and P and 88 are thermally diffused using the polycrystalline semiconductor layer as a diffusion source. By doing so, it is possible to suppress the occurrence of defects due to the diffusion of impurities and to form a shallow junction with good control.

In the present invention, the dose of P+ is 1015cr++-2
exceeding 1016 crn-2 is 1015
Below crn-2, the impurity concentration of the emitter region is about IQ19cn+-3 compared to the generally used base region impurity concentration of 1018crn-3. The ratio of the impurity concentration in the base region and the impurity concentration in the base region decreases to about 10 or less, significantly deteriorating the performance of the transistor.
), 10" cm-2 or more, the diffusion length is almost the same as when only the door is ion-implanted, and a shallow junction cannot be formed. Also, the dose of Afi+ is f I Q 12 cm- I Q',' over 2
The reason for setting it below cm-2 is that if it deviates from this range, P+
This is because it is not possible to form a shallow junction with approximately the same diffusion length as in the case where only ions are implanted.

Moreover, if the dose amount of P+ and A8+ is within the above range,
No dislocations specific to P diffusion are observed.

[Embodiments of the Invention] Hereinafter, an embodiment in which the method of the present invention is applied to the formation of an emitter of a bipolar transistor will be described with reference to FIGS.

First, a secondary P-type silicon substrate 1 with a specific resistance of 10 to 20Ω
Partially in the N+ type buried region 2 of ρ8=20~25μ
After forming, the resistivity is 0.2 to 0.4 by vapor phase growth method.
0. Rust, 1.2 μm thick N-type epitaxial layer (collector region) 3 was grown azimuthally.

Next, a buffer oxide film pattern with a thickness of 500× and a silicon nitride film pattern with a thickness of 0.1 μm (not shown) are formed on the substrate 1, and using this silicon nitride film pattern as a mask, the N-type epitaxial layer (collector region )
3 was removed by 0.75M etching. Subsequently, after forming an isolation oxide film 4 with a thickness of 1.5 μm by selective oxidation, the silicon nitride film and the buffer oxide film are sequentially removed by etching fc (as shown in FIG. 2(a)).

Next, the N-type epitaxial layer (collector region) 3
After forming a thermal oxide film 5 with a thickness of 0.2 μm on the surface, B+ is accelerated with an energy of 80 keV and a dose of 1×10 cr using a photoresist pattern (not shown) as a mask.
Ion implantation was performed under the conditions of n.

Subsequently, after removing the photoresist pattern, N
A P-type base region 6 with ρ5=6004/hole and xj=0.4 μm was formed by heat treatment at 1000° C. for 60 minutes in a 2 atmosphere (as shown in FIG. 2(b)).

Next, openings 71 and 72 were formed by selectively etching away portions of the thermal oxide film 5 corresponding to the portions where the emitter region and the collector contact region were to be formed.

Subsequently, a non-doped polycrystalline silicon layer 8 with a thickness of 0.2 μm is deposited on the entire surface by the LPCvD method, and then P+ is accelerated at an energy of 3 Q keV and a dose of 5 XLO.
Under crn conditions, the A8+ is accelerated with an energy of 60k.
The ions were implanted under the conditions of eV and a dose of 5×10 13 cm −2 (as shown in FIG. 2(c)).

Next, by thermally diffusing the polycrystalline silicon layer 8 at 900° C. for 60 minutes in a 02 atmosphere using the polycrystalline silicon layer 8 as a diffusion source, ρ
, = 6010, xj = 0.14 μm, an N++ emitter region 9 and an N+ m collector contact region 10 were formed. Incidentally, the acceleration energy of only P+ is 3 Q ke
V % When ion implantation is performed at a dose of 5x10 crn and thermal diffusion is performed, ρ8 = 60Ω/mouth, Xj
=0.26AT1. Subsequently, after removing the oxide film formed on the surface of the polycrystalline silicon layer 8 during thermal diffusion, the polycrystalline silicon layer 8 is patterned to form a polycrystalline silicon layer 8 only on the N+ type cavity transmitter region and the N++ collector contact region 10. A crystalline silicon pattern of 111 pHzk remained (as shown in FIG. 2(d)).

Next, a portion of the thermal oxide film 5 on the P-type base region 6 was selectively etched away to form an opening 12. Next, after depositing an At-Si film with a thickness of 1.0 μm on the entire surface, it is patterned to form an emitter electrode 13 and a base electrode 1.
4 and a collector electrode 15 were formed to manufacture an NPN bipolar transistor (as shown in FIG. 2(, )). In the resulting NPN bipolar transistor, h,8=5.
0, VCEO= 12 V, ■o,. =20VXv9B
. -6V.

According to the method of the present invention, the amount of P and Al1 in the polycrystalline silicon layer 8 can be strictly defined by specifying the dose of ion implantation of Ag+. P and Ag using layer 8 as a diffusion source
e Simultaneous diffusion allows formation of a shallow emitter junction with precise control. For example, the dose of P+ is 5×1
0 crnlA-dose amount 2 X 1013cm-2
When ion implantation was carried out in this manner, a junction with a diffusion length of 140X could be obtained with good uniformity. Such extremely shallow junctions are difficult to form with good control using conventional methods.

By forming such a shallow junction, the emitter series resistance can be reduced, so that the resulting bipolar transistor can achieve high-speed operation.

Further, by simultaneously diffusing P and As, crystal defects accompanying diffusion can be suppressed, abnormal diffusion of As is less likely to occur, and emitter-collector shorting is less likely to occur.

Therefore, the probability of good quality transistors is 0.99999, which is significantly improved compared to 0.99994 when the emitter is formed by the conventional method, so it is important to increase the integration of bipolar transistors. I can do it.

Furthermore, it goes without saying that the presence of the polycrystalline silicon patterns 118.11□ is effective in preventing the wiring metal from coming into contact with shallow junctions and resulting in poor junctions.

Note that the method of the present invention is applicable not only to bipolar transistors (
It can be similarly applied to the manufacture of MOS) run listers. A case in which the method of the present invention is applied to the formation of the source and drain of a MOS (MOS) run lister will be explained with reference to FIG.

First, a thick field oxide film 22 is buried in a P-type silicon substrate 21 by selective oxidation. Next, after forming a thin thermal oxide film in the element formation region, a polycrystalline silicon film is deposited on the entire surface. Subsequently, the polycrystalline silicon film is buttered to form a gate electrode 23, and then the gate electrode 23 is formed.
3 as a mask, the thin thermal oxide film is removed by etching to form a gate oxide film 24. Next, thermal oxidation treatment is performed to form a thick thermal oxide film around the gate electrode 23 and a thin thermal oxide film on the surface of the substrate 21, and then only the thin thermal oxide film on the surface of the substrate 21 is removed by etching. The oxide film 25 is left. Subsequently, after a non-doped polycrystalline silicon layer is deposited on the entire surface, P+ and Aa+ are ion-implanted at a dose within the range of the method of the present invention.

Then, P and As are thermally diffused using the polycrystalline silicon layer as a diffusion source, and the N+ type source and drain regions 26.
form 27. Subsequently, the polycrystalline silicon layer is patterned to form N+ type source and drain regions 26 and 27.
After leaving the polycrystalline silicon pattern 28 only on the top,
An At-8i film is deposited on the entire surface and patterned to form a source electrode 29 and a drain electrode 30 (third
(Illustrated)

According to the method of the present invention, it is possible to form N+ type source and drain regions 26 and 27 with a shallow junction depth, so that the channel length is almost determined by the width of the gate electrode 23, and this enables high-speed, highly integrated MOS devices. can be obtained.

〔Effect of the invention〕

As detailed above, according to the present invention, it is possible to provide a method for manufacturing a semiconductor device that suppresses the occurrence of defects due to impurity diffusion, forms shallow junctions with good control, and achieves high speed and high integration. It is.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the depth of a junction by double ion implantation of P and 88, and FIGS. 2 (a) to (,) are cross-sectional views showing the manufacturing process of an NPN bipolar transistor in an embodiment of the present invention. , FIG. 3 is a cross-sectional view of a MOS (MOS) run lister manufactured in another embodiment of the present invention. 1...P- type silicon substrate, 2...N+ type buried region, 3...Hz epitaxial layer (collector region),
4... Isolation oxide film, 5... Thermal oxide film, 6... P type base region, 71172... Opening, 8... Polycrystalline silicon layer, 9... N+ type emitter region, 10...N
+ type collector contact region, 111.112...polycrystalline silicon pattern, 12...'fA hole, 13...
- Emitter electrode, 14... Base electrode, 15... Collector electrode, 21... P-type silicon base 11i, 22
... Field acid drain region, 29... Source electrode, 30... Drain electrode.

Claims (3)

[Claims] (1) Forming an insulating film on the surface of a semiconductor substrate to electrically isolate the substrate, and forming a polycrystalline semiconductor layer to cover at least the region of the semiconductor substrate separated by the insulating film. step, and adding 1 P+ to the polycrystalline semiconductor layer.
0 AB+ above 1012 crn-2 at a dose of more than 15 cm-2 and less than 1016 crn-2
ion implantation at a dose of less than 0 cm, and thermally diffusing P and As using the polycrystalline semiconductor layer as a diffusion source to form an impurity region of one conductivity type in the substrate. A method for manufacturing a featured semiconductor device. (2) The method of manufacturing a semiconductor device according to claim 1, wherein the impurity region of one conductivity type is an emitter region of a bipolar transistor. (3) The method of manufacturing a semiconductor device according to claim 1, wherein the impurity regions of one conductivity type are source and drain regions of a MOS (MOS) run lister.