JPH0465167A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a conductive wiring layer and a semiconductor substrate from being short-circuited if a contact between polycrystalline silicon layer and a conductive wiring layer is formed by providing a second conductivity type impurity diffused layer on a lower region of a contact hole. CONSTITUTION:An impurity diffused layer 18 is formed on a semiconductor substrate l under a contact hole 8. In the layer 18, an opposite conductivity type impurity to that to the substrate l is doped, and a p-n junction is formed in a boundary to the substrate 1. For example, when the substrate 1 is mounted and a positive bias voltage is applied to a conductive wiring layer 9, a reverse bias is applied to the p-n junction. Accordingly, even if the layer 9 is connected to the substrate 1 through a polycrystalline silicon layer 3 and an oxide film 2 at the bottom of the hole 8, an insulation between the layer 9 and the substrate l is obtained, no current leakage occurs through the substrate l. Thus, a desired bias voltage is effectively applied to the layer 3 as a field shielding electrode, and shielding characteristic is held excellently to provide satisfactory shielding characteristic.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a semiconductor device including a polycrystalline silicon layer having a conductive wiring layer and an electrical connection portion.

[Conventional technology] Conventionally, MOS (Metal Oxide Sem
A thick field oxide film is formed in a field portion, which separates transistors of a conductor type integrated circuit, for element isolation. As a method for forming this field oxide film, a so-called LOCoS method is used, which takes advantage of the strong oxidation resistance of silicon nitride film (S i3 N4 film) to selectively form a thermal oxide film on a part of the silicon substrate surface. (Local Oxid
The eof 5 ilicon) method is typically used. However, this LOCoS method has a problem in that it impedes improvement in the degree of integration of semiconductor devices due to the formation of a so-called bird's beak whose cross section is shaped like a bird's beak. Therefore, in recent years, LOC
A method using a so-called field shield has come to be used as an element isolation means in place of a field oxide film such as an oS. This field shield is designed to isolate elements by applying a bias voltage to a shield electrode made of a conductive layer such as polycrystalline silicon formed on a semiconductor substrate in a field portion with a thin oxide film interposed therebetween. According to this method, compared to a method using a field oxide film such as the LOGO3 method, it is possible to isolate elements in a field portion with a narrower area, and is therefore superior in achieving higher integration.

The structure of an element isolation region using a conventional field shield and its formation process are shown in FIG. 5A.

This will be explained with reference to FIG. 5B and FIGS. 6A to 6H.

A conventional device isolation structure using a field shield is as shown in FIGS. 5A and 5Bfffl, for example. Referring to these figures, this conventional element isolation structure using a field shield is constructed by interposing an oxide film 2 with a thickness of about 500 Å on the surface of a semiconductor substrate 1 made of, for example, single-crystal p-type silicon. A field shield electrode 3 made of polycrystalline silicon doped with impurities is
It is formed with a thickness of about 2,000 by CVD method or the like. This field shield electrode 3 has a diameter of about 2000
It is covered with an oxide film 4 having a thickness of A, and a gate electrode 6 is patterned on the surface of this oxide film 4. This gate electrode is formed on the surface of the semiconductor substrate 1 with a gate insulating film 5 having a thickness of several hundred layers interposed in the active region separated and insulated by the field shield electrode 3. The gate electrode 6 and other field shield electrodes are covered with an oxide film 7.

A contact hole 8 is provided at a predetermined location of this oxide film 7, and in this contact hole 8, a conductive wiring formed of aluminum or the like on the surface of the oxide film 7 and the field shield electrode 3 are electrically connected. There is. This conductive wiring layer 9 is provided for applying a bias electrode to the field shield electrode 3. On both sides of the gate electrode 6 in the active region, as shown in FIG. 5B, MO
Impurity diffusion layers 10a and 10b of a conductivity type opposite to that of the semiconductor substrate 1 are formed, forming source/drain regions of an 8-type field effect transistor.
a and 10b are contact holes lla and ll, respectively.
In b, conductive wiring layers 12a, 1 made of aluminum etc.
2b.

Next, the manufacturing process of a semiconductor device having such a structure and having elements separated by a conventional field shield will be described with reference to FIGS. 6A to 6H.

First, on the surface of a semiconductor substrate 1, a polycrystalline silicon layer 3 doped with impurities is deposited on the surface of a semiconductor substrate 1 with an oxide film 2 of about 200 A formed by thermal oxidation, etc.
Deposit 0OA. Thereafter, an oxide film with a thickness of about 2000 Å is deposited on this polycrystalline silicon layer 3, also by CVD method (FIG. 6A). Next, by photolithography and etching, the oxide film 4. Polycrystalline silicon layer 3 and oxide film 2 are sequentially and selectively etched to form a field shield portion (arrow B in FIG. 6B) and an active region surrounded by the field shield portion (arrow B in FIG. 6B). C
part) of the semiconductor substrate 1 is exposed. Thereafter, approximately 2,000 oxide films are deposited on the entire surface of the semiconductor substrate 1 by CVD method, etc., and anisotropic etching is performed.
Sidewall spacers 4a are formed around the field shield portion, resulting in the state shown in FIG. 6B. Next, a gate oxide film 5 with a thickness of about 200 A is formed on the surface of the semiconductor substrate 1 in the active region by thermal oxidation, and then impurities such as phosphorus and arsenic are doped over the entire surface of the semiconductor substrate 1 by CVD method or the like. deposit a polycrystalline silicon layer 6 (6th C)
figure). Note that in the thermal oxidation process for forming the gate oxide film 5, heat treatment is performed at a high temperature of approximately 600° C. or higher in an oxygen atmosphere. 13 is formed.

The size of this oxide 13 is about 20,000, which is almost the same as the grain boundary diameter of polycrystalline silicon.

The thickness of the polycrystalline silicon layer 3 is approximately 20 mm.
If the thickness is sufficiently larger than 00, it will not be formed even in the thermal oxidation process, but if the thickness of the polycrystalline silicon layer 3 is less than about 2000 Å, it will be formed. Although the mechanism of formation of this oxide 13 is not necessarily clear, it is thought that it is formed by oxidation progressing along the grain boundaries of the polycrystalline silicon layer 3 or by oxidation of the polycrystalline silicon grains themselves. It will be done.

Next, the gate electrode 6 is patterned by photolithography and etching, resulting in the state shown in FIG. 6D. after that,
An oxide film 7 is formed on the entire surface of the semiconductor substrate 1 (FIG. 6E).
. A resist 14 is patterned on the surface of this oxide film 7, and anisotropic etching is performed using this as a mask to form a contact hole 8. At the time of this anisotropic etching, in order to expose the polycrystalline silicon layer 3 at the bottom of the contact hole 8, it is only necessary to remove exactly all of the oxide film 7 in the space that will become the contact hole 8. , usually 20%, taking into account variations in the thickness of the oxide film 7 due to differences in the underlying level and variations in the characteristics of the etching equipment.
Perform some over-etching. Due to this overetching, the oxide film 13 formed below the contact hole 8 is removed, and the polycrystalline silicon layer 3 is removed.
An opening 16 having a bottom on the surface of the semiconductor substrate 1 is formed by penetrating the oxide film 2 (FIG. 6F). Next, after removing the resist 14, the opening 16 including the inner wall of the contact hole 8 is formed in the semiconductor substrate. A conductive layer 9 of aluminum etc. is formed on the entire surface of 1.
a is formed by CVD method or sputtering (
Figure 6G).

Thereafter, the conductive layer 9a is patterned by photolithography and etching, and the conductive wiring layers 9, 10a, 10b are patterned.
is formed (Fig. 6H).

[Problems to be Solved by the Invention] The conventional semiconductor device described above has the following problems because it is formed through the steps described above.

When forming the conductive wiring layers 9.10a and 10b, since the openings 16 are also filled with aluminum, the openings 16 cause current leakage between the conductive wiring layers 9 and the semiconductor substrate 1. It becomes a leak path. It goes like this-
Openings 16 that cause cross paths occur when the sum of the thicknesses of oxide film 2 and polycrystalline silicon layer 3 is about 20% or less of the thickness of oxide film 4. The reason is as follows.

That is, since there is a level difference in the base of the oxide film 7, its thickness varies depending on the location. Furthermore, the etching apparatus itself has some variation in characteristics such as etching speed. However, in the dry etching for making contact with the polycrystalline silicon layer 3, the thickest part of the oxide film 7 must be etched until the polycrystalline silicon layer 3 is exposed. Therefore, the oxide 13 will be over-etched at a thinner location, and the oxide 13 will also be etched at the time of the over-etching. If the oxide 13 is completely etched by this over-etching, the conductive wiring layer 9 will be electrically connected to the semiconductor substrate 1 after it is formed, resulting in a leak path. Considering the variation in the thickness of the normal oxide film 7, if the sum of the thicknesses of the oxide film 2 and the polycrystalline silicon layer 3 exceeds about 20% of the thickness of the oxide film 7, the thinnest oxide film 4 Even at certain locations, the oxide 13 is not completely etched away due to over-etching and remains on the surface of the semiconductor substrate 1.

Therefore, no leak path occurs.

However, if the sum of the thicknesses of oxide film 2 and polycrystalline silicon layer 3 is less than about 20% of the thickness of oxide film 7, there is a risk that all of oxide 13 will be etched away due to overetching, resulting in a leak path.

When a leak path occurs, current leaks through the semiconductor substrate 1, and a desired bias voltage is not correctly applied to the polycrystalline silicon layer 3 that becomes the field shield electrode, resulting in a phenomenon in which the field characteristics of the field shield portion deteriorate. . In the conventional process described above, as a means to prevent the formation of oxide 13 in polycrystalline silicon layer 3, after forming oxide film 2, a nitride film with strong oxidation resistance is formed on the surface by CVD. It is possible to form a However, increasing the number of CVD steps in this way reduces productivity and becomes a major obstacle to improving mass productivity.

In view of the above-mentioned conventional problems, the present invention provides a method for connecting a polycrystalline silicon layer formed on a first conductivity type semiconductor substrate with a thin oxide film interposed therebetween and a conductive wiring layer, such as in the above-mentioned field shield. An object of the present invention is to provide a semiconductor device that prevents a conductive wiring layer and a semiconductor substrate from becoming short-circuited when a contact is formed.

[Means for Solving the Problems] A semiconductor device of the present invention includes a semiconductor substrate having a first conductivity type region at least on the surface and the vicinity thereof, and an oxide film interposed on the surface of the semiconductor substrate. In addition, a polycrystalline silicon layer containing impurity ions, an interlayer insulating film formed on this polycrystalline silicon layer and having a contact hole at a predetermined position with the surface of this polycrystalline silicon layer as a bottom surface, It includes a conductive wiring layer formed on the surface of the insulating film and the inner wall surface of the contact hole. A feature of this semiconductor device is that an impurity diffusion layer of the second conductivity type is provided in a region of the semiconductor substrate surface below the contact hole.

[Function] According to the present invention, by providing the impurity diffusion layer of the second conductivity type in the region located below the contact hole on the surface of the semiconductor substrate, there is a pn between the impurity diffusion layer and the semiconductor substrate. A bond will be formed. Therefore, by selecting the voltage applied to the polycrystalline silicon layer through the conductive wiring layer so as to cause a reverse bias to this pn junction, even if the conductive wiring layer penetrates the polycrystalline silicon layer and the oxide film, Even if it becomes connected to
This pn junction maintains insulation and prevents current leakage.

[Example] An embodiment of the present invention will be described below with reference to FIGS. 1A and 1B.

This will be explained based on FIGS. 2A to 2H.

In this embodiment, the present invention is applied to a semiconductor device having an element isolation structure using a field shield similar to the conventional example described above. Referring to FIGS. 1A and 1B, the element isolation structure using the field shield of this embodiment is shown in FIG. 1A and FIG. 1B. A polycrystalline silicon layer 3 doped with impurities is formed with a thickness of about 2000 Å by CVD or the like.

This polycrystalline silicon layer 3 constitutes a field shield electrode, and its surface is covered with an oxide film 4 having a thickness of about 200 OA. A gate electrode 6 is formed on the surface of this oxide film 4 by patterning. This gate electrode is formed on the surface of the semiconductor substrate 1 with a gate insulating film 5 having a thickness of several tens of OA interposed in an active region separated and insulated by a polycrystalline silicon layer 3 serving as a field shield electrode. . The top of the gate electrode 6 and the rest of the polycrystalline silicon layer 3 are covered with an oxide film 7. A contact hole 8 is provided at a predetermined location of this oxide film 7, and in this contact hole 8, a conductive wiring layer 9 formed of aluminum or the like on the surface of the oxide film 7 and the polycrystalline silicon layer 3 are electrically connected. It is connected. This conductive wiring layer 9 is provided for applying a bias voltage to the polycrystalline silicon layer 3 as a field shield electrode. On both sides of the gate electrode 6 in the active region,
Referring to FIG. 1B, impurity diffusion layers 10a and 10b of a conductivity type opposite to that of semiconductor substrate 1 are formed, forming source/drain regions of a MOS field effect transistor;
These impurity diffusion layers 10a and 10b are electrically connected to conductive wiring layers 12a and 12b made of aluminum or the like through contact holes lla and llb, respectively.

The above structure is common to the conventional example shown in FIGS. 5A and 5B. The structure of the semiconductor device of this embodiment differs from the conventional example described above in that an impurity diffusion layer 18 is formed on the surface of the semiconductor substrate 1 below the contact hole 8. This impurity diffusion layer 18 contains an impurity of a conductivity type opposite to that of the semiconductor substrate 1 (if the semiconductor substrate 1 is a p-type silicon single crystal plate, an n-type impurity ion such as phosphorus or arsenic).
is doped, and p is doped at the boundary with the semiconductor substrate 1.
An n-junction is formed. For example, when the semiconductor substrate 1 is installed and a positive bias voltage is applied to the conductive wiring layer 9, a reverse bias is applied to this pn junction. Therefore, even if the conductive wiring layer 9 penetrates through the polycrystalline silicon layer 3 and the oxide film 2 at the bottom of the contact hole 8 and is bonded to the semiconductor substrate, the insulation between the conductive wiring layer 9 and the semiconductor substrate 1 is The semiconductor substrate 1
There is no possibility of current leakage through the capacitor. Therefore, the polycrystalline silicon layer 3 as a field shield electrode
A desired bias voltage can be reliably applied to the shield, and good shielding characteristics can be maintained.

Next, the manufacturing process of the semiconductor device of this embodiment having such a structure will be explained with reference to FIGS. 2A to 2H.

First, a semiconductor substrate 1 made of p-type silicon single crystal, etc.
A resist mask 17 is applied to the entire surface of the substrate, and photolithography and etching are applied to the resist mask 17 to pattern an opening 17a in a predetermined shape. Thereafter, n-type ions such as phosphorus or arsenic are irradiated at least near the opening 17a, and an n-type impurity diffusion layer 18 is formed at a predetermined position on the surface of the semiconductor substrate 1 using the resist mask 17 as a mask (second A figure).

Next, after removing the resist mask 17, the semiconductor substrate 1
On the entire upper surface, an impurity-doped polycrystalline silicon layer 3 having a thickness of about 2000 Å is deposited by CVD or the like, with an oxide film 2 having a thickness of about 200 Å formed by thermal oxidation or the like interposed therebetween. After that, on this polycrystalline silicon layer 3, CVD is also applied.
An oxide film 4 having a thickness of about 200 OA is deposited by a method (FIG. 2B). Next, after forming a resist mask (not shown) in a predetermined shape by photolithography and etching, an oxide film 4. The polycrystalline silicon layer 3 and the oxide film 2 are sequentially and selectively etched to form a field shield portion (arrow B in FIG. 2C) and an active region surrounded by this field shield portion (arrow B in FIG. 2C). The surface of the semiconductor substrate 1 indicated by the arrow C) is exposed. Thereafter, an oxide film of about 2000 Å is deposited on the entire surface of the semiconductor substrate 1 by CVD or the like, and anisotropic etching is performed to form sidewall spacers 4a around the field shield portion, resulting in the state shown in FIG. 2C. becomes. Next, on the surface of the semiconductor substrate 1 in the active region, a gate oxide film 5 with a thickness of about 200 layers is formed by thermal oxidation, and then, on the entire surface of the semiconductor substrate 1,
A polycrystalline silicon layer 6 doped with impurities such as phosphorus and arsenic is deposited by CVD or the like. In the thermal oxidation step for forming the gate oxide film 5, heat treatment is performed at a high temperature of approximately 600° C. or higher in an oxidizing atmosphere.
Oxide 13 is formed.

The size of this oxide 13 is about 20,000, which is almost the same as the grain boundary diameter of polycrystalline silicon.

The mechanism of formation of this oxide 13 is the same as in the conventional process described above. Therefore, if the thickness of the polycrystalline silicon layer 3 is sufficiently larger than about 2,000 layers, it will not be formed even in the step of forming the oxide film 5 by thermal oxidation, but the thickness of the polycrystalline silicon layer 3 Approximately 2
If it is less than 000A, it will be formed.

Next, the gate electrode 6 is patterned by photolithography and etching, resulting in the state shown in FIG. 2D. after that,
An oxide film 7 is formed on the entire surface of the semiconductor substrate 1 (FIG. 2E)
. A resist 14 having a predetermined shape is patterned on the surface of this oxide film 7, and anisotropic etching is performed using this as a mask to form a contact hole 8. During this anisotropic etching, in order to expose the surface of the polycrystalline silicon layer 3 at the bottom of the contact hole 8, the etching is performed so that the oxide film 7 in the space that will become the contact hole 8 is completely removed. However, usually, over-etching is performed by about 20%, taking into consideration variations in the thickness of the oxide film 7 due to the presence of the underlying step and variations in the characteristics of the etching equipment. The oxide film 13 formed below the contact hole 8 for this overetching is removed, and the oxide film 2 penetrates the polycrystalline silicon layer 3 and the oxide film 2.
An opening 16 is formed with the surface of the semiconductor substrate 1 as the bottom (FIG. 2F). Next, after removing the resist 14, a conductive layer 9a made of aluminum or the like is formed on the entire surface of the semiconductor substrate 1, including the inner wall of the contact hole 8, by CVD or sputtering (FIG. 2G). Thereafter, the conductive layer is patterned by photolithography and etching to form conductive wiring layers 9.10a and 10b (FIG. 2H).

The process for forming the semiconductor device of this embodiment described above differs from the conventional process described above in that an impurity diffusion layer 18 is first formed at a predetermined position on the surface of the semiconductor substrate 1. The size of the opening 17a of the resist mask 17 for forming the impurity diffusion layer 18 is usually the same as the pattern of the resist 14 used when etching the contact hole to be formed later. The impurity diffusion layer 18 is formed in an area slightly larger than the inner periphery of the contact hole 8 in order to function to ensure insulation even when the oxide 13 is formed just below the inner periphery of the contact hole 8. There is a need to. However, when forming the impurity diffusion layer 18 by ion implantation, as shown in FIG. 2A, the opening 17 of the resist mask 17 is
Impurity ions diffuse to a region slightly outside the inner periphery of a.

Therefore, there is no particular problem even if the size of the opening 17a matches that of the contact hole 8. However, resist 14
In consideration of pattern misalignment of the resist mask 17, the opening width of the opening 17a of the resist mask 17 is set to be approximately 0.1 μm wider than the opening width of the contact hole 8 (if this is done, the impurity diffusion layer can be more safely removed). 18 formation areas are secured.

Next, another example of a manufacturing process for a semiconductor device having the same effects as the above embodiment will be described with reference to FIGS. 3A to 3C. In this manufacturing process, after forming the structure shown in FIG. 6F of the conventional example, a region on the semiconductor substrate 1 including at least the contact hole 8 is irradiated with impurity ions of a conductivity type opposite to that of the semiconductor substrate 1 ( Figure 3A). For this ion irradiation, if the semiconductor substrate 1 is a p-type, n-type impurity ions such as phosphorus or arsenic are used. By this ion irradiation, impurity ions are implanted into the surface of the polycrystalline silicon layer 3 at the bottom of the contact hole 8 using the resist 14 as a mask, thereby forming an impurity diffusion layer 18a. Furthermore, using the polycrystalline silicon layer 3 as a mask, impurity ions are also implanted onto the surface of the semiconductor substrate at the bottom of the opening 16 to form an impurity diffusion layer 18b (third
Figure B). Next, a conductive wiring layer 9 made of aluminum or the like is formed by patterning on the oxide film 7, including the inside of the contact hole 8 (FIG. 3C).

According to this manufacturing process, as described above, in the vicinity of the bottom of the opening 16 caused by the formation of the oxide 13 in the polycrystalline silicon layer 3, a conductivity type opposite to that of the semiconductor substrate 1 is formed. Impurity diffusion layer 18b is formed in a self-aligned manner. Therefore, a pn junction is formed in this part, and if a reverse bias voltage is applied between the conductive wiring layer 9 and the semiconductor substrate 1, insulation is maintained at this pn junction, and the current leaks are prevented.

Next, the present invention will be applied to a DRAM (Dynamic Rand
An example in which the present invention is applied to the periphery of the memory cell portion of the OM Access Memory will be described based on FIG. In the DRAM memory cell shown in FIG. 4, in the periphery of the memory cell array, at the contact portion with the conductive wiring for electrically connecting the cell plate to the peripheral circuit,
The present invention is applied. Therefore, in Figure 4, DR
It shows the structure near the most peripheral memory cell part in the AM memory cell array. For an outline of the structure of this memory cell, first refer to FIG.
An MO8 type bipolar transistor consisting of a transfer gate electrode 23, a source region 24, and a drain region 25 is formed in an active region separated and insulated by the upper field shield electrode 22. A bit line 26 is formed on the source region 24, and a storage node 27 is formed on the drain region 25. Furthermore, a cell plate 30 made of a polycrystalline silicon layer doped with impurities is formed with the bit line 26 via an insulating layer 28 and with the storage node 27 via a capacitor dielectric film 29. An oxide insulating film 31 is interposed between the cell plate 30 and the semiconductor substrate 21 on the outside of the active region separated by the field shield electrode 22 . The surface of the cell plate 30 is covered with an insulating layer 32,
On the insulating layer 32, including the inside of the contact hole 33 provided at a predetermined position in the insulating layer 32, there is a conductive wiring layer 3 that electrically connects the cell plate 30 and the peripheral circuit.
4 is formed by patterning. This conductive wiring layer 3
An impurity diffusion layer 35 of a conductivity type opposite to that of the semiconductor substrate 21 is formed on the surface of the semiconductor substrate 21 below the contact between the semiconductor substrate 4 and the cell plate 30 . Before forming the still oxide film 31, this impurity diffusion layer 35 is made by impurity ions of a conductivity type opposite to that of the semiconductor substrate 21 using a resist mask with the same pattern as the resist mask used when forming the contact hole 33. Formed by injection. By forming the impurity diffusion layer 35 in this manner, a pn junction is formed between the semiconductor substrate 21 and the impurity diffusion layer 35.

Therefore, in a heat treatment process such as when planarizing the insulating layer 32, an oxide 13 as shown in FIG. Even if the conductive wiring layer 34 is removed and joined to the surface of the semiconductor substrate 21, current leakage can be prevented.

[Effects of the Invention] As described above, according to the present invention, a semiconductor layer is formed on the surface of the semiconductor substrate below the contact portion between the polycrystalline silicon layer formed on the surface of the semiconductor substrate via an oxide film and the conductive wiring layer. By forming an impurity diffusion layer of a conductivity type opposite to that of the substrate, a pn junction is formed between this and the semiconductor substrate. Due to this pn junction, even if a leakage path occurs due to the formation of oxide in the polycrystalline silicon layer, a reverse bias will be created between the conductive wiring layer and the semiconductor substrate with respect to the pn junction. By applying a voltage like this, insulation is maintained and current leakage through the semiconductor substrate is prevented. Therefore, for example, if the present invention is applied to a contact portion of a wiring for applying a bias voltage to a field shield electrode, a desired bias voltage can be reliably applied and good shielding characteristics can be obtained.

[Brief explanation of the drawing]

FIG. 1A is a cross-sectional view (cross-sectional view taken along the line AA in FIG. 1B) showing the structure of a semiconductor device according to an embodiment of the present invention, and FIG. 1B is a plan view thereof. Figure 2A, Figure 2B, Figure 2C, Figure 2D, Figure 2E,
Figure 2F, Figure 2G, and Figure 2H are the same as Figure 1A and Figure 1.
FIG. 3 is a cross-sectional view sequentially showing the manufacturing process of the semiconductor device according to the embodiment of the present invention shown in FIG. FIGS. 3A, 3B, and 3C are cross-sectional views sequentially showing each step of an example of another manufacturing method for forming the semiconductor device of the present invention. FIG. 4 is a sectional view showing a structure in which the present invention is applied to the periphery of a memory cell portion of a DRAM. FIG. 5A is a cross-sectional view (A-A cross-sectional view in FIG. 5B) showing the structure of a conventional semiconductor device, and FIG. 5B is a plan view thereof. Figure 6A, Figure 6B, Figure 6C, Figure 6D, Figure 6E,
Figure 6F, Figure 6G, Figure 6H are Figures 5A and 5.
FIG. 3 is a cross-sectional view sequentially showing conventional steps for manufacturing the conventional semiconductor device shown in FIG. In the figure, 1 and 21 are semiconductor substrates, 2 and 4°7 are oxide films, 3 and 30 are polycrystalline silicon layers, 8° and 33 are contact holes, 9.34 are conductive wiring layers, and 18.35 are impurity diffusion layers. , 31 is an oxide insulating film (oxide film), 32 is an insulating layer (
oxide film). In the drawings, parts with the same reference numerals indicate the same or equivalent elements. (2 others) Fig. 1A 21: 1,400 Makuzai δ1 Hayakichi S day-'') ko〉layer-direction tt#getsara (wound Ihi one-sided) Bo ρen 1 (melting 'Af) ]'' -Taftoo・-J and respect @c line 1 Diffusion of fragments 1

Claims (1)

[Scope of Claims] A semiconductor substrate having a first conductivity type region at least on the surface and its vicinity; and a polycrystalline silicon layer containing impurity ions formed on the surface of the semiconductor substrate with an oxide film interposed therebetween. an interlayer insulating layer formed on the polycrystalline silicon layer and having a contact hole at a predetermined position with the surface of the polycrystalline silicon layer as a bottom surface; What is claimed is: 1. A semiconductor device comprising: a conductive wiring layer formed therein, and an impurity diffusion layer of a second conductivity type provided in a region of the surface of the semiconductor substrate located below the contact hole.