JPH0536843A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the area, which is occupied by wirings, and to improve an integration degree in a semiconductor device having a multilayer interconnection structure. CONSTITUTION:A contact hole 8 to penetrate an aluminium wiring layer 6, which is required connection to BPSG films 7 and 5 on a silicon substrate 1 formed with an element, is formed and the hole 8 is filled with a tungsten film 10. The electrical connection of the wiring layer 6 with an arbitrary wiring layer via the metal film in the hole 8 on the sidewall of the contact hole becomes possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to the structure of a semiconductor device having multi-layer wiring.

[0002]

2. Description of the Related Art A semiconductor device is miniaturized in a transistor element to improve the degree of integration in order to achieve higher speed and more functions. For this reason, the wiring that electrically connects the transistor elements becomes extremely complicated. In order to solve this problem, the wiring layers are multi-layered to ensure the freedom of wiring.

For example, in a MOS transistor, as shown in FIG. 2, after forming a field oxide film 2 on a silicon substrate 1, an element composed of a source 3A, a drain 3B, a gate electrode 4 and the like is formed. A BPSG film 5A is formed thereon, a contact hole is formed, and a lower layer wiring 11 is formed.
Next, the BPSG film 7A is formed again, contact holes are formed, and the upper layer wiring 12 is formed. In this way, the contact holes are displaced.

[0004]

As described above, in the conventional semiconductor device, when the uppermost wiring and the terminal of the transistor formed on the silicon substrate are connected, first, the terminal of the transistor and the wiring layer of the lowermost layer are connected. A method of connecting and connecting to the wiring in the upper layer while sequentially shifting the positions of the contact holes has been used. In this method, since the positions of the contact holes have to be shifted, there is a problem that the space required for the wiring is widened and the integration degree of the semiconductor device cannot be improved.

An object of the present invention is to provide a semiconductor device having a reduced area required for wiring and improved integration.

[0006]

The semiconductor device of the present invention comprises:
A conductor layer formed on the semiconductor substrate surface or on the semiconductor substrate, wiring formed in an insulating film on the conductor layer, and penetrating this wiring to be formed in the insulating film and reach at least the conductor layer. It includes a contact hole and an electrode buried in the contact hole and connected to the conductor layer and the wiring.

[0007]

According to the present invention, any wiring layer including each terminal of the transistor can be connected within one contact hole. As a result, the area required for wiring can be reduced.

[0008]

Embodiments of the present invention will now be described with reference to the drawings. 1A and 1B are sectional views of a semiconductor chip for explaining an embodiment of the present invention. The manufacturing method will be described below.

First, as shown in FIG. 1A, a field oxide film 2 is formed on a silicon substrate 1, and then a gate electrode 4 made of polycrystalline silicon is formed via a gate oxide film. Then, impurities are introduced using the gate electrode 4 as a mask to form the source 3A and the drain 3B. Next, the BPSG film 5 is formed on the entire surface by the CVD method, and is reflowed to be flattened. Next, an aluminum film containing Si is formed on the entire surface and then patterned to form the aluminum wiring 6 in the lower layer. Next, the BPSG film 7 is formed again and flattened, and then a contact hole 8 which penetrates the aluminum wiring 6 and reaches the surface of the drain 3B is formed by a dry etching method or the like.

Next, as shown in FIG. 1B, after a titanium nitride film 9 is formed as a barrier metal on the entire surface including the contact hole 8, a tungsten film 10 is grown by a blanket CVD method to fill the contact hole 8. Contact holes having an aspect ratio of about 3 are sufficiently filled with this tungsten film. When there is no problem of wiring resistance, the tungsten film 10 and the titanium nitride film 9 are patterned to form an upper wiring. If you want to reduce the wiring resistance,
The tungsten film 10 and the titanium nitride film 9 are etched back and left only in the contact holes 8 to form electrodes, and aluminum wiring is formed thereon.

As described above, according to this embodiment, the drain 3
Form a contact hole on B through the aluminum wiring 6,
By embedding an electrode made of a titanium nitride film and a tungsten film in it, the upper wiring, the aluminum wiring 6 and the drain 3B can be connected by one contact hole. Since it is not necessary to form the wiring, the wiring formation area can be reduced.

In the above embodiment, the case where the contact hole connected to the impurity diffusion layer is formed has been described.
It may be a case where the multilayer wirings are connected to each other. In this case, a contact hole may be formed up to the surface of the wiring of the lowermost layer, or a contact hole penetrating the wiring of the lowermost layer may be formed, and metal may be embedded in the contact hole to electrically connect the wirings. Good.

Further, although the MOS transistor is described in the above embodiment, a bipolar transistor or a compound semiconductor transistor may be used. Further, although tungsten is used for filling the contact hole by the CVD method, aluminum or the like may be used.

[0014]

As described above, according to the present invention, since a plurality of wiring layers can be directly connected in the contact holes, the area required for wiring can be reduced as compared with the conventional semiconductor device. Therefore, the degree of integration of the semiconductor device can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor chip for explaining an embodiment of the present invention.

FIG. 2 is a sectional view of an example of a conventional semiconductor device.

[Explanation of symbols]

1 Silicon substrate 2 field oxide film 3A source 3B drain 4 gate electrode 5,5A BPSG film 6 Aluminum wiring 7,7A BPSG film 8 contact holes 9 Titanium nitride film 10 Tungsten film 11 Lower layer wiring

Claims (2)

[Claims] 1. A conductor layer formed on the surface of a semiconductor substrate or on a semiconductor substrate, wiring formed in an insulating film on the conductor layer, and at least formed in the insulating film penetrating the wiring. A semiconductor device comprising: a contact hole reaching the conductor layer; and an electrode embedded in the contact hole and connected to the conductor layer and the wiring. 2. The semiconductor device according to claim 1, wherein the conductor layer is an impurity diffusion layer or a lower wiring.