JPH03230548A - Semiconductor device - Google Patents

Abstract

PURPOSE:To open a contact hole self-alignedly by making an interlayer insulating film a double-layered structure wherein an upper interlayer film is structured such that only a step part of a lower interlayer film formed by an underlying wiring and an upper part of the underlying wiring are left. CONSTITUTION:Interlayer films 10, 11 are structured in a double-layered structure, wherein an upper interlayer film 13a is constituted as a mask at the time of etching a lower interlayer film by means of partial etching of the upper interlayer film 11 with a photoresist film 12 and by means of etching after removal of the photoresist film, so as to open a contact hole without using the photoresist film. Thus a mask for etching a contact hole opening is composed of an insulating film so as to accurately form a contact hole.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to an interlayer structure between wirings and a contact hole thereof.

[Conventional technology]

FIG. 2 (al to tel shows each manufacturing process related to the interlayer structure between interconnects and contact hole formation of a conventional semiconductor device).

In the Fa1 diagram, (1) is the 81 substrate, (2) is the insulating oxide film of the field effect transistor formed of silicon oxide, and (8) is the gate electrode of the field effect transistor, which is a multilayer film containing impurities. The first wiring (4) made of crystalline silicon or the like is an impurity diffusion layer forming the source/drain of the field effect transistor. In the case of this configuration, a case will be described in which a contact hole is formed between each first wiring (8) and a second wiring is formed.

Next, as shown in Figure fb1, a silicon oxide film is formed as an interlayer insulating film (5) over the first wiring (8) by the CVD method.

Next, as shown in figure (c), a photoresist film (6) is formed with desired resist openings (7), and the interlayer insulating film (6) is etched by anisotropic etching (as shown in figure 41). 6
) to obtain a contact hole (8). Next, as shown in the te+ diagram, the photoresist film (6) is removed and the second wiring (9) is made of polycrystalline silicon containing impurities.
) to form.

[Problem to be solved by the invention]

Conventional interlayer structures and contact hole openings were constructed as described above, so when contact holes are formed between lower interconnects, this is achieved using a photoresist film, so the contact hole diameter and interconnect spacing are extremely large. small σ
When this happens, there is a problem that the overlay accuracy becomes very strict and it becomes impossible to stably form contact holes.

The present invention was developed to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device in which contact holes can be formed in a self-aligned manner.

[Means and effects for solving the problem] A semiconductor device according to the present invention has an interlayer film formed in two layers, partial etching of the upper interlayer film by a photoresist film, and etching of the lower layer by etching (L) after removal of the photoresist film. The upper interlayer film is configured as a mask for pattern etching between the sublayers, and holes can be opened in a self-aligned manner without using a photoresist film.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
Figures ta+ to (gl) are cross-sectional views showing the manufacturing process of a semiconductor device according to an embodiment of the present invention.

(In figure a1, (1) is an 81 substrate, (2) is a silicon oxide insulating oxide film of F5 type field effect transistor, (8) is a gate electrode of a field effect transistor, and is an impurity The first wiring (width is L) is made of polycrystalline silicon, etc., and is made of polycrystalline silicon, etc. (4) is an impurity diffusion layer that forms the source and drain of the field effect transistor. A case will be described in which a contact hole is formed between the first wirings (8) and a second wiring is formed.

In Figure ib1, a silicon oxide film is formed as an interlayer insulating film 00) over the first wiring (8) by the C1VD method. Next, the interlayer insulating film (I) is placed on the interlayer insulating film C (10).
A silicon nitride film is formed as Qυ by the CVD method.

At this time, the interlayer insulating film Cσ(1/ii1 interlayer insulating film B(l
When performing anisotropic etching, which will be used later, υ should have a composition that makes the selectivity as large as possible. In addition, interlayer insulating film B
(The film thickness of each part of Ill (on the first wiring (8), on the contact hole) is assumed.

Next, in the tct diagram, a photoresist film (width L') (13) which is longer than the width of the first wiring (8) by an approximate thickness of the interlayer insulating film B (1υ) is formed on the interlayer insulating film BGll.

Next, as shown in Figure fd1, the interlayer insulating film BQυ is partially etched by anisotropic etching using a photoresist film until the film thickness of the contact hole portion becomes l', which is thinner than l, and the photoresist film ctz'i Remove.

Next, as shown in the tet diagram, an interlayer insulating film F8 (1υ remaining A (13a)) is placed on the first wiring (8), and an interlayer insulating film B (1υ remaining H (13b) is placed on the stepped portion of the interlayer insulating film A). The interlayer insulating film B (Ill) is completely removed by anisotropic etching over the entire surface so as to form the interlayer insulating film B (Ill) in the portion (13c) corresponding to the contact hole.

Next, as shown in figure ff1, the interlayer insulating film A (10) is etched by anisotropic etching, which has a high selectivity between the interlayer insulating film A (ego) and the interlayer film J (10). 8) Drill a hole. At this time, interlayer insulating film remaining A (13a), interlayer insulating film remaining B (13b
) becomes the etching mask.

Next, as shown in FIG. 1g1, a second wiring (9) is formed using polycrystalline silicon or the like containing impurities.

In the above embodiment, the upper wiring is the second wiring (9), but this may correspond to the electrode of a capacitor, that is, a storage node in a so-called stood capacitor structure. Furthermore, the remaining interlayer insulating films A (13a) and B (13b) may be removed before forming the second wiring.

〔Effect of the invention〕

As described above, according to the present invention, since the contact hole etching mask is formed of an insulating film in a self-aligned manner, contact holes can be formed with high precision.

[Brief explanation of drawings]

Figure 1 Fa1 ~ (gl is a sectional view showing the manufacturing process of a semiconductor device which is an embodiment of the present invention, Figure 2 (al ~ +81
1 is a newspaper diagram showing a conventional manufacturing process of a semiconductor device. In the figure, (1) is an 81 substrate, (2) is an insulating oxide film,
(8) is the first wiring, (4) is the impurity diffusion layer, (8) is the contact hole, (9) is the second wiring, αQ is the interlayer insulating film A1σD is the interlayer insulating film Btoil is the photoresist film, (
13a), (13b) are interlayer insulation traces A↓ and H,
(13c) shows a portion corresponding to a contact hole. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In the interlayer structure between interconnects in a semiconductor device, a two-layer film structure is formed, and the thickness of the upper interlayer film is such that the thickness corresponding to the upper part of the lower interconnect is thicker than the other parts. A semiconductor device characterized in that, regarding the structure of the upper interlayer film, the upper interlayer film is formed only at the stepped portion of the lower interlayer film formed by the lower wiring and the upper part of the lower wiring.