JPS6138860B2 - - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing an insulated gate field effect semiconductor device having a multilayer wiring structure, and particularly to a method for forming contacts between each wiring layer. Regarding improvements.

(Prior Art) An example of a multilayer wiring structure conventionally employed for gate wiring of a MOS type field effect semiconductor device is shown in FIGS. 1 and 3. Note that FIG. 3 is a plan view of the pattern, and FIG. 1 is a sectional view taken along line A-A.

In FIGS. 1 and 3, 11 is a gate electrode formed by patterning a first layer of polycrystalline silicon film. As shown in the figure, the gate electrode 11 is formed on a channel region between a source region and a drain region via a gate oxide film in an element region surrounded by a field oxide film. A polycrystalline silicon wiring layer 11 is also formed on the field oxide film by patterning the first layer of polycrystalline silicon film, similarly to the gate electrode 10. These first layer polycrystalline silicon patterns 10 and 11 are made of an interlayer insulating film 1 such as a CVD-SiO ₂ film.
Covered by 2. A second wiring layer 14 is formed on the interlayer insulating film 12 by patterning a second layer polycrystalline silicon film.
The second layer wiring 14 is connected to the first layer polycrystalline silicon patterns 10 and 11 through a contact hole 13 formed in the interlayer insulating film 12.

Furthermore, a multilayer wiring structure shown in FIG. 2 has also been conventionally employed as gate electrode wiring of a MOS type semiconductor device. In this example, a first interlayer insulating film 12' is formed on the first layer polycrystalline silicon patterns 10' and 11'.
A second layer of polycrystalline silicon pattern 14' is wired on this first interlayer insulating film 12'.
Further, a metal wiring layer 16 is formed thereon via a second interlayer insulating film 15', and contact holes are formed in each end of the metal wiring layer in the interlayer insulating films 12' and 15'. They are connected to the first-layer polycrystalline silicon patterns 10', 11' and the second-layer polycrystalline silicon pattern 14', respectively, through them. That is, in this example, via the metal wiring layer 16, which is the third layer wiring,
First polycrystalline silicon wiring pattern 10', 1
1' and a second layer polycrystalline silicon pattern 14' are connected.

As described above, connections between each wiring layer in a conventional multilayer wiring structure are made through contact holes formed in an interlayer insulating film. The opening of the contact hole is made of PEP (Photo Engraving
This is done by selective etching (Process).
At this time, first, a photoresist coated on the surface of the interlayer insulating film is exposed and developed through a mask having a predetermined contact hole pattern, thereby forming a resist pattern having openings at contact hole formation positions. Next, by using the resist pattern as an etching mask and selectively etching the underlying interlayer insulating film,
A contact hole is opened that reaches the underlying wiring.

After forming the contact hole in this way, an upper layer wiring material is deposited and patterned to form an upper layer wiring connected to the lower layer wiring through the contact hole.

(Problems to be Solved by the Invention) In the conventional manufacturing method, in order to reliably connect the upper layer wiring to the lower layer wiring, the contact hole must be opened at the correct position on the lower layer wiring. As is clear from the above explanation, the accuracy of contact hole opening depends on the accuracy of forming the resist pattern, which is an etching mask, and this is greatly influenced by the alignment accuracy of the mask used for exposing the photoresist. .

However, since misalignment generally occurs in the mask alignment, the conventional manufacturing method has the following problems.

The first problem is that the first layer polycrystalline silicon wiring patterns 10, 10', 11, 1
1' must be formed with sufficient dimensional margin. For this reason, as shown in FIG.
1 must be made considerably wider than the contact holes 13, 13', which impedes an increase in the degree of integration. Moreover, when the interlayer insulating film covering the first layer polycrystalline silicon pattern 11 in the example of FIG. When forming the holes, side etching must be taken into account in addition to the above-mentioned mask misalignment, so the polycrystalline silicon patterns 10 and 11 of the first layer must have additional dimensional margin.

The second problem is that for the following reasons, connections between each wiring layer through contact holes cannot be made directly on the gate, but must be made on the field oxide film as shown in Figure 3, which reduces the integration density. This further hinders the improvement of That is, in recent years, the gate width has become extremely narrow in devices that have been miniaturized, so that it is not possible to sufficiently provide the above-mentioned mask alignment margin necessary for forming contact holes. Furthermore, even if there is no misalignment in the mask alignment, over-etching is usually performed when forming contact holes, so the etching solution will penetrate along the grain boundaries of the polycrystalline silicon layer and the gate oxide film will be damaged. This is because it may be damaged and adversely affect the reliability and characteristics of the element.

In view of the above circumstances, the technical object of the present invention is to reduce the area necessary for forming contact holes and thereby improve the degree of integration of elements.

[Structure of the Invention] (Means for Solving the Problems) In the method of the present invention, a gate electrode pattern and other first-layer polycrystalline silicon wiring patterns are first formed on a polycrystalline silicon layer through a thin silicon oxide film. By forming a laminated film pattern in which silicon nitride films are laminated and re-patterning only the silicon nitride film pattern, the silicon nitride film is left only in the contact forming portion.

Next, using the silicon nitride film left in the contact formation area as an oxidation-resistant mask, the surface of the first layer polycrystalline silicon wiring layer such as the gate electrode and the surface of the semiconductor substrate are selectively oxidized to function as an interlayer insulating film. A silicon oxide film is formed.
Subsequently, by removing the remaining silicon nitride film and the thin buffer oxide film thereunder, an exposed portion is formed for forming a contact with the second layer wiring formed thereon.

Thereafter, as in the conventional method, a conductor layer for the second layer wiring was deposited and patterned, thereby connecting the first layer polycrystalline silicon wiring and the second layer wiring at the exposed portion. Obtain a multilayer wiring structure.

As the conductor layer for the second layer wiring in the present invention, a polycrystalline silicon layer may be used, or a metal film such as aluminum may be used.

(Function) In the manufacturing method of the present invention, when re-patterning the silicon nitride film pattern laminated on the first layer polycrystalline silicon wiring pattern,
It is only necessary to remove unnecessary portions of the silicon nitride film pattern that already covers the electrode wiring pattern in the same shape as the electrode wiring pattern. Therefore, the resist pattern formed by PEP at that time is sufficient as long as it can protect the silicon nitride film in the contact formation area from etching. That is, as long as this condition is satisfied, even if the resist pattern is formed to extend outside the wiring, the protected nitride film portion will inevitably remain accurately on the wiring pattern. Therefore, if the dimensions of this resist pattern are made sufficiently larger than the width of the wiring pattern, there will be no problem even if the photomask is misaligned during PEP exposure.

Furthermore, a thin silicon oxide film is interposed between the silicon nitride film left in the contact forming portion as described above and the polycrystalline silicon layer therebelow. Therefore, even when forming an interlayer insulating film by selective oxidation using the remaining silicon nitride film as an oxidation-resistant mask, in the present invention, this thin silicon oxide film acts as a buffer and relieves the stress generated during the thermal process. . Therefore, it is possible to prevent minute cracks (voids) from being generated along the grain boundaries of the polycrystalline silicon layer due to the thermal stress. If such voids occur in the gate electrode, problems will arise in the reliability of the device due to impurity injection, etc. Therefore, the buffer oxide film mentioned above contributes to improving the reliability of the device.

Furthermore, when removing the remaining silicon nitride film and the thin buffer oxide film thereunder and forming a contact portion with the second layer wiring formed thereon, the etching is carried out by itself without any mask. This can be done by alignment. That is, the etching rates of the silicon nitride film and the silicon oxide film are significantly different, and the buffer oxide film is significantly thinner than the interlayer insulating film formed by the selective oxidation.

(Embodiment) Next, an embodiment in which the present invention is applied to the manufacture of a MOS type semiconductor device will be described with reference to FIGS. 4a to 4f.

(1) First, as shown in FIG. 4a, one main surface of a silicon semiconductor substrate 21 of one conductivity type (for example, P type) is selectively oxidized to form a field oxide film 22 with a thickness of about 1μ. Thus, an element region for a MOS transistor surrounded by the field oxide film 22 is formed. Next, by thermally oxidizing the exposed surface of the substrate 21 in this element region, a silicon oxide film 23 having a thickness of about 500 to 1500 Å is formed as a gate oxide film. Subsequently, a buried contact is formed according to a conventional method, but illustration thereof is omitted here.

(2) Next, a polycrystalline silicon film 24, a thin silicon oxide film 25, and a silicon nitride film 26 are formed on the entire main surface of the substrate 21 by a normal method such as a vapor phase growth method.
are sequentially formed in this order to obtain the laminated film shown in FIG. 4b.

At this time, if the polycrystalline silicon film 24 and the silicon nitride film 26 are in direct contact, cracks called voids will occur along the grain boundaries in the polycrystalline silicon film due to stress caused by the difference in thermal expansion between the two. Or silicon crystal grains are easily destroyed. As a result, problems arise in the reliability of the device due to the intrusion of impurities and the like. However, by interposing the thin silicon oxide film 25 between both films as described above, the oxide film acts as a buffer and compensates for the difference in thermal expansion between the polycrystalline silicon film 24 and the silicon nitride film 26. problems can be avoided.

Note that the polycrystalline silicon film 24 is doped in advance with impurities that are the same or have the same conductivity type as impurities that will be used later to form the source and drain regions.

(3) Next, as shown in FIG. 4c, the above laminated film other than the portions necessary for the electrode and wiring layer is selectively etched away by photolithography, and the gate electrode and other first layer polycrystalline layers are etched away. The shape corresponds to the silicon wiring pattern.

As a result, polycrystalline silicon patterns 24 ₁ ,
The silicon oxide film pattern ₂₅₁ and the silicon nitride film pattern ₂₆₁ have the same shape. Also,
The polycrystalline silicon pattern 24 ₂ , the silicon oxide film pattern 25 ₂ and the silicon nitride film pattern 26 ₂ also remain in the same pattern.

(4) Next, the silicon nitride film patterns 26 ₁ and 26 ₂ in other parts are selectively removed, leaving only the parts that will be in contact with the second layer wiring in the future, and then HF or NH ₄ F is removed. By removing the exposed portions of the silicon oxide films 23, 25 ₁ , 25 ₂ with an etching solution such as etchant, the state shown in FIG. 4d is obtained. As a result, a gate oxide film ₂₃₁ is formed as shown in the figure, and openings for impurity diffusion are formed on both sides of the gate oxide film 231. A polycrystalline silicon pattern 24 ₁ for a gate electrode is formed on the gate oxide film 23 ₁ , and a thin silicon oxide film pattern 27 ₁ and a silicon nitride film pattern 28 ₁ are formed at the portions that will become contacts. Also, a thin silicon oxide film pattern ₂₇₂ and a remaining silicon nitride film pattern ₂₈₂ are formed on the contact portion of the polycrystalline silicon pattern ₂₄₂ for other wirings. Note that after selectively removing the silicon oxide films 23, 25 ₁ and 25 ₂ , the silicon nitride films 26 ₁ and 26 ₂ are removed.
Re-patterning may also be performed.

The silicon nitride film patterns 26 ₁ , 26 ₂
When re-patterning, as shown in FIG. 6a, resist patterns 32 ₁ and 32 ₂ are formed to cover the contact forming area, and this is used as a mask for selective etching. The re-patterned silicon nitride film patterns 28 ₁ and 28 ₂ are obtained as shown in FIG. In that case, as shown in the figure, the resist patterns 32 ₁ and 32 ₂ may be formed to be large enough to protrude outside each wiring pattern, that is, outside the silicon nitride film patterns 26 ₁ and 26 ₂ . Therefore, a resist pattern is formed.
Even if the mask alignment is misaligned during PEP, if sufficiently large resist patterns 32 ₁ and 32 ₂ are formed, the nitride film patterns 28 ₁ and 28 ₂ can be reliably left on the wiring pattern.

(5) Next, a source region and a drain region are formed by diffusing an impurity of a conductivity type opposite to that of the substrate (for example, N type) through the opening using a normal diffusion technique or an ion implantation technique. Then,
The remaining silicon nitride film pattern 28 ₁ ,
By thermally oxidizing the entire substrate using 28 ₂ as an oxidation-resistant mask, the exposed surface of the substrate and the exposed surfaces of the polycrystalline silicon films 24 ₁ and 24 ₂ are selectively oxidized to form a new silicon oxide film 29. The state shown in FIG. 4e is obtained.

At this time as well, the thin silicon oxide film pattern 2
Since 7 ₁ and 27 ₂ function as a buffer and relieve stress during oxidation, it is possible to prevent voids from forming in the polycrystalline silicon wiring layer.

(6) Next, the remaining silicon nitride film pattern 28
_1,28 Remove ₂ . At the positions where the silicon nitride film patterns 28 ₁ , 28 ₂ have been removed, thin silicon oxide film patterns 27 ₁ , 2 with corresponding shapes are formed.
7 ₂ remains, but these oxide film patterns 27
₁ and 27 ₂ are formed sufficiently thinner than the newly formed silicon oxide film 29. Therefore, thin silicon oxide film patterns 27 ₁ , 27
Contact portions 30 ₁ and 30 2 in which polycrystalline silicon patterns 24 ₁ and 24 ₂ are exposed can be formed by etching the silicon oxide film for a sufficient time to remove the polycrystalline silicon patterns 24 ₁ and 24 ₂ . Next, after depositing, for example, a polycrystalline silicon film over the entire surface as a conductor layer for the second layer wiring, this is formed into the first polycrystalline silicon patterns 24 ₁ , 24 ₂ at the contact portions 30 ₁ and 30 ₂ . If patterning is performed so as to connect with the second polycrystalline silicon film 31, wiring can be formed using the second polycrystalline silicon film 31, as shown in FIG. 4f. The conductor layer for the second layer wiring may be made of aluminum, silicide, etc. in addition to polycrystalline silicon. When a polycrystalline silicon film is used as described above, it can also be configured to be used as a resistor or an active element. Note that FIG. 5 shows a pattern plan view corresponding to FIG. 4f.

As is clear from the above description, the contact portions 30 ₁ , 30 ₂ connecting the first layer polycrystalline silicon wiring patterns 24 ₁ , 24 ₂ and the second layer polycrystalline silicon wiring pattern 31 are made of first layer polycrystalline silicon They are self-aligned to have substantially the same width as the wiring patterns 24 ₁ and 24 ₂ . Therefore, the area required for contact formation does not require a margin for dealing with misalignment of masks and the like. Furthermore, the first polycrystalline silicon film ₂₄₁ and the second polycrystalline silicon film 31 are formed not only on the field oxide film but also on the gate.
can be connected in a self-aligned manner. Therefore, compared to the conventional MOS type semiconductor devices shown in FIGS. 1 to 3, the degree of integration can be significantly increased, and the degree of freedom in pattern layout can also be increased.

By the way, when forming a contact on the gate, penetration of the etching solution becomes a problem as described above. However, in the above embodiment, when etching the silicon nitride film, the thin buffer oxide film therebelow acts as a stopper, and long over-etching is not necessary to remove the thin buffer oxide film. Therefore, damage to the gate oxide film due to penetration of the etching solution can be avoided, and deterioration of reliability and characteristics can be prevented.

[Effects of the Invention] As detailed above, according to the present invention, the area required to form a contact hole can be reduced,
Moreover, by making it possible to form a contact on the gate, remarkable effects such as improving the degree of integration of the device can be obtained.

[Brief explanation of the drawing]

1 and 2 are sectional views of conventional semiconductor devices, respectively, and FIG. 3 is a plan view corresponding to FIG. 1. FIG. 4 is a sectional view showing each step of an embodiment of the present invention. FIG. 5 is a plan view of a semiconductor device obtained by the present invention. FIG. 6 is an explanatory diagram showing the main steps in the embodiment of FIG. 4. 21...Semiconductor substrate, 23...Silicon oxide film, 24, 24 ₁ , 24 ₂ ...Polycrystalline silicon film, 25, 25 ₁ , 25 ₂ , 27 ₁ , 27 ₂ ...
Thin silicon oxide film, 26, 26 ₁ , 26 ₂ , 2
8 ₁ , 28 ₂ ... silicon nitride film, 23 ₁ ... gate oxide film, 29 ... silicon oxide film, 30 ₁ ,
30 ₂ ... Contact portion, 31 ... Second layer polycrystalline silicon wiring pattern, 32 ₁ , 32 ₂ ... Resist pattern.

Claims (1)

[Claims] 1. A step of selectively forming a field insulating film on the surface of a semiconductor substrate of one conductivity type, and then forming a gate insulating film on the surface of the element region surrounded by the field insulating film; After depositing the crystalline silicon layer,
By stacking a silicon nitride film on the surface of the polycrystalline silicon layer via a thin silicon oxide film and by patterning the silicon nitride film, a gate electrode and other first By forming a silicon nitride film pattern corresponding to the layered polycrystalline silicon wiring pattern and etching the thin silicon oxide film and the polycrystalline silicon layer using the silicon nitride film pattern as a mask, the gate electrode pattern and other A step of forming a first layer polycrystalline silicon wiring pattern, and contacting the gate electrode pattern and other first layer polycrystalline silicon wiring patterns using a resist pattern having a dimension larger than the width of the first layer polycrystalline silicon wiring pattern. After covering the formation area, selectively etching and removing the silicon nitride film pattern using the resist pattern as a mask, leaving the silicon nitride film pattern only in the contact formation area, and masking the gate electrode pattern. A step of forming a source region and a drain region separated from each other by introducing an impurity having a conductivity type opposite to that of the semiconductor substrate into the element region, and making the remaining silicon nitride film pattern resistant to oxidation. oxidizing the surface of the first layer polycrystalline silicon wiring pattern including the gate electrode pattern and the surface of the semiconductor substrate using a oxidizing mask to form an oxide film; A step of exposing the contact formation portion of the first layer polycrystalline silicon wiring pattern including the gate electrode pattern by removing the thin oxide film, and depositing and patterning a conductor layer for the second layer wiring. A method of manufacturing a semiconductor device, comprising: forming a second layer wiring pattern connected to the first layer polycrystalline silicon wiring layer at the contact forming portion. 2. Prior to depositing the polycrystalline silicon layer, exposing at least a portion of the surface of the device region in the vicinity of the field insulating film, and
The semiconductor according to claim 1, wherein the first layer polycrystalline silicon wiring pattern is formed in contact with the surface of the element region at the exposed portion, and is used as a source electrode or a drain electrode. Method of manufacturing the device.