JP2915015B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor integrated circuit having a multilayer wiring structure and a method of manufacturing the same. It is an object of the present invention to provide a method of manufacturing a semiconductor device which performs high-precision alignment and realizes a high-density multilayer wiring structure, comprising: a first wiring layer formed on a semiconductor substrate;
A first side-fall layer formed on a side wall of the first wiring layer, a first stopper layer formed on the first wiring layer, and a first interlayer formed on the first stopper layer An insulating layer, a first contact hole formed in the first interlayer insulating layer, and exposing one end of the first stopper layer and the semiconductor substrate; and a first contact hole in the first contact hole and the first contact hole. A second wiring layer extending on the interlayer insulating layer, a second sidewall layer formed on a side wall of the second wiring layer, and a second wiring layer on the first interlayer insulating layer; A second interlayer insulating layer formed on the first interlayer insulating layer and the second interlayer insulating layer,
A second contact hole exposing the other end of the first stopper layer and the semiconductor substrate; and a third wiring layer extending in the second contact hole and on the second interlayer insulating layer. Constitutes a semiconductor device.

In the method for manufacturing a semiconductor device having a multilayer wiring structure, a step of forming a first wiring layer having a first stopper layer on an upper surface and a step of depositing a first interlayer insulating layer over the entire surface and then opening at least an opening thereof A part of the first wiring layer includes a mask pattern including an upper part of one end of the first wiring layer;
Forming a first contact hole in the first interlayer insulating layer using the stopper layer as an etching stopper; forming a second wiring layer in a region including the first contact hole; After depositing the second interlayer insulating layer, using a mask pattern including at least a part of the opening above the other end of the first wiring layer, using the first stopper layer as an etching stopper, Forming a second contact hole in the first interlayer insulating layer and the second interlayer insulating layer; and forming a third wiring layer in a region including the second contact hole. Constitute.

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor integrated circuit having a multilayer wiring structure and a method for manufacturing the same.

[Related Art] In recent years, in a semiconductor integrated circuit that is steadily miniaturized, a multilayer structure of a wiring layer has been performed in addition to a high density in a lateral direction. When the wiring layers are multi-layered, finer patterns and highly accurate alignment of contact holes for wiring are required.

Conventionally, such a technique of miniaturizing a pattern of a wiring layer and a highly accurate alignment of a contact hole has been performed by, for example, a stepper exposure apparatus having an extremely low configuration using reduced projection.

[Problems to be Solved by the Invention] However, in such a conventional method for forming a multilayer wiring layer, an extremely high-precision apparatus is used in order to position and open a contact hole in the wiring layer with high precision. Due to the necessity, there is a problem that workability is reduced and the cost is increased.

Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device which realizes a high-density multilayer wiring structure by performing a highly accurate alignment of a contact hole of a wiring layer by a relatively easy pattern forming process. .

[Means for Solving the Problems] The above object is achieved by a first wiring layer formed on a semiconductor substrate, a first sidewall layer formed on a side wall of the first wiring layer, A first stopper layer formed on the first wiring layer, a first interlayer insulating layer formed on the first stopper layer, and a first stopper layer formed on the first interlayer insulating layer. A first contact hole exposing one end of a layer and the semiconductor substrate, a second wiring layer extending in the first contact hole and on the first interlayer insulating layer, and the second wiring A second sidewall layer formed on a side wall of the layer, a second interlayer insulating layer formed on the first interlayer insulating layer and the second wiring layer, and a first interlayer insulating layer And the other end of the first stopper layer formed on the second interlayer insulating layer And a second contact hole exposing the semiconductor substrate, and a third wiring layer extending in the second contact hole and on the second interlayer insulating layer. Achieved.

In the above semiconductor device, the semiconductor device may further include a second stopper layer on the second wiring layer, wherein the second contact hole includes the other end of the first stopper layer,
The second stopper layer and the semiconductor substrate may be exposed.

Further, in the method for manufacturing a semiconductor device having a multi-layer wiring structure, there is provided a method of forming a first wiring layer having a first stopper layer on an upper surface and a method of forming a first interlayer insulating layer on the entire surface. A first contact with the first interlayer insulating layer using a mask pattern including at least a part of the opening above one end of the first wiring layer and using the first stopper layer as an etching stopper; Forming a hole, forming a second wiring layer in a region including the first contact hole, and depositing a second interlayer insulating layer on the entire surface. A second contour is formed on the first interlayer insulating layer and the second interlayer insulating layer by using a mask pattern including an upper portion of the other end of the first wiring layer and using the first stopper layer as an etching stopper. Also achieved by a method of manufacturing a semiconductor device characterized by a region including a step of forming a Tohoru the second contact hole and forming a third wiring layer.

In the method of manufacturing a semiconductor device, a sidewall layer may be provided on a side wall of the first wiring layer at the same time as the formation of the first contact hole and the second contact hole.

Further, in the method for manufacturing a semiconductor device having a multi-layer wiring structure, there is provided a method of forming a first wiring layer having a first stopper layer on an upper surface and a method of forming a first interlayer insulating layer on the entire surface. Forming a first contact hole in the first interlayer insulating layer, and forming a second wiring layer including the first contact hole and extending on the first wiring layer; Forming a second wiring layer having a second stopper layer on the upper surface, and depositing a second interlayer insulating layer on the entire surface, and at least a part of the opening is formed at one end of the second wiring layer. The first interlayer insulating layer and the second interlayer insulating layer using a first stopper layer and a second stopper layer as an etching stopper using a mask pattern including a portion and an upper portion of one end of the first wiring layer. Second interlayer insulating layer Forming a contact hole, also achieved by the manufacturing method of the semiconductor layer, which comprises a step of forming a third wiring layer in a region including the second contact hole.

In the method for manufacturing a semiconductor layer, the second
Simultaneously with the formation of the contact hole, a sidewall layer may be provided on the side wall of the first wiring layer and the second wiring layer.

In the method of manufacturing a semiconductor device, the first wiring layer may form a word line, the second wiring layer may form a bit line, and the third wiring layer may form one electrode of a capacitor. You may.

[Operation] According to the present invention, by forming a stopper layer on a first wiring layer, when opening a contact hole in a second wiring layer, a hole is formed in a self-aligned manner using the stopper layer as a mask. Can do it. This allows
Even if a somewhat rough contact mask pattern is used, the positioning of the contact hole in the second wiring layer can be performed with high accuracy, and the stopper layer on the upper and side surfaces of the first wiring layer and The first wiring layer and the second wiring layer can be completely separated by the sidewall layers.

[Examples] Hereinafter, the present invention will be specifically described based on the illustrated examples.

FIG. 1 is a process chart showing a method of manufacturing a memory cell according to one embodiment of the present invention, and FIGS.
It is the top view and perspective view of the memory cell manufactured by the process shown in the figure.

For example, on a semiconductor substrate 2 composed of a silicon substrate, SiO ₂
After the layer 4 and the Si ₃ N ₄ layer 6 are sequentially formed, the Si ₃ N in the field region is formed using a patterned resist (not shown).
_Fourth layer 6 is selectively removed. Then, using the resist on the element region and the Si ₃ N ₄ layer 6 as a mask, B ⁺ (boron ion) ions are selectively implanted into the field region to form a B ⁺ ion implanted region 8 (FIG. 1A )reference).

Next, LOCOS (Local Oxid) using the Si ₃ N ₄ layer 6 as a mask
A field oxide film 10 having a large thickness is formed in the field region by an ation of silicon) method to separate an element region. At this time, the B ⁺ ion-implanted region 8 is annealed to become a p-type channel cut layer 8a below the field oxide film 10.

Then, after removing the Si ₃ N ₄ layer 6 and the SiO ₂ layer 4, a gate oxide film 12 is formed on the semiconductor substrate 2 in the element region. Subsequently, the polysilicon layer 14, the SiO ₂ layer 16 and the AlN _X stopper layer
18 are formed in order. Then, a resist 20 is applied on the AlN _X stopper layer 18 and patterned into a predetermined shape (see FIG. 1B).

Next, using the patterned resist 20 as a mask, the AlN _X stopper layer 18, the SiO ₂ layer 16 and the polysilicon layer 14 are selectively etched in this order. Thus, a plurality of word lines 14a made of the polysilicon layer are formed. During this etching, the polysilicon layer 14 and the SiO ₂ layer 16
And using an etchant having an etching rate different from that of the AlN _X stopper layer 18 as shown in FIG.
It is desirable to side etch a.

Subsequently, after removing the resist 20, the AlN _X stopper layer
Using the SiO ₂ layer 16 and the word line 14a as masks, As ⁺ (arsenic ion) ions are selectively implanted to form an As ⁺ ion implanted region 22 (see FIG. 1C).

Next, the As ⁺ ion implantation region 22 is made into an n-type bit contact region 22a and an n-type capacitor impurity region 22b by annealing, and an interlayer insulating layer 24 made of SiO ₂ is deposited on the entire surface. Then, a resist is formed on the interlayer insulating layer 24.
26 is applied and patterned into a predetermined shape, and RIE (Reactiv
The interlayer insulating layer 24 is selectively etched by the (e Ion Etching) method, and a bit contact hole 28 is opened on the n-type bit contact region 22a.

At this time, the AlN _X stopper layer 1 is placed on the word line 14a.
Even if the patterning of the resist 26 is very rough because the resist pattern 26 is formed, the bit contact hole 28 to be opened is positioned with high accuracy by being etched into the cell alignment using the AlN _X stopper layer 18 as a mask. Is done. In addition, a sidewall layer 24a made of SiO ₂ remains on the side wall of the word line 14a adjacent to the n-type bit contact region 22a (see FIG. 1D).

Next, after sequentially forming a polysilicon layer, a SiO ₂ film, and an AlN _X stopper layer, patterning into a predetermined shape,
A bit line 30 made of polysilicon connected to the n-type bit contact region 22a through the bit contact hole 28, and an SiO ₂ layer 32 and AlN _x on the bit line 30
The stopper layer 34 is formed. At this time, word line 14
AlN _X stopper layer 18 on a and side wall layer 2 on side
4a, the bit line in the bit contact hole 28
30 and the adjacent word line 14a are completely separated. In this step, when forming the bit line 30, using an etchant having a different etching rate between the polysilicon layer, the SiO ₂ film, and the AlN _X stopper layer,
It is desirable to side-etch the bit line 30 made of polysilicon (see FIG. 1 (e)).

Next, an interlayer insulating layer 36 made of SiO ₂ is deposited on the entire surface. Then, a resist 38 is applied on the interlayer insulating layer 36 and patterned into a predetermined shape, and then a capacitor contact hole 40 is opened on the n-type capacitor impurity region 22b by RIE using the patterned resist 38 as a mask.

At this time, similarly to the step of opening the Z-contact hole 28, the AlN _X stopper layer 1 is formed on the word line 14a.
8 is formed, and the AlN _X stopper layer 34 is formed on the bit line 30, so that the AlN _X stopper layer 34 and the AlN
By being etched Seruarain the N _X stopper layer 18 as a mask, the capacitor contact hole 40
Are aligned with high precision. On the side walls of the bit line 30 and the side of the word line 14a adjacent to the n-type capacitor impurity region 22b, the side wall layers 36a and 24b made of SiO ₂ remain (see FIG. 1 (f)).

Next, a capacitor layer 42 made of polysilicon is formed in the capacitor contact hole 40 on the n-type capacitor impurity region 22b. This capacitor layer 42 has a fin structure with a large surface area to increase the capacitance of the capacitor. And the AlN _X stopper layer on the bit line 30
The capacitor layer 42 in the capacitor contact hole 40 and the adjacent bit line 30 and word line are formed by the AlN _X stopper layer 18 and the side wall layer 24a on the word line 14a. 14a is completely separated.

Subsequently, a SiO ₂ layer / S
After forming the i ₃ N ₄ layer 44, a cell plate layer 46 made of polysilicon is formed on the SiO ₂ layer / Si ₃ N ₄ layer 44 and the interlayer insulating layer 36.
Is formed (see FIG. 1 (g)).

Next, a plan view and a perspective view of the memory cell thus manufactured are shown in FIGS. 2 and 3, respectively.

The word line 14 formed in the step shown in FIG.
The bit lines 30 formed in the step a and the step shown in FIG. 1 (e) are wired in a mesh. AlN _X is placed on the word line 14a and the bit line 30, respectively.
Since the stopper layers 18 and 34 are formed, in the step shown in FIG.
When patterning the resist mask for opening the holes, a very rough bit contact mask pattern as shown by a broken line in part A of FIG. 2 can be used. Similarly, in the step shown in FIG. 1 (f), when patterning a resist mask for opening the capacitor contact hole 40, a very rough capacitor contact mask pattern as shown by a broken line Can be used.

That is, even if such a bit contact mask pattern of the part A and a capacitor contact mask pattern of the part B are formed very roughly, they are formed on the word lines 14a and the bit lines 30, respectively, in the subsequent etching process. The AlN _X stopper layers 18 and 34 function as a mask, and a bit contact portion 48 and a capacitor contact portion 50 are formed in a self-aligned manner.

In this way, the bit contact hole can be formed by performing photolithography and etching at the level of the conventional processing accuracy without using a high-precision device.
28 and the capacitor contact hole 40 can be formed with high precision alignment. Therefore, as shown in FIG. 3, it is possible to realize a high-density multilayered wiring structure of the word lines 14a, the bit lines 30, and the capacitor layers 42.

As described above, according to the present embodiment, the AlN _X stopper layers 18, 34 are formed on the word lines 14a and the bit lines 30, respectively.
Forming these AlN _X stopper layers 18, 3
Using 4 as a mask, bit contact hole 28 and capacitor contact hole 40 can be formed in a self-aligned manner. Therefore, the bit contact hole 28 and the capacitor contact hole 40 in the multilayer wiring structure of the word line 14a, the bit line 30, and the capacitor layer 42 can be accurately positioned.

When the bit contact hole 28 and the capacitor contact hole 40 are opened, the SiO ₂ side wall layers 24a, 24b,
By forming 30a, bit contact hole 28
In addition, the mutual insulation between the word line 14a, the hit line 30, and the capacitor layer 42 in the capacitor contact hole 40 can be completed.

The inventor was able to manufacture a high-density D-RAM having a cell area of 2 μm ² / bit by using such a relatively easy pattern forming process according to this embodiment.

In the above embodiment uses the AlN _X as a stopper layer formed on the word line 14a and the bit line 30 may be AlO _X. Although it is conceivable to use SiN _X , according to the experiments of the present inventors, AlN
In the case of the N _X film or the AlO _X film, the selectivity to the SiO ₂ film is 100 to 200, whereas in the case of the SiN _X film, it is 10 to 20. For this reason, it does not have sufficient masking properties when etching the interlayer insulating layer made of SiO ₂ . Therefore, AlN _X
Alternatively, the yield can be improved by using AlO _X.

[Effects of the Invention] As described above, according to the present invention, in a method of manufacturing a semiconductor device having a multilayer wiring structure, a stopper layer is formed on a first wiring layer, and a contact hole of a second wiring layer is opened. In this case, holes are formed in self-alignment using the stopper layer as a mask,
The alignment of the contact hole in the second wiring layer can be performed with high accuracy, and the insulation between the first wiring layer and the second wiring layer in the contact hole can be made perfect.

Thus, the alignment of the contact holes in the wiring layer can be performed with high accuracy by a relatively easy pattern formation process, and a high density can be realized.

[Brief description of the drawings]

FIG. 1 is a process chart showing a method of manufacturing a memory cell according to one embodiment of the present invention, FIG. 2 is a plan view of a memory cell manufactured by the process shown in FIG. 1, and FIG. FIG. 2 is a perspective view of a memory cell manufactured by the process shown in FIG. In FIG, 2 ...... semiconductor substrate, 4,16,32 ...... SiO ₂ layer, 6 ...... Si ₃ N ₄ layer, 8 ...... B ⁺ ion implantation region, 8a ...... p-type channel cut layer, 10 ...... Field oxide film, 12 ... Gate oxide film, 14 ... Polysilicon layer, 14a ... Word line, 18,34 ... AlN _X stopper layer, 20,26,38 ... Resist 22 ... As ⁺ ion implantation area 22a ... n-type bit contact region, 22b ... n-type capacitor impurity region, 24, 36 ... interlayer insulating layer, 24a, 24b, 36a ... sidewall layer, 28 ... bit contact hole, 30 ... bit Line, 40: Capacitor contact hole, 42: Capacitor layer, 44: SiO ₂ layer / Si ₃ N ₄ layer, 46: Cell plate layer, 48: Bit contact part, 50: Capacitor contact part.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/28-21/288 H01L 21/3205-21/3213 H01L 21/768

Claims (7)

(57) [Claims] A first wiring layer formed on the semiconductor substrate; a first sidewall layer formed on a side wall of the first wiring layer; and a first wiring layer formed on the first wiring layer. A first stopper layer; a first interlayer insulating layer formed on the first stopper layer; an end portion of the first stopper layer formed on the first interlayer insulating layer; and the semiconductor substrate. A first contact hole exposing a second wiring layer extending in the first contact hole and on the first interlayer insulating layer; and a second wiring layer formed on a side wall of the second wiring layer. 2 sidewall layers; a second interlayer insulating layer formed on the first interlayer insulating layer and the second wiring layer; a first interlayer insulating layer and a second interlayer insulating layer And the other end of the first stopper layer and the semiconductor substrate are exposed. The semiconductor device of the second contact hole, characterized in that it has a third wiring layer extending in said second contact hole and the second interlayer insulating layer. 2. The semiconductor device according to claim 1, further comprising a second stopper layer on the second wiring layer, wherein the second contact hole is provided at the other end of the second stopper layer. A semiconductor device, wherein the first substrate, the second stopper layer, and the semiconductor substrate are exposed. 3. A method of manufacturing a semiconductor device having a multilayer wiring structure, comprising: forming a first wiring layer having a first stopper layer on an upper surface; and depositing a first interlayer insulating layer on the entire surface. Using a mask pattern including at least a part of the opening above one end of the first wiring layer, using the first stopper layer as an etching stopper, forming a first layer on the first interlayer insulating layer.
Forming a second wiring layer in a region including the first contact hole; and depositing a second interlayer insulating layer over the entire surface, and then forming at least a part of the opening. Using a mask pattern including an upper portion of the other end of the first wiring layer, using the first stopper layer as an etching stopper, forming a second layer on the first interlayer insulating layer and the second interlayer insulating layer. A method for manufacturing a semiconductor device, comprising: forming a contact hole; and forming a third wiring layer in a region including the second contact hole. 4. The method for manufacturing a semiconductor device according to claim 3, wherein a sidewall layer is provided on a side wall of the first wiring layer simultaneously with the formation of the first contact hole and the second contact hole. A method for manufacturing a semiconductor device. 5. A method for manufacturing a semiconductor device having a multilayer wiring structure, comprising: forming a first wiring layer having a first stopper layer on an upper surface; and depositing a first interlayer insulating layer on the entire surface. Forming a first contact hole in the first interlayer insulating layer; forming a second wiring layer including the first contact hole and extending on the first wiring layer; Forming a second wiring layer having a second stopper layer on the upper surface; and depositing a second interlayer insulating layer on the entire surface, and at least a part of the opening is formed at one end of the second wiring layer. And the first
Using a mask pattern including the upper part of one end of the wiring layer,
Forming a second contact hole in the first interlayer insulating layer and the second interlayer insulating layer using the first stopper layer and the second stopper layer as an etching stopper; Forming a third wiring layer in a region including the contact hole. 6. The method for manufacturing a semiconductor layer according to claim 5, wherein a sidewall layer is provided on side walls of said first wiring layer and said second wiring layer simultaneously with said formation of said second contact hole. Manufacturing method of a semiconductor device. 7. The method of manufacturing a semiconductor device according to claim 3, wherein said first wiring layer is a word line, said second wiring layer is a bit line, and said third wiring layer is a bit line. Wherein each of the wiring layers constitutes one electrode of a capacitor.