JPH05190809A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to achieve high integration density by suppressing the effects of the machining-size errors and the position deviation of a photo- mask. CONSTITUTION:A nitride film 220 is formed on an SiO2 film 210. The nitride film 220 is removed by anisotropic plasma etching so that the sidewall part of the SiO2 film 210 remains. The nitride film, which remains at the sidewall part of the SiO2 film 210, becomes a spacer 22Oa. Then, an SiO2 film 230 is formed. At this time, the spacer 220 acts as a mask for forming the SiO2. The SiO2 film 230 is formed at a part, where the spacer 22Oa is not present. The thick part of SiO2 is used as an etching mask, and the etching is performed down to a polysilicon film 110. Thus a stack gate is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a NAND type memory cell (semiconductor memory and I including the same).
C) manufacturing method.

[0002]

2. Description of the Related Art A NAND memory cell is known as a structure for increasing the integration degree of EPROM. The NAND type memory cell is equivalent to a circuit in which memory cells are equivalently cascade-connected by patterning a stack gate in which two layers of gates (floating gates and control gates) are arranged at predetermined intervals. Higher integration N
The manufacturing method of the AND type memory cell is "IEDM 90-1.
03 ". "IEDM 90-103"
The manufacturing method described will be briefly described as follows.

Two layers of polysilicon, which serve as a floating gate and a control gate, are provided on a semiconductor substrate. Next, nitride films are provided at regular intervals, and a resist is patterned between the nitride films (see FIG. 3A). Etching is performed using the nitride film and the resist as a mask to form a stack gate (see FIG. 3B). The width of the nitride film and the resist is 0.6 μm, and the distance between the nitride film and the resist is 0.
It is 3 μm.

[0004]

In the method of manufacturing a semiconductor device described above, different photomasks are used for patterning the nitride film and the resist. Due to the processing dimensional error and positional deviation of these photomasks, an error may occur in the patterns of the nitride film and the resist, and the stack gate may not be processed with a predetermined size and interval. Further, there is a limit to the miniaturization of the gate interval due to the above error. Therefore, there is a limit to high integration.

In view of the above-mentioned problems, the present invention proposes a method of manufacturing a semiconductor device which is not affected by a processing dimensional error of a photomask, a positional deviation, and the like, and which enables higher integration.

[0006]

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a NAND type memory cell having a stack gate. Conductor layers (for example,
A first step of forming a first insulating film (for example, SiO ₂ ) on a semiconductor substrate having polysilicon), thickening a predetermined portion of the first insulating film, and performing patterning;
A second step of forming a second insulating film (for example, a nitride film) and removing a portion of the pattern of the first insulating film formed in the first step, which will be a spacer in the vicinity of the side surface, A third step of forming a third insulating film (for example, SiO ₂ ) that serves as an etching mask using the spacer as a mask, the spacer is removed, and the portion where the spacer is present is etched to below the conductor layer to form a stack gate. And a fourth step of forming.

[0007]

In the method of manufacturing a semiconductor device according to the present invention, the first insulating film is patterned in the first step, and the spacer is formed in the vicinity of the side surface of the pattern in the second step. In the third step, the etching mask (third
Insulating film) is formed. At this time, the etching mask is formed in self alignment with the spacer. And
In the fourth step, the spacer portion is etched under the conductor layer to form a stack gate. The portion to be etched is almost the same as the width of the spacer, which is the distance between the stack gates.

[0008]

Embodiments of the present invention will be described with reference to the drawings.
Description of the same or equivalent elements as those of the above-mentioned conventional example will be simplified or omitted.

FIG. 1 and FIG. 2 show characteristic parts of the process of one embodiment of the present invention. This step is performed using a gas phase, and this step will be described step by step. First, on the semiconductor substrate 101, a thin SiO ₂ film 103 of about 20 to 150 Å and a polysilicon film 110 of 0.2 to 0.5 μm with a SiO ₂ film of about 50 to 300 Å or an ONO composite film 105 interposed. 1
20 is formed (see FIG. 1A). Next, a SiO ₂ film 210 having a thickness of about 0.1 to 0.7 μm is grown on the polysilicon film 120 and etched to have a predetermined shape.
This will be the first etching mask for later stack gate patterning. During etching of the SiO ₂ film 210, SiO ₂ of ₂₀ to 200 is formed on the polysilicon film 120.
Leave about angstroms. This is to serve as a stopper for later etching of the nitride film (see FIG. 1).
(See (b)).

A nitride film 220 is formed on the SiO ₂ film 210 (see FIG. 1C). Anisotropic plasma etching is performed on the nitride film 220 from the vertical direction to remove the SiO ₂ film 2.
The spacers 220a made of the nitride film 220 are left on the sidewalls of 10 (see FIG. 1D). The nitride film left on the side wall of the SiO ₂ film 210 becomes the spacer 220a. Next, 0.
A SiO ₂ film 230 having a thickness of about 1 to 0.7 μm is formed by CVD or thermal oxidation (see FIG. 2E). At this time, the spacer 220a acts as a mask for forming SiO ₂ , and the SiO ₂ film 230 is formed in a portion where the spacer 220a is not present. This is the second etching mask for stack gate patterning. The spacer 220a is removed by etching (see FIG. 2 (f)). Then, the polysilicon film 110 is etched using the portion of the SiO ₂ films 210 and 220 where the SiO ₂ is thick as an etching mask to form a stack gate (see FIG. 2G). Then, the drain region is formed to complete the memory cell.

In FIG. 2E, the thickened SiO ₂ portion serves as an etching mask for stack gate patterning, and the spacing between these masks is the spacer 22.
Determined by the width of 0a. Therefore, this space is equal to
The film thickness can be controlled by the film thickness at the time of film formation (FIG. 1 (c)), and it is possible to make the size very small. The distance between the stack gates is the same as the width of the spacer 220a, and this distance can be made very small depending on the film thickness of the nitride film 220, and higher integration can be achieved.

The SiO ₂ film 230 is the SiO ₂ film 2.
10 and spacers 220a are patterned,
No dedicated photomask is used. Therefore, SiO
_{The two} photomasks for the ₂ film 210 and the SiO ₂ film 230 are not affected by the processing dimensional error or the positional deviation.

[0013]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the etching mask is formed in a self-aligned manner with respect to the spacers, and the width of the spacers becomes the distance between the stack gates. The spacing of the stack gates can be adjusted by the width of the spacers without being affected by errors or displacement. Then, by reducing the width of the spacer, the distance between the stack gates can be reduced, and a highly integrated semiconductor device can be manufactured.

[Brief description of drawings]

FIG. 1 is a process diagram (first half) of an embodiment of the present invention.

FIG. 2 is a process diagram (second half) of an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a conventional example.

[Explanation of symbols]

101 ... Semiconductor substrate, 110, 120 ... Polysilicon,
210, 230 ... SiO ₂ film, 220 ... Nitride film, 220
a ... Spacer

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device having a NAND-type memory cell having a stack gate, wherein a first insulating film is formed on a semiconductor substrate having a conductor layer for the stack gate. A first step of thickening a predetermined portion of the first insulating film to perform patterning, a second insulating film is formed, and a pattern of the first insulating film formed in the first step is formed. A second step of removing a portion that becomes a spacer in the vicinity of the side surface; a third step of forming a third insulating film that serves as an etching mask by using the spacer as a mask; And a fourth step of forming a portion of the stack gate by etching the existing portion to the bottom of the conductor layer.