JP3028539B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a connection wiring film having good step coverage.

[Conventional technology]

In a method of manufacturing a semiconductor device, a technique of wiring connection between elements is a very important technique. Today, this wiring connection is performed by a method shown in FIGS. 3A to 3D using a good conductor metal such as aluminum.

In recent years, semiconductor elements and wiring intervals have been reduced with higher integration and higher density of semiconductor devices. However, there is no fundamental difference in a method of forming connection wiring.
The same applies to the case where the wiring has a laminated structure of two or more layers.

The conventional method for forming the connection wiring film will be described below in the order of steps. That is, as shown in FIG. 3A, an interlayer insulating film 4 is first deposited on the impurity diffusion layer 2 of the semiconductor element on the semiconductor substrate 1, and then a contact opening window is formed on the impurity diffusion layer 2. A photoresist pattern 6a for selective formation is patterned by photolithography. Next, as shown in FIG. 3B, a contact hole is opened on the impurity diffusion layer 2 using the resist pattern 6a as a mask. In the step of etching the interlayer insulating film 4, when the ratio (aspect ratio) between the diameter of the contact hole to be opened and the depth direction (aspect ratio) is reduced, when the wiring film is formed, the maximum value and the minimum value of the wiring film thickness at the periphery of the contact hole are reduced. Since the value ratio (step coverage) becomes large and causes disconnection of the wiring film, a vertical step in the depth direction of the contact hole is reduced to form a gentle slope (taper) near the surface of the opening. That is, the contact hole is opened by a combination of isotropic etching and anisotropic etching using the resist pattern 6a as a mask. Next, resist
The pattern 6a is removed, and a low-resistance metal film (for example, aluminum) 5 is deposited on the entire surface of the interlayer insulating film 4 including the opening of the contact hole by a sputtering method. After that, if the low resistance metal film 5 is subjected to reactive ion etching (RIE) using the photoresist pattern 6b as a mask, the connection electrode wiring film 8 can be obtained [FIGS. 3 (c) and (d)]. )reference〕.

[Problems to be solved by the invention]

However, this conventional method of forming connection wiring becomes extremely difficult to implement when the degree of integration and density of a semiconductor device is further advanced and the size of an element is significantly reduced. For example, recent field effect transistors (MO
In the case of an S transistor, for example, the distance between the source and drain electrodes and the gate electrode has been narrowed down to 1 μm or less. Since the thickness of the interlayer insulating film in which the lead-out contact hole is to be opened is formed to be considerably thicker than the thickness on the adjacent gate electrode, various drawbacks are revealed in the formation of the contact portion. Have been. In other words, if it is attempted to improve the step coverage of the connection wiring film by sufficiently forming a tapered portion in the contact hole and reducing the vertical step in the depth direction, as shown in FIG. 3 is exposed, and a short-circuit portion A is formed between the electrode 3 and the source or drain electrode wiring 7. Also, if the thickness of the interlayer insulating film 4 is increased to ensure sufficient coverage so that the gate electrode is not exposed, the tapering effect of the contact hole is lost and the step coverage of the connection wiring film is reduced.
As shown in the figure, a disconnection portion B occurs in the source and drain electrode wirings 7.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device that solves the drawbacks of the conventional connection wiring forming method, which cannot cope with high integration and high density of the semiconductor device in view of the above situation. .

[Means for solving the problem]

According to the method of manufacturing a semiconductor device, the first insulating film and the second insulating film having a lower etching rate than the first insulating film are formed on the semiconductor substrate on which the impurity diffusion layer is formed.
Forming a laminate including at least an insulating film, forming a first photoresist pattern on the first insulating film, and forming the first insulating film using the first photoresist pattern as a mask. A first etching step of exposing the second insulating film by taper etching
A step of covering the tapered portion formed in the first insulating film in the first etching step with a second photoresist pattern; and exposing the first and second photoresist patterns as masks. A second etching step of taper-etching the second insulating film;
And a third etching step of etching the remaining stacked body using the second photoresist pattern as a mask to expose the surface of the impurity diffusion layer.

(Operation)

According to the present invention, since two taper etchings are performed using the first and second resist masks while controlling the respective times, the contact holes having a small vertical step are insulated from the element structure on the semiconductor substrate. The film can be formed adjacent to the film without being thinned. Therefore, good step coverage can be easily provided to the connection wiring of the highly integrated and high-density semiconductor device.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

1 (a) to 1 (d) are process diagrams of forming a connection wiring according to a reference example of the present invention. In the present embodiment, a case where the present invention is applied to the formation of the source and drain electrode wirings of a MOS transistor is shown. First, a first photoresist pattern 6a is formed on the interlayer insulating film 4 by photolithography in order to selectively form a contact opening window in the same manner as in the prior art. Next, using the photoresist pattern 6a as a mask, the surface of the interlayer insulating film 4 is isotropically etched to form a gentle slope (taper) in the opening window (see FIG. 1A).
At this time, care should be taken to make the etching time shorter than in the prior art so as to sufficiently cover the insulating film on the polysilicon gate electrode 3 adjacent to the opening window. Here, reference numerals 1 and 2 denote a semiconductor substrate and a source (drain) impurity diffusion layer, respectively. Next, the first photoresist pattern
A photoresist film is applied again on the entire surface of 6a, and the whole surface is exposed. The tapered portion formed in the previous step is filled with a second photoresist pattern 6b, and the two photoresist patterns 6a and 6b are used as masks to re-isotropy. (See FIG. 1 (b)).

After the above-described two-stage taper etching, anisotropic etching is performed while leaving the photoresist patterns 6a and 6b, and the interlayer insulating film 4 is removed until the photoresist pattern 6a, 6b is reached. . By this opening method, the vertical spread of the contact opening window is substantially suppressed while suppressing the excessive expansion of the tapered portion in the lateral direction and maintaining sufficient insulation coverage on the polysilicon gate electrode adjacent to the opening window. Can be reduced. later,
After removing the photoresist patterns 6a and 6b, a low-resistance aluminum film 5 is deposited on the entire surface of the substrate using a sputtering method as before, and a third photoresist pattern 6c for wiring is formed by photolithography [ Referring to FIG. 1 (c)], reactive ion etching (RIE) is performed using the photoresist pattern 6c as a mask to form a predetermined source (drain) electrode wiring 7 [see FIG. 1 (d)]. ]. According to the present embodiment, since the vertical steps of the contact holes are substantially reduced, it is possible to obtain an electrode wiring having good step coverage.

FIGS. 2 (a) to 2 (d) are process diagrams of forming a connection wiring showing an embodiment of the present invention. According to the present embodiment, there is shown a case where the present invention is applied to a MOS transistor having a three-layer structure of the silicon oxide film 4a, the BPSG film 4b, and the liquid silicon oxide film 4c as the interlayer insulating film. The reason why the interlayer insulating film has the three-layer structure is to make the interlayer insulating film flatter by utilizing the reflow properties of the BPSG film and the liquid oxide film (see FIG. 2A). As in the previous embodiment, a first photoresist pattern 6a is formed on the uppermost liquid silicon oxide film 4c in order to selectively form a contact opening window, and then taper etching is performed using this as a mask [second. See FIG. At this time, the BPSG film
A large etching rate difference between the liquid silicon oxide film 4b and the liquid silicon oxide film 4c (for example, the etching rate of both is about 500Å / min for liquid silicon oxide film and about 200Å / min for BPSG film for 130BHF).
min) can be used. Next, the tapered portion immediately below the first photoresist pattern 6a is filled with a second photoresist pattern 6b, and the BPSG film 4b is again subjected to isotropic taper etching using the two photoresist patterns 6a and 6b as a mask. (See FIG. 2 (c)). Next, the remaining film of the BPSG film 4b and the silicon oxide film 4a are removed by reactive ion etching (RIE) using the two photoresist patterns 6a and 6b as masks to expose the surface of the source (drain) impurity diffusion layer 2. Finally, by removing the unnecessary photoresist patterns 6a and 6b,
Forming a contact hole for leading out a source (drain) electrode wiring with a small vertical step, which suppresses an excessive lateral spread of the tapered portion and sufficiently maintains insulation coverage on an adjacent polycrystalline silicon gate electrode 3. Can be. Therefore, the source (drain) electrode wiring 7 having good step coverage can be provided adjacent to the polysilicon gate electrode 3 as in the previous embodiment.

〔The invention's effect〕

As described above in detail, according to the present invention, a contact hole having a small vertical step is formed adjacent to an element structure on a semiconductor substrate by performing two-stage taper etching with a processing time shorter than that in the related art. Therefore, it is possible to easily form a connection wiring having good step coverage for a highly integrated and high-density semiconductor device.

[Brief description of the drawings]

1 (a) to 1 (d) are views showing a process of forming a connection wiring showing a reference example of the present invention, FIGS. 2 (a) to 2 (d) are views showing a process of forming a connection wiring showing an embodiment of the present invention, 3 (a) to 3 (d) are views showing a process for forming a conventional connection wiring, and FIGS. 4 and 5 are views each explaining a defect of a conventional method for forming a connection wiring. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Impurity diffusion layer, 3 ... Polycrystalline silicon gate electrode, 4 ... Interlayer insulating film, 4a ... Silicon oxide film, 4b ... BPSG film, 4c ... Liquid silicon oxide film , 5 ... aluminum film, 6a, 6b, 6c ... photoresist pattern, 7 ... source (drain) electrode wiring.

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Claims (3)

(57) [Claims] A step of forming a stacked body including at least a first insulating film and a second insulating film having a lower etching rate than the first insulating film on a semiconductor substrate on which an impurity diffusion layer is formed; Forming a first photoresist pattern on the first insulating film, and taper-etching the first insulating film using the first photoresist pattern as a mask to expose the second insulating film First
An etching step, a step of covering a tapered portion formed in the first insulating film in the first etching step with a second photoresist pattern, and a step of covering the first and second photoresist patterns.
A second etching step of taper-etching the exposed second insulating film using the photoresist pattern as a mask, and etching the remaining stacked body using the first and second photoresist patterns as a mask. A third etching step of exposing the surface of the diffusion layer. 2. The method according to claim 1, wherein said third etching step is anisotropic etching. 3. The laminate further warms a third insulating film,
The method according to claim 1, wherein the third insulating film is etched by the third etching step.