JP2004146812A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To quickly prevent a degradation in reliability of metal interconnections and signal delay even if a memory cell is miniaturized. <P>SOLUTION: There are provided: a plurality of first interconnections 3 arranged parallel to each together on a same layer, each of them connecting to a different contact portion; a plurality of second interconnections arranged alternately and parallel with the first interconnections on a same layer as the layer for the first interconnections, each of them connecting to a different contact portion; a plurality of first metal interconnections 7 that connect to the first interconnections through a first plug 6; and a plurality of second metal interconnections 13 formed on a different layer from the layer for the first metal interconnections through a second plug 12. The first and second metal interconnections are different from each other in at least one of thickness and width, or different from each other in resistance of interconnection materials, and a multiplied product of capacitance among the interconnections with resistance of the first metal interconnection is substantially equal to such product of the second metal interconnection. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a semiconductor memory device, and is particularly applied to a memory cell array structure having fine memory cells and metal wiring.

(4) Wiring formation in a conventional semiconductor memory device will be described with reference to FIGS. FIGS. 9A to 10B are cross-sectional views illustrating a process for manufacturing a metal wiring portion of a memory cell. First, for example, an interlayer insulating film 22 having a flat surface is formed to a thickness of 500 nm on the main surface of a P-type silicon semiconductor substrate 21 (see FIG. 9A). Next, a photoresist is applied to the entire surface of the interlayer insulating film 22, and a desired resist pattern (not shown) is formed by photolithography. Thereafter, the interlayer insulating film 22 is processed by dry etching using, for example, RIE (Reactive Ion Etching) using the resist pattern as a mask, and a groove having a depth of, for example, 100 nm is formed in the interlayer insulating film 22. Then, after forming a metal wiring having a laminated structure including a Ti layer 50 nm, a TiN layer 50 nm, and a W layer 250 nm from below, the surface is flattened to a desired height by chemical mechanical polishing (hereinafter referred to as CMP) and tungsten wiring is formed in the groove. 23 are formed (see FIG. 9B). The tungsten wiring 23 is connected to a diffusion layer in the substrate via a contact (not shown).

Next, an interlayer insulating film 24 is formed to a thickness of 500 nm on the entire surface of the interlayer insulating film 22 and the tungsten wiring 23. Thereafter, a photoresist is applied to the entire surface of the interlayer insulating film 24, a resist pattern (not shown) having an opening on a part of the tungsten wiring 23 is formed by photolithography, and then the interlayer insulating film is formed by dry etching. 24 is patterned to form a via hole having a depth of 500 nm reaching the tungsten wiring 23 in the interlayer insulating film 24. Then, a metal layer having a laminated structure of a Ti layer 50 nm, a TiN layer 50 nm, and a W layer 250 nm from the lower layer is formed so as to fill the via hole, the surface is flattened to a desired height by CMP, and tungsten is formed in the via hole. The plug 25 is formed.

Next, to cover the interlayer insulating film 24 and the tungsten plug 25, a barrier metal layer 26a consisting of a 50 nm thick Ti layer and a 50 nm TiN layer, an Al layer 26b having a thickness of 200 nm, and a 50 nm thick Ti layer and a 50 nm TiN layer. A metal wiring film 26 having a laminated structure having a barrier metal layer 26c is formed (see FIG. 9C).

Further, after applying a photoresist on the metal wiring 26 and forming a desired resist pattern by the photolithography technique, the metal wiring film 26 is processed by dry etching, and the metal wiring film 26 is formed at a desired position on the tungsten plug 25. 26A is formed (see FIG. 10A). Thereafter, a protective film 29 is formed on the metal wiring 26A (see FIG. 10B), thereby completing a part of the multilayer wiring process of the semiconductor memory device. Note that a top view of the semiconductor memory device shown in FIG. 10A before the protective film 29 is formed is shown in FIG. 11 with the interlayer insulating film 24 omitted.

However, in a semiconductor memory device, particularly, wires used for word lines and bit lines need to be formed with minimum design dimensions. As the memory cells are miniaturized, the wiring dimensions are simultaneously miniaturized. However, as shown in FIG. 12, the electromigration (hereinafter referred to as EM) characteristic showing the characteristics of the metal wiring depends on the wiring size, and it is known that in a region where the wiring size is small, the finer the wire, the more rapidly the deterioration occurs. Therefore, there is a problem that the reliability of the metal wiring is lost when the memory cell is miniaturized.

Further, as another problem caused by miniaturization, as shown in FIG. 13, the time constant τ (= C × R) increases due to the increase in the resistance R of the wiring and the increase in the capacitance C between the wirings, thereby causing a signal delay. I do. The occurrence of a delay in a signal line to which a signal is transmitted causes a change in driving of a transistor which requires a high-speed operation, which causes a reduction in device performance.

Note that in order to reduce the coupling capacitance between bit lines and reduce malfunctions, the semiconductor device has an upper layer wiring section and a lower layer wiring section. Is known (for example, see Patent Document 1).
JP-A-2002-57227

The present invention has been made in view of the above circumstances, and it is possible to prevent the occurrence of signal delay as much as possible without losing the reliability of wiring even if the memory cells are miniaturized. It is an object to provide a semiconductor memory device.

A semiconductor memory device according to a first aspect of the present invention includes a plurality of first connection lines arranged in parallel in the same layer and connected to different contact portions, respectively, and the first connection line in the same layer as the first connection line. A plurality of second connection lines alternately arranged with one connection line and in parallel with each other and connected to different contact portions; a plurality of first plugs respectively formed on the plurality of first connection lines; A plurality of second plugs respectively formed on the second connection wiring, a plurality of first metal wirings connected to the plurality of first plugs, and the plurality of first metal wirings formed on a layer different from the first metal wiring. A plurality of second metal wirings connected to two plugs, wherein the first and second metal wirings have at least one of a thickness and a width different from each other, and a wiring capacitance between the wirings of the plurality of first metal wirings. The product of the wiring resistance, the product of wiring capacitance and wiring resistance between wirings of the plurality of second metal wiring is characterized in that it is configured to be substantially the same.

A semiconductor memory device according to a second aspect of the present invention includes a plurality of first connection lines arranged in parallel in the same layer and connected to different contact portions, respectively, and the first connection line in the same layer as the first connection line. A plurality of second connection lines alternately arranged with one connection line and in parallel with each other and connected to different contact portions; a plurality of first plugs respectively formed on the plurality of first connection lines; A plurality of second plugs respectively formed on the second connection wiring, a plurality of first metal wirings connected to the plurality of first plugs, and the plurality of the plurality of metal wirings formed on a layer different from the first metal wiring. A plurality of second metal wires connected to a second plug, wherein the first and second metal wires are different from each other in at least one of a material and a configuration, and are provided between the plurality of first metal wires. The wiring capacitance and the product of the wiring resistance, the product of wiring capacitance and wiring resistance between wirings of the plurality of second metal wiring is characterized in that it is configured to be substantially the same.

According to the present invention, even if the memory cell is miniaturized, it is possible to prevent the occurrence of signal delay as much as possible without losing the reliability of the wiring.

Hereinafter, an embodiment of the present invention will be specifically described with reference to the drawings.

First, before describing a semiconductor memory device according to an embodiment of the present invention, a semiconductor memory device as a premise of the present embodiment will be described with reference to FIGS. 1A to 6 as a reference example. The semiconductor memory device according to this reference example is formed as follows.

First, for example, an interlayer insulating film 2 having a flat surface is formed to a thickness of 500 nm on a main surface of a P-type silicon semiconductor substrate 1 on which a memory cell array (not shown) and elements to be peripheral circuits are formed (see FIG. 1A). ). A gate line (not shown) is buried in the interlayer insulating film 2, and a wiring perpendicular to the gate line is formed on the surface of the interlayer insulating film 2. Specifically, a photoresist is applied to the entire surface of the interlayer insulating film 2, a desired resist pattern (not shown) is formed by photolithography, and then the interlayer insulating film 2 is dry-etched using the resist pattern as a mask. To form a groove (not shown) having a depth of 100 nm in the interlayer insulating film 2.

Thereafter, a metal wiring film having a stacked structure of a Ti layer 50 nm, a TiN layer 50 nm, and a W layer 250 nm from the lower layer is formed, and then the surface is flattened to a desired height by CMP, and a tungsten wiring 3 is formed in the groove. (See FIG. 1B). FIG. 5 shows a top view of the tungsten wiring 3 thus formed. FIG. 1B is a cross-sectional view taken along a cutting line AA shown in FIG. FIG. 6 is a cross-sectional view taken along a cutting line BB shown in FIG. As can be seen from FIG. 5, the tungsten wiring 3 has a contact portion 3a for connecting to a metal wiring to be a bit line described later, an N-type active region 28 formed on the silicon semiconductor substrate 1, and a bit line contact 27. And an elongate portion 3b connected thereto via a wire. Then, a tungsten wiring (lower tungsten wiring) 3 having a contact portion 3a on the lower side of FIG. 5 and a tungsten wiring (upper tungsten wiring) 3 having a contact portion 3a on the upper side are formed alternately. ing. The active region 28 is separated by a shallow device isolation insulating film 61 formed on the silicon substrate 1. In FIG. 6, the interlayer insulating film 2 is composed of two layers of interlayer insulating films. That is, the lower insulating film is made of BPSG (Boron Phosphorus Silicate Glass) for embedding a gate line (not shown), and the upper insulating film is made of SiO ₂ .

Next, an interlayer insulating film 4 having a thickness of 500 nm is formed so as to cover the interlayer insulating film 2 and the tungsten wiring 3 (see FIG. 1C). Thereafter, a photoresist is applied to the entire surface of the interlayer insulating film 4 and a resist pattern 5 having an opening 17 in a part on every other tungsten wiring 3 is formed by photolithography. Subsequently, using the resist pattern 5 as a mask, the interlayer insulating film 4 is processed by dry etching, for example, RIE, and a via hole 17 having a depth of 500 nm reaching the tungsten wiring 3 is formed in the interlayer insulating film 4 (FIG. 1). (D)). The contact opening resist used in this embodiment is a thermal flow resist, and can be reduced in diameter with respect to the dimension at the time of exposure.

Next, after the resist pattern 5 is removed, a metal film having a laminated structure including a Ti layer 50 nm, a TiN layer 50 nm, and a W layer 250 nm is formed from the lower layer so as to fill the via hole 17. The surface is flattened by height, and a tungsten plug 6 is formed in the via hole (see FIG. 2A).

Next, a barrier metal 7a composed of a lower 50 nm Ti layer and a 50 nm TiN layer, an Al layer 7b having a thickness of 200 nm, and a 50 nm thick Ti layer and a 50 nm TiN layer so as to cover the interlayer insulating film 4 and the tungsten plug 6. A metal wiring film having a laminated structure composed of the barrier metal 7c is formed in order, a photoresist is applied on the metal wiring film, and a desired resist pattern (not shown) is formed by photolithography. Using the pattern as a mask, the metal wiring film is processed by dry etching, for example, RIE, to form a metal wiring 7 having a thickness of 200 nm at a desired position on the tungsten plug 6 (see FIG. 2B).

(4) After removing the resist pattern, an interlayer insulating film 10 is formed on the entire surface so as to cover the metal wiring 7 as shown in FIG. Thereafter, a photoresist is applied to the entire surface of the interlayer insulating film 10 and a desired resist pattern 11 having an opening corresponding to the tungsten wiring 3 adjacent to the tungsten wiring 3 in contact with the tungsten plug 6 is formed by photolithography. After that, the interlayer insulating films 10 and 4 are processed using the resist pattern 11 as a mask by dry etching, for example, RIE, and a via hole 18 reaching the tungsten wiring is formed in the interlayer insulating films 10 and 4 (FIG. 2C). reference). At this time, the opened via hole 18 is to be connected to the contact portion 3a of the upper tungsten wiring 3 shown in FIG. 5, and appears on the drawing when it is cut along the cutting line CC shown in FIG. is there. The via hole 17 formed in FIG. 1D is connected to the contact portion 3a of the lower tungsten wiring 3 shown in FIG. 1A to 3 are cross-sectional views taken along a cutting line AA shown in FIG. As in the previous step, the contact opening resist used in this step uses a thermal flow resist, so that the diameter can be reduced with respect to the dimension at the time of exposure.

Next, after removing the resist pattern 11, as shown in FIG. 3, a metal film having a laminated structure including a Ti layer 50 nm, a TiN layer 50 nm, and a W layer 250 nm is formed so as to fill the via hole 18 from below. The surface is flattened by CMP, and the tungsten plug 12 is formed in the via hole 18.

Subsequently, a barrier metal 13a consisting of a 50 nm thick Ti layer and a 50 nm TiN layer, an Al layer 13b having a thickness of 200 nm, and a 50 nm thick Ti layer and a 50 nm TiN layer cover the interlayer insulating film 10 and the tungsten plug 12. A metal wiring film having a laminated structure having a barrier metal 13c is formed. Further, a photoresist is applied on the metal wiring film, a desired resist pattern is formed by a photolithography technique, and the metal wiring film is processed by dry etching, for example, RIE using the resist pattern as a mask. Then, a metal wiring 13 serving as a bit line is formed at a desired position on the tungsten plug 12. After removing the resist pattern, a protective film 16 is formed on the metal wiring 13 (see FIG. 3), thereby completing a part of the multilayer wiring process of the semiconductor memory device.

FIG. 4 shows a plan view of the wiring formed by this reference example. FIG. 4 is a plan view in which the interlayer insulating films 4, 10, and 16 are not shown. The semiconductor memory device according to the present reference example has a two-layer metal wiring structure in which a metal wiring 13 is added as compared with a conventional semiconductor memory device. In the present embodiment, the thickness of the metal wiring 7 and the metal wiring 13 and the space between the wirings are formed to be the same. Therefore, the delay of the signal transmitted through the metal wiring 7 and the delay of the signal transmitted through the metal wiring 13 are substantially the same.

As described above, according to the present embodiment, the spacing between adjacent metal wirings (space between wirings) and the pitch of the metal wirings are made larger than in the conventional case by adopting the two-layer metal wiring structure. And the width of the metal wiring can be increased. Thus, even if the memory cell is miniaturized, the metal wiring does not need to be miniaturized as compared with the conventional case, and it is possible to prevent the reliability of the metal wiring from lowering and the occurrence of signal delay.

(4) By adopting such a bit line structure, it is possible to form a wiring with a size smaller than the design rule, so that it is possible to manufacture a memory transistor which does not reduce the reliability of the metal wiring and the driving force of the transistor.

Next, the configuration of the semiconductor memory device according to one embodiment of the present invention will be described with reference to FIGS. FIG. 7 is a sectional view showing the configuration of the semiconductor memory device according to the present embodiment, and FIG. 8 is a plan view of the metal wiring of the semiconductor memory device according to the present embodiment.

In the semiconductor memory device according to this embodiment, the width b and the space c between the metal wires 7 and the metal wires 13 of the semiconductor memory device according to the reference example are the same, and one of the metal wires 7 and the metal wires 13, for example, metal. The thickness (film thickness) of the wiring 7 is 1 / x (x１ ／ 0) times the thickness (film thickness) a of the other metal wiring 13.

Assuming that the thickness of the metal wiring 7 is 1 / x times the thickness a of the metal wiring 13, the resistance R of the metal wiring 7 is x times the resistance of the metal wiring 13. The inter-capacitance C is 1 / x times the inter-wiring capacitance of the metal wiring 13. Therefore, in the present embodiment, the delay of the signal transmitted through the metal wiring 7 and the delay of the signal transmitted through the metal wiring 13 are substantially the same. In this embodiment, that the delay is substantially the same means that the product of the resistance R and the capacitance C between the wirings is within a range of ± 2%.

As described above, changing the thickness of one of the metal wirings without changing the material of the metal wirings 7 and 13, for example, making the thickness of the metal wiring 13 larger than the thickness of the metal wiring 7 is equivalent to the metal wiring 13. Is shared by the bit line of the memory cell array and the power supply line of the peripheral circuit area. In other words, global wiring such as power supply lines is generally provided in a layer above local signal lines, and the width of bit lines must be as narrow as possible for miniaturization, while power supply lines secure current density. Therefore, it is desired to increase the cross-sectional area as much as possible, and therefore, by increasing the thickness of the common metal wiring 13, it is possible to simultaneously satisfy the requirements for these. In this case, since the thickness of the metal wiring 7 is smaller than that of the metal wiring 13, the thickness of the interlayer insulating film 10 can be reduced, and the tungsten plug 12 can be more easily buried.

In the present embodiment, as in the case of the reference example, the two-layer metal wiring structure makes it possible to increase the distance between adjacent metal wirings and the pitch of the metal wiring as compared with the conventional case. Can be made wider. Thus, even if the memory cell is miniaturized, the metal wiring does not need to be miniaturized as compared with the conventional case, and it is possible to prevent the reliability of the metal wiring from lowering and the occurrence of signal delay.

Further, in the embodiment shown in FIGS. 7 and 8, the thickness of one metal wiring is changed without changing the material of the metal wiring 7 and the metal wiring 13, but in another embodiment of the present invention, the thickness of one metal wiring is changed. A material may be used in which the specific resistance of the metal wiring is different from the specific resistance of the other metal wiring. In this case, the sum of the wiring width b and the space c between the wirings is the same for the metal wiring 7 and the metal wiring 13 and the wiring width of one of the metal wirings is changed or the interlayer insulating film 10 between the metal wirings 7 and the metal wiring By using materials having different dielectric constants for the insulating films 16 between the 13, the product of the wiring resistance R and the capacitance C between the wirings is made substantially the same in the metal wiring 7 and the metal wiring 13. In particular, when the metal wiring 13 is shared with a power supply line in the peripheral circuit region, for example, when copper is used as the material of the metal wiring 13, the current density of the power supply line can be increased because the specific resistivity is low. There is a merit. In this case, if the interlayer insulating film 10 between the metal wires 7 is made of a material having a low relative dielectric constant, signal transmission can be performed at high speed even if the lower metal wire 7 is used as a signal line on the peripheral circuit side. .

Also, as in the embodiment shown in FIGS. 7 and 8, the wiring material is not changed between the metal wiring 7 and the metal wiring 13 while the product of the resistance R and the capacitance C between the wirings is made substantially the same. The width and the relative dielectric constant of the insulating film between the wirings may be different. That is, in another embodiment of the present invention, between the metal wiring 7 and the metal wiring 13, two or three of the specific resistivity of the wiring material, the wiring width, and the relative permittivity of the insulating film between the wirings are used. It is preferable that the product of the wiring resistance R and the capacitance C between the wirings is substantially the same for the metal wiring 7 and the metal wiring 13. At this time, the metal wiring 7 and the metal wiring 13 may have the same thickness or different thicknesses as shown in FIG.

When the material of the metal wiring 7 and the material of the metal wiring 13 are changed, as shown in FIG. 15, one metal wiring may be formed as a single layer and the other metal wiring may be formed as a multilayer (two layers in FIG. 15). In this case, the wiring thickness a, the wiring width b, and the wiring space c are the same for the metal wiring 7 and the metal wiring 13, and the product of the wiring resistance R and the wiring capacitance C is the same as the metal wiring 7 and the metal wiring 13. Should be substantially the same. For example, in FIG. 15, the metal wiring 7 has a single-layer structure, and the metal wiring 13 has a two-layer structure including wiring layers 13A and 13B. Is ρ, the wiring thickness of the wiring layer 13A is a1, the wiring width is b, the specific resistivity is ρ1, the wiring thickness of the wiring layer 13B is a2, the wiring width is b, and the specific resistivity is ρ2. It is assumed that the length L is the same and the materials of the interlayer insulating film 10 and the protective film 16 are the same. Then, the resistance R of the metal wiring 7 is R = ρ × L / (b × a), the resistance R1 of the wiring layer 13A is R1 = ρ1 × L / (b × a1), and the resistance R2 of the wiring layer 13B is R2 = ρ2 × L / (b × a2). Therefore, if the resistance of the metal wiring 13 is made equal to the resistance R of the metal wiring 7, that is,
1 / R = 1 / R1 + 1 / R2 (1)
Then, the product of the wiring resistance R and the capacitance C between the wirings is substantially the same in the metal wiring 7 and the metal wiring 13.

The thickness a of the metal wiring 13 is the sum of the thickness a1 of the wiring layer 13A and the thickness a2 of the wiring layer 13B, that is, a = a1 + a2 (2)
It is.

When the specific resistances ρ, ρ1, and ρ2 are known and the thickness a1 of the wiring layer 13A and the thickness a2 of the wiring layer 13B are obtained from the above equations (1) and (2), the values a1, a2 are the wiring resistances. A solution in which the product of R and the capacitance C between wirings is substantially the same for the metal wiring 7 and the metal wiring 13 is provided. In the example shown in FIG. 15, the metal wiring 13 has a two-layer structure, but may have a multilayer structure of three or more layers.

(4) Both the metal wiring 7 and the metal wiring 13 may have a multilayer structure made of different materials, or may have a multilayer structure made of the same material, and the thickness of each layer in the multilayer structure may be changed. As described above, when the materials of the members of the multilayer structure of the metal wiring 7 and the metal wiring 13 are different or the configurations such as the thickness of the members are different, when the combined resistances R of the metal wiring 7 and the metal wiring 13 are different. It is necessary to change the wiring width of the metal wiring and the material of the interlayer insulating film between the metal wirings so that the product of the wiring resistance R and the capacitance C between the wirings is substantially the same in the metal wiring 7 and the metal wiring 13. is there.

As another example in which copper is used as the material of the upper metal wiring 13 and a material having a higher specific resistivity than the metal wiring 13, for example, aluminum, is used for the lower metal wiring 7, as shown in FIG. One example is a semiconductor memory device 30 in which a circuit 32 and a logic circuit 34 are mounted on one chip. It goes without saying that the present invention is also applicable to the semiconductor memory device 30 in which the memory circuit 32 and the logic circuit 34 are mounted on one chip.

FIG. 16 is a cross-sectional view of a specific example of the semiconductor memory device 30 in which the memory circuit 32 and the logic circuit 34 are mounted on one chip. The memory circuit 32 is an EEPROM, and is formed on a semiconductor substrate 40 so that a plurality of electrically rewritable memory cells 41 selected by a word line are connected in series to form a NAND cell. Each memory cell 41 becomes a floating gate 41b formed via a tunnel oxide film 41a, an interlayer gate insulating film 41c formed on the floating gate 41b, and a word line formed on the interlayer gate insulating film 41c. A control gate 41d is provided. Each memory cell 41 is connected in series via a source / drain diffusion layer 42.

The NAND cell is connected to a wiring 47 via a contact 45 provided on the interlayer insulating film 44. The wiring 47 is embedded in an interlayer insulating film 46 formed on the interlayer insulating film 44. The wiring 47 is connected to a first bit line 50 via a via 49 provided in an interlayer insulating film 48 covering the wiring 47. Note that another NAND cell (not shown) is connected to another wiring (not shown) in the same layer as the wiring 47 embedded in the interlayer insulating film 46, and this other wiring is connected to the interlayer insulating film 48 and the first bit line 50. It is connected to a second bit line 53 via a via 52 shown by a broken line provided in an interlayer insulating film 51 formed thereon.

On the other hand, in the logic circuit 34, transistors 60a and 60b constituting a logic element are formed on the semiconductor substrate 40, and the transistors 60a and 60b are element-isolated by the element isolation insulating film 61. The source / drain diffusion layer 42 of each transistor is connected to a pad 47a via a contact 45a provided on an interlayer insulating film 44. The pad 47a is embedded in an interlayer insulating film 46 formed on the interlayer insulating film 44. The pad 47a is connected to wirings 50a and 50b that are in the same layer as the first bit line 50 via a via 49a provided in the interlayer insulating film 48, or formed on the interlayer insulating films 48 and 51. It is connected to the wiring 53a via the via 52a. The wiring 50b is connected to the wiring 53b via a via 52b formed in the interlayer insulating film 51. The wirings 53a and 53b are in the same layer as the second bit line 53. The wiring 53a is connected to a wiring 57 via a via 54 provided in an interlayer insulating film 55 covering the wirings 53a and 53b. The wiring 57 is embedded in an interlayer insulating film 56 formed on the interlayer insulating film 55. The reason why various types of wiring layers are used in the logic circuit 34 is to optimize the configuration of the wiring pattern with respect to area or distance.

As shown in FIG. 16, in a semiconductor memory device in which the memory circuit 32 and the logic circuit 34 are mixed, wirings and interlayer insulating films are commonly shared between these circuits. Further, the thickness, material, and material of the interlayer insulating film are selected so that the wiring pattern in the logic circuit 34 is optimized. In addition, in the embodiment shown in FIG. 16, for example, by making the wiring widths of the first bit line 50 and the second bit line 53 different from each other, the product of the wiring capacitance and the wiring resistance between the wirings of the first bit line 50 is reduced. , And the product of the wiring capacitance and the wiring resistance between the wirings of the second bit line 53 is substantially the same. In FIG. 16, the first bit line 50 of the memory circuit 32 is formed so as to be in the same layer as the wirings 50a and 50b of the logic circuit 34, and the second bit line 53 is formed in the same layer as the wirings 53a and 53b of the logic circuit 34. However, the logic circuit 34 may be formed so as to be in the same layer as the other wiring layers.

Further, in the embodiment shown in FIGS. 7 and 8, the metal wirings 7 and 13 are processed by using RIE as a forming method. However, as in the embodiment shown in FIG. When copper is used as the wiring material, damascene wiring can be used. When a damascene wiring is used, a material having a low dielectric constant can be preferably used as an interlayer insulating film provided between the wirings. As described above, when a low-resistance material (for example, copper) is used as a metal wiring material and a low-dielectric-constant material is used as an insulating film material between metal wirings, it is effective for wiring that requires high-speed signal transmission. It is.

{Furthermore, it goes without saying that the present invention is not limited to the embodiments described above, and can be applied to various semiconductor memory devices such as DRAM, SRAM, EPROM, EEPROM, and ferroelectric memory.

As described above, according to the embodiment of the present invention, even if the memory cell is miniaturized, a reduction in the reliability of the metal wiring and the occurrence of signal delay can be prevented as much as possible.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of a semiconductor memory device according to a reference example of one embodiment of the present invention. FIG. 4 is a cross-sectional view illustrating a manufacturing process of a semiconductor memory device according to a reference example of one embodiment of the present invention. FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor memory device that is a reference example of one embodiment of the present invention. FIG. 4 is a plan view of metal wiring of a semiconductor memory device of a reference example. FIG. 3 is a plan view showing a configuration of a tungsten wiring. FIG. 6 is a cross-sectional view taken along a cutting line BB shown in FIG. 5. FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a plan view of a metal wiring of the semiconductor memory device according to the embodiment of the present invention. Sectional drawing of the manufacturing process of the conventional semiconductor memory device. Sectional drawing of the manufacturing process of the conventional semiconductor memory device. FIG. 9 is a plan view of metal wiring in a conventional semiconductor memory device. FIG. 5 is a diagram illustrating electromigration characteristics of a wiring. The figure which shows the relationship between a wiring width and the time constant of a wiring. FIG. 4 is a block diagram showing a configuration of a semiconductor memory device in which a memory circuit and a logic circuit are mounted. FIG. 14 is a cross-sectional view illustrating a configuration of a semiconductor memory device according to a modification of one embodiment of the present invention. FIG. 11 is a cross-sectional view illustrating a configuration of an example of a semiconductor memory device in which a memory circuit and a logic circuit are mixed.

Explanation of reference numerals

Reference Signs List 1 silicon semiconductor substrate 2 interlayer insulating film 3 tungsten wiring 4 interlayer insulating film 5 resist pattern 6 tungsten plug 7 metal wiring 7a barrier metal 7b Al layer 7c barrier metal 10 interlayer insulating film 11 resist pattern 12 tungsten plug
13 metal wiring 13a barrier metal 13b Al layer 13c barrier metal 16 protective film 17 via hole 18 via hole 51 element isolation insulating film 53 active region 57 bit line contact

Claims (15)

A plurality of first connection lines arranged in parallel in the same layer and connected to different contact portions, respectively; and a plurality of first connection lines arranged alternately in parallel with the first connection lines in the same layer as the first connection lines, respectively. A plurality of second connection lines connected to different contact portions, a plurality of first plugs respectively formed on the plurality of first connection lines, and a plurality of second plugs respectively formed on the plurality of second connection lines A second plug, a plurality of first metal wirings connected to the plurality of first plugs, and a plurality of second metal wirings formed in a different layer from the first metal wiring and connected to the plurality of second plugs; Wherein the first and second metal wirings have at least one of a thickness and a width different from each other, and a product of a wiring capacitance and a wiring resistance between the wirings of the plurality of first metal wirings; The semiconductor memory device characterized by a wiring capacitance and the wiring resistance product between wirings are configured to be substantially identical. 4. The semiconductor memory device according to claim 1, wherein the first and second metal wirings are made of the same material and form bit lines of a memory cell array. 3. The semiconductor memory device according to claim 2, wherein the first metal wiring is formed below the second metal wiring and is thinner than the second metal wiring. 4. The semiconductor memory device according to claim 3, wherein said second metal wiring forms a power supply line in a peripheral circuit region of a memory cell array. A plurality of first connection lines arranged in parallel in the same layer and connected to different contact portions, respectively; and a plurality of first connection lines arranged alternately in parallel with the first connection lines in the same layer as the first connection lines, respectively. A plurality of second connection lines connected to different contact portions, a plurality of first plugs respectively formed on the plurality of first connection lines, and a plurality of second plugs respectively formed on the plurality of second connection lines A second plug, a plurality of first metal wirings connected to the plurality of first plugs, and a plurality of second metal wirings formed in a different layer from the first metal wiring and connected to the plurality of second plugs; Wherein the first and second metal wirings are different from each other in at least one of a material and a configuration, and a product of a wiring capacitance and a wiring resistance between the wirings of the plurality of first metal wirings; The semiconductor memory device characterized by a wiring capacitance and the wiring resistance product between wires tal wires are configured to be substantially identical. 6. The semiconductor memory device according to claim 5, wherein said first and second metal wirings form bit lines of a memory cell array. 6. The semiconductor memory device according to claim 5, wherein at least one of the first and second metal wirings has a multilayer structure in which different materials are stacked. 8. The semiconductor memory device according to claim 7, wherein the first and second metal wirings have the same width and thickness. The first metal wiring is formed below the second metal wiring, and the material of the second metal wiring is lower in specific resistivity than the material of the first metal wiring. 6. The semiconductor memory device according to claim 5, wherein a relative dielectric constant of an insulating film provided in said first metal wiring is lower than a relative dielectric constant of an insulating film provided between said plurality of second metal wirings. The first metal wiring is formed below the second metal wiring, the second metal wiring forms a power supply line in a peripheral circuit region of a memory cell array, and the first metal wiring forms a signal line in the peripheral circuit region. 7. The semiconductor memory device according to claim 6, wherein said semiconductor memory device is formed. 6. The semiconductor memory device according to claim 1, wherein relative dielectric constants of insulating films provided between the plurality of first metal wirings and between the plurality of second metal wirings are different from each other. 12. The semiconductor memory device according to claim 1, wherein at least one of the first and second metal wirings is a damascene wiring. 6. The semiconductor memory according to claim 1, wherein a memory circuit having a memory cell array and a logic circuit are mounted on the same chip, and the first and second metal wirings form bit lines of the memory cell array. apparatus. 14. The semiconductor memory device according to claim 13, wherein the first and second metal wirings further form a wiring pattern of the logic circuit. 15. The method according to claim 14, wherein the first metal wiring is formed below the second metal wiring, a material of the first metal wiring is aluminum, and a material of the second metal wiring is copper. Semiconductor storage device.

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