KR20050014839A - Enhanced structure and method for buried local interconnects - Google Patents

Abstract

Disclosed are a structure and method for forming an embedded circuit (10) of an integrated circuit in a single crystal semiconductor layer (12) of a substrate. This buried interconnect consists of deposited conductors and has one or more sidewalls 18 in contact with a single crystal region of the electronic device 20 formed in a single crystal semiconductor layer.

Description

Structure of buried local interconnects and its formation method {ENHANCED STRUCTURE AND METHOD FOR BURIED LOCAL INTERCONNECTS}

In the microelectronics industry, there is a continuing need for high-density, high-speed, compact microcircuits, specifically memory cells and support circuits. Different solutions are being implemented to achieve the highest density, speed and desired size requirements.

In semiconductor processes, older expertise such as silicon-on-insulator (SOI) is more widely used to meet the demand for high-speed integrated circuits. In SOI technology, a relatively thin layer of semiconductor material, usually silicon (Si), is disposed over a layer of insulating material, commonly referred to as a buried oxide (BOX). This relatively thin semiconductor material layer is generally a region in which an active element is formed in an SOI element.

Integrated circuits are made of various electronic semiconductor devices such as resistors, transistors, diodes, and capacitors that are fabricated together in a combination process on a semiconductor substrate. A substrate refers to one or more semiconductor layers or structures that include active or operable portions of a semiconductor device. An important aspect of the manufacture of integrated circuits is the electrical interconnection of active elements through interconnect structures.

The interconnect structure usually includes a region of conductive material formed between semiconductor elements in which electrical contact is made. This interconnect serves as a conduit for transferring current between semiconductor devices. Certain types of interconnect structures known to those skilled in the art include, for example, M0, M1 wiring level local interconnects, buried contacts, vias, studs, surface straps, and buried straps. . Sometimes a diode may function as an interconnect between semiconductor elements. Diodes can be formed in a semiconductor substrate by combining active regions of different carrier types.

One type of frequently used interconnect structure is a buried contact. This buried contact can be a region of polysilicon that makes integrated contact between the interconnect structure and the active region, eliminating the need for metal connections. In forming the buried contacts, windows are formed in the gate oxide of the thin film over the active region to which the interconnect structure must be electrically connected. Thus, polysilicon is deposited in direct contact with the active region of the formed opening, but is separated from the silicon underlying the active region by the field oxide and by the gate oxide in other portions of the semiconductor substrate. Ohmic contact is formed by diffusion of the dopant preset in the polysilicon into the active region at the interface between the polysilicon and the active region. Dopant diffusion into the active region effectively merges the active region with polysilicon. An insulating film layer is deposited to cover the buried contacts. The buried contact is so called because the metal layer can traverse the active region forming the buried contact without electrical connection with the buried contact.

In some cases, multiple metal interconnects are stacked on top of each other, taking into account the increasing density of the circuitry involved. Typically, the density of the device is reduced in each successive metal layer. This is because such hierarchical configurations in density must mask overlay errors that each accumulate with additional interconnect layers. For example, if a contact is required between the active region AA and the second metal layer M2, a second via is formed so that M1 and M2 are interconnected after forming a via between AA and the second metal layer M1. Should be. The total overlay tolerance of AA for the M2 contact is the sum of the tolerances of the AA-M1 and M1-M2 contacts. Accordingly, the property to increase circuit density by adding mutual contact layers is limited.

In many cases, it is difficult to provide adequate manufacturing tolerances while meeting size, speed, and density requirements. There is a need for new structures that allow for increased circuit density, while maintaining manufacturing tolerances at workable levels.

FIELD OF THE INVENTION The present invention relates to semiconductor front end of line (FEOL) processes, and more particularly to buried local interconnects formed at the transistor level.

1, 1A, 9 and 10 are diagrams showing a buried interconnect structure according to an embodiment of another method of the present invention.

2 through 8 are diagrams illustrating the manufacturing steps of the buried interconnect structure according to the embodiment of the present invention.

According to one aspect of the invention, a structure and method are provided for forming an embedded interconnect of an integrated circuit in a single crystal semiconductor layer of a substrate. The buried interconnects consist of deposited conductors and have one or more vertical sidewalls in contact with a single crystal region of an electronic device formed in a single crystal semiconductor layer.

According to another aspect of the invention, forming a trench isolation region in a substrate and forming a trench in a single crystal region of the substrate adjacent the isolation region, wherein the trench is a bottom separated in the single crystal region. And a sidewall adjacent the trench isolation region, and depositing a conductor in the trench, wherein the conductor is in contact with a single crystal region on at least one sidewall of the trench. From contacting the deposited conductor.

1 illustrates a buried interconnect structure according to a silicon-on-insulator (SOI) embodiment of the present invention. As shown in FIG. 1, the buried interconnect 10 is formed in a single crystal semiconductor layer (SOI layer) 12 of an SOI substrate with a buried oxide layer (BOX) 14 disposed over a support substrate 16. . The buried interconnect 10 is almost vertically oriented (hereinafter, “contacted”) in contact with the single crystal region 12 of the electronic device 20 formed in the SOI layer 12, which may be, for example, a transistor, diode, capacitor or resistor. Side wall 18).

In the case where the electronic device 20 is an insulated gate field effect transistor (IGFET), the vertical sidewall 18 of the buried interconnect 10 may be a body or diffusion region (e.g. , Source / drain diffusion region). If the electronic device 20 is a diode or a depletion diode, the vertical sidewall 18 of the buried interconnect 10 may be in contact with the diffusion region of that device.

The buried interconnect 10 is manufactured to extend in a direction substantially parallel to the substrate 16 (extending in and out of the page of FIG. 1). In this way, the buried interconnect 10 may be a vertical sidewall, or another single crystal region of the substrate that may contact one or more single crystal regions 12 of another electronic device through other sidewalls that are not separated. 12) Pass right by. An isolation region 28 (eg, trench isolation), which extends at least a portion of the length of the buried interconnect 10 in and out of the ground, extends along the sidewall 30 from other electronic devices except where contact is required. Isolate the buried interconnect 10. If contact with other electronic devices is desired, contact may be made along portions of the sidewall 30 where there is no isolation region 28.

The buried interconnects 10 may be polysilicon, metal silicides (e.g., WSi _x , CoSi _x , TiSi _x ), deposited polysilicon followed by silicidation or even deposited metal self-aligned with subsequent metal deposits. And a deposited conductor such as tungsten (W), or a refractory metal or titanium (Ti), niobium (Nb), zirconium (Zr), tantalum (Ta), molybdenum (Mo) or That layer is good. The buried interconnect may be aligned with a liner 32 comprising a nitride of a deposited conductor metal or a nitride of a similar metal, such as tungsten nitride, or titanium nitride or tantalum silicon nitride (TaSiN). Alternatively, particularly in the case where the deposited conductor is polysilicon, the silicon nitride of the ultra thin layer (for example, 7 GPa or less) can be used as will be described fully below.

The buried interconnect 10 is preferably conductively coupled to a conductive line 22 formed on the substrate, the conductive line 22 being for example a gate conductor or a MOS element 24 (“MOS”, ie an insulated gate). , A polysilicon conductor capable of forming a "polyconductor" of a field effect transistor or MOS capacitor), the gate conductor being disposed over the gate dielectric 26 formed over the SOI layer 12. Polyconductor 22 is shown in FIG. 1 as a gate conductor connecting a MOS device, such as MOSFET 24, to the source / drain region 20 of another electronic device, such as another MOSFET. MOSFETs can be connected in a manner that uses a pair of mutually coupled COMSFETs, such as multiple latches, flip-flops, drivers, or even static random access memory (SRAM).

Alternatively, the polyconductor 22 can be patterned to extend only as an interface to the buried interconnect 10 over the STI 28 and the oxide 46. Alternatively, the polyconductor 22 may extend over the gate dielectric of the MOSFET device 20, with the body of the buried interconnect 10 electrically contacting through the sidewall 18. In this case, the body of the MOSFET 20 is tied to the same voltage as the gate conductor 20. Such a gate and body interconnect allows the MOSFET 20 to operate as a variable threshold voltage element at which the threshold voltage drops as the gate conductor voltage rises.

1A is a plan view illustrating an exemplary semiconductor device layer layout in which buried interconnects are formed in accordance with the present invention. In such a layout, regions 110 and 210 represent buried interconnects and regions 120 and 220 represent active regions of the substrate. In the example shown, n-channel IGFETs (NFETs) are preferably formed in the active region 120, and p-channel (PFETs) are preferably formed in the active region 220. Polyconductors 122, 222 and 322 are shown traversing over portions of active regions 120 and 220, such as the gate conductors of NFETs and PFETs therein. The first buried interconnect 110 has one or more sidewalls 118, 119 in contact with the source / drain regions of the NFET in a single crystal region (active region 120). The buried interconnect 110 also has sidewalls 218 and 219 in contact with another device in the single crystal region (active region 220), namely the source / drain region of the PFET. Thus, as will be appreciated, a single buried interconnect has one or more sidewalls in contact with one or more single crystal regions of a plurality of electronic devices (eg, NFETs and PFETs). A buried contact 248 is formed between the polyconductor 122 and the buried interconnect 110 to establish a conductive interconnect for the polyconductor 122.

Similarly, the second buried interconnect 210 has one or more sidewalls that contact the electronic device, ie the source / drain regions of the NFET, in a single crystal region (active region 120). The buried interconnect 210 also has sidewalls 418 and 419 in contact with another device in the single crystal region (active region 220), namely the source / drain region of the PFET. A buried contact 248 is formed between the polyconductor 122 and the buried interconnect 210 to form a conductive interconnect for the polyconductor 122.

2-7 illustrate the manufacturing steps of the buried interconnect 10 shown in FIG. 1 in an SOI process embodiment. As shown in FIG. 2, a shallow trench isolation region (STI) 28 is formed in the SOI layer 12 of the substrate on which the buried oxide layer (BOX) 14 is disposed on the support substrate 16. STI 28 extends to BOX layer 14 to separate electronic elements formed in SOI layer 12 on their respective sides. Pad nitride 24 covers SOI layer 12 at a location other than STI 28.

Next, as shown in FIG. 3, a photoresist is applied and patterned to form a mask 36, adjacent to the STI 28 on at least one side and the SOI layer 12 on at least one other side. The opening 35 may be etched using a directed reactive ion etching (RIE) method. This etching may be done in a timed manner, or may be stopped when reaching the support substrate 16. And the mask 36 is removed. The exposed sidewall 13 of the SOI 12 may be passivated at this point to remove surface damage to the single crystal SOI layer using timed sidewall oxidation, subsequent oxide removal, and the like.

Next, as shown in FIG. 4, the oxide is deposited by high density plasma deposition to form a separation layer 38 at the bottom of the trench and an oxide 40 on the surface. The oxides attached to the sidewalls 13 of the openings 35, including any oxides generated from the selectable passivation process described above, are removed at this point (e.g., using isotropic etching). Subsequently, as shown in FIG. 5, it is preferable to attach the liner 32 to first line the opening, and then deposit the conductor 44 to fill the opening 35. Various materials may be deposited as the conductor 44, including polysilicon, tungsten (W), niobium (Nb), zirconium (Zr), tantalum (Ta), molybdenum (Mo) and silicides. Metal, and nitrides of such metals or layers thereof. In the case where the conductor 44 is formed by depositing a refractory metal such as tungsten, the liner 32 is preferably formed by depositing a material that promotes adhesion such as tungsten nitride or titanium nitride.

When the conductor 44 is formed by depositing polysilicon, the polysilicon may be heavily doped at the time of deposition. However, the polysilicon may be doped by the following deposition method. When the conductor 44 is made of polysilicon, there is no need to use the liner 32 for adhesion. However, for other reasons, it is preferable to use a liner to line the opening 35 with a barrier layer of a conductive material or even an ultra thin silicon nitride layer. Ultra thin films, such as silicon nitride layers of up to 7 microseconds, are known to be conductive because of quantum tunneling through the ultra thin layers. Such barrier layers function to delay dopant diffusion from polysilicon to adjacent SOI regions 12 and / or to prevent recrystallization of polysilicon at the interface between conductor 44 and SOI regions 12. . Recrystallization should be avoided because it potentially causes crystal defects in the SOI region 12, which in turn can undermine the performance of the electronic devices formed therein.

After depositing conductor 44, the substrate may be subjected to a process such as pad nitride (CMP) selective to nitride to remove deposited conductors and deposited oxides from the top surface of the substrate. It is flattened to the level of 34), and the structure shown in FIG. The conductor 44 and the liner 32 are then formed with recesses by a directional etching such as a reactive ion etching method selective for oxides and nitrides, resulting in the structure shown in FIG.

Subsequently, as shown in FIG. 7, the oxide layer 46 on the upper surface is formed on the conductor 44. This deposits the oxide in a high density plasma process, then planarizes the oxide 46 to the level of the pad nitride 34 (using a CMP process selective to nitride), and then the remaining pads from the SOI region 12. It is preferably done by removing the nitride 34.

Now, referring back to the completed structure shown in FIG. 1, a further process for forming the buried contact portion 48 from the polyconductor 22 will be described. Polyconductor 22 may be, but need not necessarily, a gate conductor of one or more electronic devices disposed in SOI region 12. This process is preferably performed after performing any necessary ion implantation into the device 24 and optionally for the device 20, and then forming the gate insulator 26 by either the oxidation method or the deposition method. The photoresist is then applied and patterned to form a window for etching the contact openings in the deposited top oxide 46. The photoresist is then peeled off, and heavily doped polysilicon is deposited and patterned to form a buried contact with the polysilicon 22 shown.

8 and 9 illustrate the steps of an alternative process of completing the buried interconnect 10. FIG. 9 shows a complete structure consisting of another process of forming a buried contact 50 in the buried interconnect 10 from the second conductor 52 in contact with the polyconductor 22. The structure shown in FIG. 9 differs from the structure of FIG. 1 in that the buried interconnect 10 has sidewalls that contact the body of the electronic element 20A formed in the SOI layer 12. This is because the SOI layer 12 in which contact is made under the gate insulator 26 and the polyconductor 22 is used as the gate conductor there. The contact of the electronic element 20A by the buried interconnect 10 with the main body is only one possible embodiment, and this process focuses on the use of the second conductor 52 in contact with the polyconductor 22. It is not necessary. The second conductor 52 may be composed of any suitable material, such as heavily doped polysilicon, metal silicide, or the metal itself.

In the other process, the process proceeds through the formation of the gate insulator in the manner described above with reference to FIGS. 2 to 7. Then, as shown in FIG. 8, the polyconductor 22 is deposited. This differs from that described above with respect to FIG. 1 in that the polyconductor layer 22 is deposited over the gate insulator 26 to form a buried contact 48 prior to etching the opening through the oxide layer 46. This process sequence is desirable to prevent possible interactions between the gate resist 26 and the photoresist used to pattern the contact openings.

Referring again to FIG. 9, a photoresist is applied and patterned to define the polyconductor layer 22 where it is etched to form contact openings. A second conductor layer 52 is deposited over the polyconductor layer 22 and in the contact openings to form the buried contact 50. The photoresist is then applied and patterned, and the second conductor 52 and the polyconductor layer 22 are etched together in one combination etching method, such as directional reactive ion etching. Polyconductor 22 is formed.

10 illustrates a completed buried interconnect structure 10 formed in accordance with another embodiment of the present invention when formed on a bulk semiconductor substrate as opposed to an SOI substrate. The process proceeds in the same manner as described above with reference to the embodiments of FIGS. 1-7 or 2-9, except as now described. Referring to FIG. 4, since the bulk substrate embodiment has no buried oxide layer, the oxide 38 may be embedded buried in order to prevent unwanted leakage current from the source / drain diffusion region 20B to the bulk substrate 17. 10 needs to be deposited in the high level openings 35 in a manner that contacts the device layer 20B, such as source / drain diffusion of the electronic device, rather than the bulk substrate 17.

While the invention has been described above with reference to certain preferred embodiments, those skilled in the art will recognize that various modifications and improvements can be made without departing from the spirit and scope of the invention, which is limited only by the claims appended hereto.

The present invention can be used in integrated electronic circuits and their fabrication.

Claims (21)

An integrated circuit comprising a buried interconnect formed on a single crystal semiconductor layer of a substrate, Wherein the buried interconnect is comprised of deposited conductors and has one or more vertical sidewalls in contact with a single crystal region of an electronic device formed in the single crystal semiconductor layer. The integrated circuit of claim 1 wherein a plurality of electronic devices are contacted in a single crystal region by the buried interconnects through the one or more vertical sidewalls. The integrated circuit of claim 1 wherein the buried interconnect has at least one sidewall in contact with a separation region on one side other than the vertical sidewall in contact with the single crystal region. The integrated circuit of claim 1, wherein the single crystal region contacted by the buried interconnect comprises at least one diffusion region of at least one of the electronic devices. The integrated circuit of claim 4, wherein a source / drain region of the electronic device is formed in the diffusion region. The integrated circuit of claim 1, wherein the single crystal region contacted by the buried interconnect comprises at least one body of the electronic device. The integrated circuit of claim 1, wherein at least one conductive line formed over the substrate is conductively coupled to the buried interconnect. 8. The integrated circuit of claim 7, wherein the at least one conductive line is conductively coupled to the buried interconnect. 9. The integrated circuit of claim 8 wherein the conductive line is in contact with a top surface of the buried interconnect. The integrated circuit of claim 1 wherein the buried interconnect has a sidewall in contact with a trench isolation. The integrated circuit of claim 1, wherein the deposited conductor comprises doped polysilicon. The integrated circuit of claim 1, wherein the deposited conductor comprises a metal. The integrated circuit of claim 1, wherein the deposited conductor comprises a metal silicide. The integrated circuit of claim 11, further comprising a liner formed in the trench in advance of the deposited conductor. The integrated circuit of claim 1, wherein the single crystal region is separated from the substrate by a buried oxide layer. A method of forming an embedded interconnect of an integrated circuit according to any one of claims 1-15. Forming a trench isolation region in the substrate, Forming a trench in a single crystal region of the substrate adjacent to the isolation region, the trench having a bottom separated from the single crystal region and a sidewall adjacent to the trench isolation region; Depositing a conductor in the trench that contacts a single crystal region on at least one sidewall of the trench; Forming a contact in said deposited conductor from above. 17. The method of claim 16 wherein the contact with the deposited conductor is through an opening etched in a separation layer deposited on the deposited conductor. 17. The method of claim 16, further comprising depositing a first conductive line on the substrate, And wherein the conductive line is conductively coupled to the deposited conductor by contact with the deposited conductor. 19. The method of claim 18, further comprising depositing a second conductive line in contact with the first conductive line, And wherein the first conductive line and the second conductive line are conductively coupled to the deposited conductor by contact with the deposited conductor. 17. The method of claim 16 wherein the bottom of the trench is separated by deposited oxide. 17. The method of claim 16 further comprising depositing a liner in the trench prior to depositing the conductor.