CN1628387A - Enhanced structure and method for buried local interconnects - Google Patents

Enhanced structure and method for buried local interconnects Download PDF

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Publication number
CN1628387A
CN1628387A CNA028289897A CN02828989A CN1628387A CN 1628387 A CN1628387 A CN 1628387A CN A028289897 A CNA028289897 A CN A028289897A CN 02828989 A CN02828989 A CN 02828989A CN 1628387 A CN1628387 A CN 1628387A
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conductor
integrated circuit
deposited
contact
buried interconnects
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拉马钱德拉·迪瓦卡鲁尼
奥利格·格卢申科夫
杰克·A·曼德尔曼
卡尔·J·拉登斯
罗伯特·C·旺
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A structure and method is disclosed for forming a buried interconnect of an integrated circuit in a simple crystal semiconductor layer of a substrate. The buried interconnect is formed of a deposited conductor and has one or more verticalsidewalls which contact a single crystal region of ane electronic device formed in the single crystal semiconductor layer.

Description

Be used to bury the enhancing structure and the method for local interlinkage
Technical field
(front end of line FEOL) handles, and relates more specifically to the local interlinkage of burying with transistor level formation to the present invention relates to semiconductor front end of line.
Background technology
In microelectronics industry, have especially intensive, at a high speed and also make the lasting needs of microcircuit miniaturization for memory cell and support circuit.In order to realize the dimensional requirement of maximal density, speed and hope, carry out different solutions.
In semiconductor technology, in order to help to satisfy the needs of high speed integrated circuit, use more widely specialized technology such as silicon-on-insulator in the past (Silicon-on-Insulator, SOI).In the SOI technology, the semiconductor material layer of relative thin, normally silicon (Si), generally overlapping buried oxide (buriedoxide, insulation material layer BOX) of being called.The semiconductor material layer of this relative thin has normally wherein formed the zone of active device in the SOI device.
Integrated circuit manufactures has a large amount of electronic semiconductor components, and as resistor, transistor, diode and capacitor, they are manufactured on the Semiconductor substrate together with the technology of combination.But substrate refers to comprise the one or more semiconductor layers or the structure of the active or operation part of semiconductor device.An importance making integrated circuit is to come electric interconnection active device wherein by interconnection structure.
Interconnection structure generally comprises the electric conducting material district that forms between the semiconductor device that electrically contacts being in.Interconnection is as the conduit that is used for delivered current between semiconductor device.The particular type of interconnection structure is that the those skilled in the art is known, and can comprise M0, M1 wire level local interlinkage, bury contact, through hole, post, surface band and buried strap, only give some instances.Diode sometimes also can be as the interconnection between the semiconductor device.Can in Semiconductor substrate, form diode by the active area that connects different carrier types.
Often a kind of interconnection structure that uses is to bury contact.Burying contact can be the multi-crystal silicon area of making direct contact between interconnection structure and active area, eliminates the needs that metal connects.Bury in the contact in formation, open window in the thin gate oxide on the active area that interconnection structure will be electrically connected.After this, the deposit polysilicon directly contacts with active area in the opening, but by the silicon isolation under the gate oxide in other parts of Semiconductor substrate and field oxide and the active area.By being preset in diffuse dopants in the polysilicon in active area, the formation ohmic contact at the interface between polysilicon and active area.Diffuse dopants in active area, effectively, in conjunction with polysilicon and active area.The deposit insulating film layer is buried contact with covering then.Bury contact and so called, form the active area of burying contact, do not bury contact and can not be electrically connected to because metal level can be crossed over.
In some cases, in order to allow to increase the current densities that comprises, a plurality of metal interconnecting layers are stacked in top of each other.Generally, each continuous metal level has the component density that reduces.This classification in the density is because the mask overlap mistake of each additional interconnect accumulation.For example, if active area (active area, AA) and need between second metal level (M2) contact, have to so between AA and the first metal layer (M1), produce through hole, produce then second through hole with the interconnection M1 to M2.The total overlapping tolerance of AA to M2 is AA to M1 contacts tolerance with M1 to M2 a summation.Therefore, be restricted by the ability that increases interconnection layer and increase current densities.
In many cases, providing enough manufacturing tolerances when satisfying size, speed and density requirements may be a challenge task.Need a kind of new structure, but when keeping other manufacturing tolerance of processing stage, allow to increase current densities.
Summary of the invention
According to an aspect of the present invention, provide a kind of structure and method, be used for forming the buried interconnects of integrated circuit at the single-crystal semiconductor layer of substrate.Buried interconnects is formed by the conductor of deposit, and has one or more vertical sidewalls in the monocrystalline tagma of the electronic device that contact forms in single-crystal semiconductor layer.
According to a further aspect in the invention, provide a kind of method that forms buried interconnects, this method comprises: form channel separating zone in substrate; Form groove in the single-crystal region of the substrate of adjacency isolated area, wherein groove has the bottom that isolates with single-crystal region, and the sidewall of adjacent trench isolated area; Conductor deposited in groove then, this conductor contacts single-crystal region at least one sidewall of groove; And the contact that is formed up to conductor deposited from the top.
Description of drawings
Fig. 1,9 and 10 buried interconnect structure that illustrate according to selectivity embodiment of the present invention;
Fig. 2 to 8 illustrates the stage of making buried interconnect structure according to embodiments of the invention.
Embodiment
Fig. 1 illustrates the buried interconnect structure according to silicon-on-insulator of the present invention (SOI) embodiment.As shown in Figure 1, in the single-crystal semiconductor layer (soi layer 12) of SOI substrate, form buried interconnects 10 with the buried oxide layer (BOX 14) on support substrates 16.Buried interconnects 10 has common vertical orientation (hereinafter referred to as " vertically ") sidewall 18, the single-crystal region 12 of sidewall 18 contact electronic devices 20, and for example electronic device 20 can be formed in transistor, diode, capacitor or the resistor in the soi layer 12.
When electronic device 20 was isolated-gate field effect transistor (IGFET) (IGFET), the vertical sidewall 18 of buried interconnects 10 can directly contact tagma or diffusion region (for example, the source/leakage diffusion region) of the electronic device 20 that is formed in the soi layer 12.When electronic device 20 was diode or depletion capacitor, the vertical sidewall 18 of buried interconnects 10 can contact the diffusion region of this device.
Buried interconnects 10 is extended (the inside and outside direction of the page in Fig. 1 is extended) usually on the direction that is roughly parallel to substrate 16.In this way, buried interconnects 10 is by other single-crystal region 12 of vicinity of substrate, and it can contact one or more single-crystal region 12 of other electronic devices by not segregate vertical sidewall 18 or other sidewalls.Isolated area 28 (for example, trench isolations) (it is at the partial-length at least that extends buried interconnects 10 on inside with the outside direction of the page) along sidewall 30 with buried interconnects 10 and other electronic devices isolation that remove expecting to contact.In expectation and other electronic device position contacting, can contact along sidewall 30 parts that do not have isolated area 28.
Buried interconnects 10 is by the conductor of deposit such as polysilicon, metal silicide (for example, WSi x, CoSi x, TiSi x, follow follow-up metal deposit and autoregistration silicification reaction after the deposit polysilicon) and even can be depositing metal, it is tungsten (W) or other refractory metals or titanium (Ti) preferably, niobium (Nb), and zirconium (Zr), tantalum (Ta), molybdenum (Mo), or its layer constitutes.Buried interconnects can be used lining 32 liners, and lining 32 comprises nitride or the nitride of metalloid, for example tungsten nitride or titanium nitride or the tantalum nitride silicon (TaSiN) of the conductor metal of deposit.Perhaps, when the conductor of deposit is polysilicon, can use the extremely thin layer (below 7 dusts) of silicon nitride especially, describe more completely as following.
Buried interconnects 10 is preferably conducted electricity and is couple to the conductor wire 22 that is formed on the substrate, conductor wire 22 is polysilicon conductors, for example, it can form MOS device 24, and (it is " MOS ", promptly, insulated gate, field-effect transistor or mos capacitance device) grid conductor or " polycrystalline conductor (polyconductor) ", above the gate medium 26 of grid conductor on being formed at soi layer 12.Polycrystalline conductor 22 has been shown among Fig. 1 has connected the source/drain region 20 of MOS device (for example MOSFET 24) to other electronic device (for example other MOSFET) as the grid conductor.As in a large amount of latchs, trigger, driver and even static RAM (SRAM), MOSFET can connect in one way and wherein used cross-coupled CMOSFET right.
The selectivity scheme, polycrystalline conductor 22 can be patterned, only to extend on STI 28 and oxide 46, as just the interface to buried interconnects 10.As another kind of selectivity scheme, polycrystalline conductor 22 can extend on the gate medium of MOSFET device 20, and buried interconnects 10 is by the tagma of sidewall 18 conduction contact MOSFET devices 20.In the case, the tagma of MOSFET 20 will be bound in the voltage identical with grid conductor 22.This grid and body interconnection allow MOSFET 20 to be operating as the variable threshold voltage device, and wherein threshold voltage reduces with the increase of grid conductor voltage.
Figure 1A is the top-down diagrammatic sketch of example semiconductor device layout layer formed according to the present invention, as to have buried interconnects.In this layout, zone 110 and 210 expression buried interconnects, and the active area of zone 120 and 220 expression substrates.In the example that illustrates, preferably in active area 120, form N raceway groove IGFET (NFET), preferably in active area 220, form P raceway groove (PFET).The polycrystalline conductor 122,222 that intersects shown on part active area 120 and 220 and 322 is as wherein NFET and the grid conductor of PFET.First buried interconnects 110 has one or more sidewalls 118,119 in source/drain region of NFET in single-crystal region of touching (active area 120).Buried interconnects 110 also has the sidewall 218,219 in source/drain region of another device PFET in single-crystal region of touching (active area 220).Therefore, should be appreciated that single buried interconnects has one or more sidewalls of one or more single-crystal region of a plurality of electronic devices of contact (for example, NFET and PFET).Between polycrystalline conductor 222 and buried interconnects 110, form and bury contact 148, with the conductive interconnection of foundation with polycrystalline conductor 222.
Similarly, second buried interconnects 210 has one or more sidewalls 318,319 in the source/drain region of the electronic device NFET in the contact single-crystal region (active area 120).Buried interconnects 210 also has another device PFET's in single-crystal region of touching (active area 220)/sidewall 418,419 in drain region.Between polycrystalline conductor 122 and buried interconnects 210, form and bury contact 248, with the conductive interconnection of foundation with polycrystalline conductor 122.
Fig. 2 to 7 illustrates the stage of making buried interconnects 10 shown in Figure 1 in SOI process implementing example.As shown in Figure 2, in the soi layer 12 of substrate, form shallow channel isolation area (STI 28) with the buried oxide layer (BOX 14) on support substrates 16.STI28 extends to BOX layer 14, so that be isolated in the electronic device that forms in the soi layer 12 on its each side.Soi layer 12 in the position that pad nitride 34 covers except STI 28.
Next, as shown in Figure 3, deposit and composition photoresist, forming mask 36, preferred user tropism, reactive ion etching (RIE) etching opening 35, its at least one side in abutting connection with STI 28 and at least one other side in abutting connection with soi layer 12.This etching can be by timing, or preferably stops when reaching support substrates 16.Remove mask 36 then.But this moment passivation soi layer 12 expose sidewall 13, removing the surface damage of monocrystalline soi layer, as by timing sidewall oxidation and oxide removal subsequently.
Then, as shown in Figure 4, deposited oxide preferably by high density plasma deposition, forms separator 38 and forms oxide 40 from the teeth outwards with the bottom at groove.Remove the oxide (for example, passing through isotropic etching) that adheres to opening 35 sidewalls 13 this moment, comprises any oxide that comes from above-mentioned optional passivation technology.Then, as shown in Figure 5, preferably by deposit lining 32 at first after the liner opening, conductor deposited 44 is with filling opening 35.Can deposition of various materials as conductor 44, this material is a polysilicon, comprises the metal of tungsten (W), niobium (Nb), zirconium (Zr), tantalum (Ta), molybdenum (Mo), and the silicide of this metal and nitride, or its layer.When forming conductor 44, preferably promote material such as the tungsten nitride or the titanium nitride formation lining 32 of adhesion by deposit by deposit refractory metal such as tungsten.
When the deposit polysilicon when forming conductor 44, preferred high doped when deposit, but another kind of scheme can be mixed in original place after the deposit.When forming conductor 44, for adhesiveness can not need lining 32 by polysilicon.But, for other reasons, still preferably utilize electric conducting material or even the barrier layer of the very thin layer of silicon nitride come liner opening 35.The very thin layer of silicon nitride is 7 or littler known the conduction for example, because pass through the very quantum tunneling of thin layer.This barrier layer will be used for hindering dopant and be diffused into adjacent SOI district 12 from polysilicon, and/or forbid the crystallization again of polysilicon at the interface between conductor 44 and SOI district 12.Should avoid crystallization again, because it can cause the crystal defect in the SOI district 12 potentially, the final performance that worsens the electronic device that wherein forms.
After conductor deposited 44, by technology as nitride chemico-mechanical polishing selectively (CMP) being come the horizontal plane of smooth substrate to pad nitride 34, remove the conductor of deposit and the oxide of deposit with top surface, produce structure as shown in Figure 5 from substrate.Then preferably by the directivity etching as to oxide and nitride reactive ion etching selectively, make conductor 44 and lining 32 depressions, produce structure as shown in Figure 6.
Then, as shown in Figure 7, above conductor 44, form top oxide layer 46.This preferably realizes by carrying out following steps: by the high density plasma process deposited oxide, smooth then oxide 46 is (as by to nitride CMP selectively) to the plane of pad nitride 34, then the remaining pad nitride 34 of 12 removings from SOI district.
Next, refer again to complete structure shown in Figure 1, carry out further and handle, bury contact 48 to form by polycrystalline conductor 22.Polycrystalline conductor 22 can be the grid conductor that (but not necessarily) is arranged in one or more electronic devices in SOI district 12.Preferably carry out necessary arbitrarily ion be injected into device 24, to device 20 optionally ion inject and form gate medium 26 by oxidation or deposit after carry out this operation.Deposit and composition photoresist then are to be defined for the window of etching contact openings in the top oxide 46 of deposit.After this, stripping photoresist, and the polysilicon of deposit and composition high doped contact 48 with the polycrystalline conductor 22 shown in forming with burying.
Fig. 8 and 9 illustrates the stage of the selectivity operation that is used to finish buried interconnects 10.Fig. 9 illustrates the complete structure that is produced by the selectivity operation, wherein makes from second conductor 52 that contacts with polycrystalline conductor 22 and contacts 50 to burying of buried interconnects 10.The place that structure shown in Figure 9 is different from structure shown in Figure 1 also is, buried interconnects 10 has the sidewall 18 in the tagma of the electronic device 20A that contact forms in soi layer 12 since the soi layer 12 that is touched is positioned at below the gate medium 26 and polycrystalline conductor 22 there as the grid conductor.Notice that the tagma by buried interconnects 10 contact electronic device 20A only is a possible embodiment, use in this selectivity operation that second conductor 52 contacts with polycrystalline conductor 22 necessity anything but concentrating on.Second conductor 52 can be formed by the material that is fit to arbitrarily, as polysilicon, metal silicide or the metal of high doped itself.
In this selectivity operation, use and above-mentionedly proceed to handle referring to figs. 2 to 7 same way as and by the formation of gate medium.Then, deposit polycrystalline conductor layer 22, as shown in Figure 8.It is that with reference to the aforesaid difference of figure 1 opening that passes oxide layer 46 in etching is buried with formation before the contact 48, deposit polycrystalline conductor layer 22 on gate medium 26.For fear of gate medium 26 be used for may interact between the photoresist of composition contact openings, this processing sequence can be desirable.
Refer again to Fig. 9, coating and composition photoresist will be etched with the position in the polycrystalline conductor layer 22 that forms contact openings with qualification then.Deposit second conductor layer 52 on polycrystalline conductor layer 22 comprises entering contact openings then, buries contact 50 with formation.Can apply then and the composition photoresist, and in a combination etching one etching second conductor layer 52 and polycrystalline conductor layer 22, as by vectorial reaction ion etching, to limit second conductor 52 and polycrystalline conductor 22.
Figure 10 illustrates the completed buried interconnect structure 10 that forms according to another embodiment of the present invention, is formed in the case in the bulk semiconductor substrate relative with the SOI substrate.Except that will describing now, utilize with proceeding and handle with reference to the same as mentioned above method of embodiment of figure 1-7 or Fig. 2-9.With reference to figure 4, owing in build substrate embodiment, do not have buried oxide layer, oxide 38 may need to be deposited to the higher level of opening 35, make buried interconnects 10 contact the device layer 20B of electronic devices, as source/leakage diffusion, rather than build substrate 17 so that avoid undesirable leakage current from the source/leakage diffusion region 20B is to build substrate 17.
Although described the present invention with reference to its certain preferred embodiment, the those skilled in the art will be understood that, can carry out many changes and improvements under the condition that does not only break away from by the true scope of the present invention of claims restriction and spirit.
Industrial applicibility
The present invention can be applicable to integrated electronic circuit and manufacturing thereof.

Claims (21)

1, a kind of integrated circuit is included in the buried interconnects that forms in the single-crystal semiconductor layer of substrate, and described buried interconnects is formed by conductor deposited and has one or more vertical sidewalls of single-crystal region that contact is formed at the electronic device in the described single-crystal semiconductor layer.
2, according to the integrated circuit (IC)-components of claim 1, wherein via described one or more vertical sidewalls by described buried interconnects, a plurality of electronic devices are touched at its single-crystal region place.
3, according to the integrated circuit (IC)-components of claim 1, wherein said buried interconnects have with face except that the described vertical sidewall that contacts described single-crystal region on contacted at least one sidewall of isolated area.
4,, wherein comprise at least one diffusion region of at least one described electronic device by the described single-crystal region of described buried interconnects contact according to the integrated circuit (IC)-components of claim 1.
5,, wherein in described diffusion region, form the source/drain region of described electronic device according to the integrated circuit (IC)-components of claim 4.
6,, wherein comprise the tagma of at least one described electronic device by the described single-crystal region of described buried interconnects contact according to the integrated circuit (IC)-components of claim 1.
7, according to the integrated circuit (IC)-components of claim 1, at least one conductor wire that wherein is formed on the described substrate is couple to described buried interconnects by conduction.
8, according to the integrated circuit of claim 7, wherein said at least one conductor wire is couple to described buried interconnects conductively.
9, integrated circuit according to Claim 8, wherein said conductor wire contacts the top surface of described buried interconnects.
10, according to the integrated circuit of claim 1, wherein said buried interconnects has the sidewall in abutting connection with a trench isolations.
11, according to the integrated circuit of claim 1, wherein said conductor deposited comprises doped polycrystalline silicon.
12, according to the integrated circuit of claim 1, wherein said conductor deposited comprises metal.
13, according to the integrated circuit of claim 1, wherein said conductor deposited comprises metal silicide.
14,, in described groove, form lining before also being included in described conductor deposited according to claim 11, any one integrated circuit of 12 or 13.
15, according to the integrated circuit of claim 1, wherein said single-crystal region is by a buried oxide layer and described substrate isolation.
16, a kind of formation comprises according to the method for the buried interconnects of any one integrated circuit of claim 1 to 15:
In substrate, form channel separating zone;
In the single-crystal region of the described substrate of described isolated area, forming groove, the bottom that described groove has and described single-crystal region is isolated and in abutting connection with the sidewall of described channel separating zone;
Conductor deposited in described groove contacts described single-crystal region at the above conductor of at least one sidewall of described groove; And
Be formed into the contact of described conductor deposited from the top.
17, according to the method for claim 16, wherein be fabricated onto the described contact of described conductor deposited by the opening of etching in the separator on being deposited to described conductor deposited.
18, according to the method for claim 16, also be included in deposit first conductor wire on the described substrate, wherein the described contact to described conductor deposited is couple to described conductor deposited with described conductor wire conduction.
19, according to the method for claim 18, also comprise second conductor wire that deposit contacts with described first conductor wire, wherein the described contact to described conductor deposited is couple to described conductor deposited with described first conductor wire and described second conductor wire conduction.
20, according to the method for claim 16, the described bottom of wherein said groove is deposited oxide-isolated.
21,, also be included in the described conductor of deposit deposit lining in described groove before according to the method for claim 16.
CNA028289897A 2002-06-14 2002-06-14 Enhanced structure and method for buried local interconnects Pending CN1628387A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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CN104867864A (en) * 2015-03-27 2015-08-26 上海新储集成电路有限公司 Method for realizing local interconnection

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8897470B2 (en) * 2009-07-31 2014-11-25 Macronix International Co., Ltd. Method of fabricating integrated semiconductor device with MOS, NPN BJT, LDMOS, pre-amplifier and MEMS unit
US9224712B2 (en) 2014-02-11 2015-12-29 International Business Machines Corporation 3D bond and assembly process for severely bowed interposer die
EP3139405B1 (en) 2015-09-01 2021-08-11 IMEC vzw Buried interconnect for semicondutor circuits
CN108538839B (en) * 2017-03-01 2019-08-23 联华电子股份有限公司 Semiconductor structure, for semiconductor structure of memory component and preparation method thereof
US11101217B2 (en) 2019-06-27 2021-08-24 International Business Machines Corporation Buried power rail for transistor devices

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63138764A (en) * 1986-11-29 1988-06-10 Tdk Corp Semiconductor integrated circuit and manufacture thereof
KR960016229B1 (en) * 1993-09-13 1996-12-07 삼성전자 주식회사 Semiconductor device contact structure and manufacturing method thereof
US6215158B1 (en) * 1998-09-10 2001-04-10 Lucent Technologies Inc. Device and method for forming semiconductor interconnections in an integrated circuit substrate
US6143595A (en) * 1999-07-07 2000-11-07 United Microelectronics Corp. Method for forming buried contact
US6407444B1 (en) * 2000-07-19 2002-06-18 Hughes Electronics Corp. Single event upset hardening of a semiconductor device using a buried electrode

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103563086A (en) * 2011-06-27 2014-02-05 国际商业机器公司 Low-profile local interconnect and method of making the same
CN103563086B (en) * 2011-06-27 2016-09-14 国际商业机器公司 Low profile local interlinkage and manufacture method thereof
CN104867864A (en) * 2015-03-27 2015-08-26 上海新储集成电路有限公司 Method for realizing local interconnection
CN104867864B (en) * 2015-03-27 2018-08-28 上海新储集成电路有限公司 A method of realizing local interlinkage

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AU2002306174A1 (en) 2003-12-31

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