KR100290486B1 - Method of manufacturing transistor of semiconductor device - Google Patents

Method of manufacturing transistor of semiconductor device Download PDF

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Publication number
KR100290486B1
KR100290486B1 KR1019980061374A KR19980061374A KR100290486B1 KR 100290486 B1 KR100290486 B1 KR 100290486B1 KR 1019980061374 A KR1019980061374 A KR 1019980061374A KR 19980061374 A KR19980061374 A KR 19980061374A KR 100290486 B1 KR100290486 B1 KR 100290486B1
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South Korea
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field oxide
oxide film
film
forming
silicon substrate
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KR1019980061374A
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Korean (ko)
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KR20000044871A (en
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박승희
이희열
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박종섭
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

본 발명은 반도체 소자의 트랜지스터 제조 방법에 관한 것으로, 소자분리 공정시 채널영역과 소자 분리 영역의 사이에 추가적으로 필드 산화막이 더 형성되도록 하여 트랜지스터의 소오스와 실리콘 기판의 직접적인 접속이 이루어지도록 하므로써 공정의 단순화 및 소자의 집적도 향상을 이룰 수 있는 반도체 소자의 트랜지스터 제조 방법이 개시된다.The present invention relates to a method for fabricating a transistor of a semiconductor device, which further simplifies the process by allowing an additional field oxide layer to be further formed between the channel region and the device isolation region in the device isolation process to allow direct connection between the source of the transistor and the silicon substrate. And a transistor manufacturing method of a semiconductor device capable of improving the degree of integration of the device.

Description

반도체 소자의 트랜지스터 제조 방법Method of manufacturing transistor of semiconductor device

본 발명은 반도체 소자의 트랜지스터 제조 방법에 관한 것으로, 특히 소오스로 이용되는 접합영역과 실리콘 기판의 접속이 금속배선을 통해 이루어지지 않고 직접적으로 이루어질 수 있도록 하므로써 소자의 집적도가 향상될 수 있는 반도체 소자의 트랜지스터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor of a semiconductor device. In particular, the connection between a junction region used as a source and a silicon substrate can be directly made through a metal wiring, and thus the degree of integration of the device can be improved. A method of manufacturing a transistor.

일반적으로 반도체 소자의 트랜지스터는 게이트 전극과, 소오스 및 드레인으로 이용되는 접합영역으로 이루어지며, 상기 게이트 전극은 게이트 산화막에 의해 상기 실리콘 기판과 전기적으로 분리되도록 구성된다. 또한, 메모리 소자의 주변회로 지역에 형성되는 트랜지스터는 상기 각 구성요소들의 형성이 완료되면 도 1에 도시된 바와 같이 상기 소오스(S) 또는 드레인(D)으로 이용되는 접합영역과 상기 실리콘 기판(Sub)을 서로 연결시키는데, 종래에는 외부에서 금속배선을 이용하여 연결하였다. 따라서 종래의 트랜지스터 제조 방법을 이용하면 칩에서 트랜지스터가 차지하는 면적이 커지게 되고, 금속배선 형성시 생성되는 결함에 의한 불량이 발생되며, 금속배선이 가지는 자체 저항으로 인한 회로의 오동작이 유발된다.In general, a transistor of a semiconductor device includes a gate electrode and a junction region used as a source and a drain, and the gate electrode is configured to be electrically separated from the silicon substrate by a gate oxide film. In addition, the transistor formed in the peripheral circuit region of the memory device has a junction region and the silicon substrate (Sub) used as the source (S) or drain (D) as shown in FIG. ) Are connected to each other, and in the related art, a metal wire is connected from the outside. Therefore, using a conventional transistor manufacturing method increases the area occupied by transistors in a chip, defects caused by defects generated when metal wirings are formed, and malfunctions of circuits due to self-resistance of metal wirings.

따라서 본 발명은 소자분리 공정시 채널영역과 소자 분리 영역의 사이에 추가적으로 필드 산화막을 더 형성하여 트랜지스터의 소오스와 실리콘 기판의 직접적인 접속이 이루어질 수 있도록 하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 트랜지스터 제조 방법을 제공하는 데 그 목적이 있다.Therefore, in the device isolation process, the field oxide layer may be additionally formed between the channel region and the device isolation region so that the source of the transistor and the silicon substrate may be directly connected to each other. The purpose is to provide a manufacturing method.

상기한 목적을 달성하기 위한 본 발명은 소자분리 영역에 제 1 필드 산화막이 각각 형성되며, 채널영역의 일측부와 하나의 상기 제 1 필드 산화막 사이에 제 2 필드 산화막이 형성된 실리콘 기판상에 게이트 산화막 및 폴리실리콘층을 순차적으로 형성하는 단계와, 상기 단계로부터 상기 폴리실리콘층 및 게이트 산화막을 순차적으로 패터닝하여 상기 채널영역 상부에 게이트 전극이 형성되도록 하는 단계와, 상기 단계로부터 전체 상부면에 감광막을 형성한 후 상기 제 1 필드 산화막의 일부와 상기 제 2 필드 산화막이 노출되도록 상기 감광막을 패터닝하는 단계와, 상기 단계로부터 패터닝된 상기 감광막을 마스크로 이용한 식각 공정으로 노출된 부분의 상기 제 1 및 제 2 필드 산화막을 식각한 후 상기 감광막을 제거하는 단계와, 상기 단계로부터 노출된 상기 실리콘 기판에 불순물 이온을 주입하여 소오스 또는 드레인으로 이용될 접합영역을 각각 형성하는 단계와, 상기 단계로부터 전체 상부면에 절연막을 형성하고 상기 접합영역의 소정 부분이 노출되도록 상기 절연막을 패터닝하여 콘택홀을 각각 형성하는 단계와, 상기 단계로부터 상기 콘택홀내에 금속을 매립시켜 금속 플러그를 형성하는 단계로 이루어지는 것을 특징으로 한다.According to the present invention for achieving the above object, a first field oxide film is formed in each device isolation region, and a gate oxide film is formed on a silicon substrate having a second field oxide film formed between one side of the channel region and one of the first field oxide films. And sequentially forming a polysilicon layer, sequentially patterning the polysilicon layer and the gate oxide film from the step so that a gate electrode is formed over the channel region, and forming a photoresist film on the entire upper surface from the step. Patterning the photoresist film so that a portion of the first field oxide film and the second field oxide film are exposed after formation, and the first and second portions of the exposed part by an etching process using the photosensitive film patterned from the step as a mask. Removing the photoresist after etching the two-field oxide film, and exposing from the step Implanting impurity ions into the silicon substrate to form a junction region to be used as a source or a drain, and forming an insulating film on the entire upper surface from the step and patterning the insulating film so that a predetermined portion of the junction region is exposed. And forming holes, respectively, and forming metal plugs by embedding metal in the contact holes.

도 1은 종래 반도체 소자의 트랜지스터를 설명하기 위한 회로도.1 is a circuit diagram for explaining a transistor of a conventional semiconductor device.

도 2 내지 7은 본 발명에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 소자의 단면도.2 to 7 are cross-sectional views of a device for explaining a transistor manufacturing method of a semiconductor device according to the present invention.

도 8은 본 발명에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 레이-아웃도.8 is a layout view illustrating a method for manufacturing a transistor of a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

1: 실리콘 기판 2 및 2A: 제 1 및 제 2 필드 산화막1: Silicon Substrate 2 and 2A: First and Second Field Oxide Films

3: 게이트 산화막 4: 게이트 전극3: gate oxide film 4: gate electrode

5: 감광막 6A 및 6B: 접합영역5: photosensitive films 6A and 6B: junction region

7: 절연막 8A 및 8B: 콘택홀7: insulating film 8A and 8B: contact hole

9: 금속 플러그9: metal plug

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 2 내지 6은 본 발명에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 소자의 단면도로서, 도 7을 참조하여 설명하면 다음과 같다.2 to 6 are cross-sectional views of devices for describing a method of manufacturing a transistor of a semiconductor device according to the present invention.

도 2는 소자분리 영역에 제 1 필드 산화막(2)이 각각 형성된 실리콘 기판(1)상에 게이트 산화막(3) 및 폴리실리콘층(4)을 순차적으로 형성한 후 상기 폴리실리콘층(4) 및 게이트 산화막(3)을 순차적으로 패터닝하여 채널영역의 상부에 게이트 전극을 형성한 상태의 단면도인데, 상기 제 1 필드 산화막(2) 형성 공정시 상기 게이트 전극 즉, 상기 트랜지스터의 채널영역 일측부와 상기 제 1 필드 산화막(2)의 사이에 다른 하나의 제 2 필드 산화막(2A)이 형성되도록 한다.FIG. 2 sequentially forms a gate oxide film 3 and a polysilicon layer 4 on a silicon substrate 1 on which a first field oxide film 2 is formed in an isolation region, and then the polysilicon layer 4 and A cross-sectional view of a gate electrode formed on the channel region by sequentially patterning the gate oxide layer 3. In the process of forming the first field oxide layer 2, the gate electrode, that is, one side of the channel region of the transistor and the gate electrode is formed. Another second field oxide film 2A is formed between the first field oxide film 2.

도 3은 전체 상부면에 감광막(5)을 형성한 후 상기 제 1 필드 산화막(2)의 일부와 상기 제 2 필드 산화막(2A)이 노출되도록 상기 감광막(5)을 패터닝한 상태의 단면도이다.3 is a cross-sectional view of the photosensitive film 5 in a state in which a portion of the first field oxide film 2 and the second field oxide film 2A are patterned after the photosensitive film 5 is formed on the entire upper surface.

도 4는 패터닝된 상기 감광막(5)을 마스크로 이용한 식각 공정으로 노출된 부분의 상기 제 1 및 제 2 필드 산화막(2 및 2A)을 식각한 후 상기 감광막(5)을 제거한 상태의 단면도로서, 상기 제 1 필드 산화막(2)과 제 2 산화막(2A)이 제거된 부분의 계면은 철(凸) 형태를 이룬다.FIG. 4 is a cross-sectional view of the photosensitive film 5 after the first and second field oxide films 2 and 2A of the exposed portion are etched by an etching process using the patterned photosensitive film 5 as a mask. The interface between the portion where the first field oxide film 2 and the second oxide film 2A are removed is in the form of iron.

도 5는 노출된 상기 실리콘 기판(1)에 불순물 이온을 주입하여 소오스 또는 드레인으로 이용될 접합영역(6A 및 6B)을 각각 형성한 상태의 단면도이다.FIG. 5 is a cross-sectional view of a state in which impurity ions are implanted into the exposed silicon substrate 1 to form junction regions 6A and 6B to be used as sources or drains, respectively.

도 6은 전체 상부면에 절연막(7)을 형성하고 상기 접합영역(6A 및 6B)의 소정 부분이 노출되도록 상기 절연막(7)을 패터닝하여 콘택홀(8A 및 8B)을 각각 형성한 상태의 단면도로서, 이때 상기 접합영역(6B)의 철(凸) 부분이 노출되도록 상기 콘택홀(8B)을 형성한다. 여기서 도 6은 도 8의 X1 - X2 부분을 절취한 상태이다.FIG. 6 is a cross-sectional view of the insulating film 7 formed on the entire upper surface and the contact holes 8A and 8B formed by patterning the insulating film 7 so that predetermined portions of the junction regions 6A and 6B are exposed. In this case, the contact hole 8B is formed to expose the iron portion of the junction region 6B. 6 is a state in which the X1-X2 part of FIG. 8 is cut out.

도 7은 상기 콘택홀(8A 및 8B)내에 금속을 매립시켜 금속 플러그(9)를 형성한 상태의 단면도로서, 상기 콘택홀(8A 및 8B)을 형성하기 위한 식각 공정시 상기 콘택홀(8A 및 8B) 저면부의 노출된 상기 실리콘 기판(1)이 손실되기 때문에 상기 접합영역(6B)과 상기 실리콘 기판(1)이 상기 금속 플러그(9)에 의해 서로 접속된다.FIG. 7 is a cross-sectional view of a state in which a metal plug 9 is formed by embedding metal in the contact holes 8A and 8B. The contact holes 8A and 8A are formed during an etching process for forming the contact holes 8A and 8B. 8B) Since the exposed silicon substrate 1 in the bottom portion is lost, the junction region 6B and the silicon substrate 1 are connected to each other by the metal plug 9.

상술한 바와 같이 본 발명에 의하면 소자분리 공정시 채널영역과 소자분리 영역의 사이에 추가적으로 필드 산화막을 형성하여 트랜지스터의 소오스와 실리콘 기판의 직접적인 접속이 이루어질 수 있도록 하므로써 접합영역과 실리콘 기판을 접속시키기 위한 추가적인 금속배선 형성 공정이 실시되지 않는다. 그러므로 공정의 단순화가 이루어지며, 소자의 집적도가 향상될 수 있다. 또한, 금속배선의 사용에 따른 배선 저항의 증가가 방지되어 소자의 동작 속도가 향상될 수 있다.As described above, according to the present invention, a field oxide film is additionally formed between the channel region and the device isolation region in the device isolation process to directly connect the source of the transistor to the silicon substrate, thereby connecting the junction region and the silicon substrate. No additional metallization process is performed. Therefore, the process is simplified, and the degree of integration of the device can be improved. In addition, an increase in the wiring resistance due to the use of the metal wiring is prevented, so that the operation speed of the device can be improved.

Claims (2)

소자분리 영역에 제 1 필드 산화막이 각각 형성되며, 채널영역의 일측부와 하나의 상기 제 1 필드 산화막 사이에 제 2 필드 산화막이 형성된 실리콘 기판상에 게이트 산화막 및 폴리실리콘층을 순차적으로 형성하는 단계와,Sequentially forming a gate oxide film and a polysilicon layer on a silicon substrate having a first field oxide film formed in each device isolation region, and having a second field oxide film formed between one side of the channel region and one first field oxide film. Wow, 상기 단계로부터 상기 폴리실리콘층 및 게이트 산화막을 순차적으로 패터닝하여 상기 채널영역 상부에 게이트 전극이 형성되도록 하는 단계와,Sequentially patterning the polysilicon layer and the gate oxide layer from the step so that a gate electrode is formed on the channel region; 상기 단계로부터 전체 상부면에 감광막을 형성한 후 상기 제 1 필드 산화막의 일부와 상기 제 2 필드 산화막이 노출되도록 상기 감광막을 패터닝하는 단계와,Forming a photoresist film on the entire upper surface from the step, and then patterning the photoresist film to expose a portion of the first field oxide film and the second field oxide film; 상기 단계로부터 패터닝된 상기 감광막을 마스크로 이용한 식각 공정으로 노출된 부분의 상기 제 1 및 제 2 필드 산화막을 식각한 후 상기 감광막을 제거하는 단계와,Etching the first and second field oxide films of the exposed portions by an etching process using the photosensitive film patterned from the step as a mask, and then removing the photosensitive film; 상기 단계로부터 노출된 상기 실리콘 기판에 불순물 이온을 주입하여 소오스 또는 드레인으로 이용될 접합영역을 각각 형성하는 단계와,Implanting impurity ions into the silicon substrate exposed from the step to form junction regions to be used as sources or drains, respectively; 상기 단계로부터 전체 상부면에 절연막을 형성하고 상기 접합영역의 소정 부분이 노출되도록 상기 절연막을 패터닝하여 콘택홀을 각각 형성하는 단계와,Forming an insulating film on the entire upper surface from the step and patterning the insulating film so as to expose a predetermined portion of the junction region, and forming contact holes, respectively; 상기 단계로부터 상기 콘택홀내에 금속을 매립시켜 금속 플러그를 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조 방법.And embedding a metal in the contact hole from the step to form a metal plug. 제 1 항에 있어서,The method of claim 1, 상기 콘택홀을 형성하기 위한 식각 공정은 노출된 부분의 상기 실리콘 기판이 일부 손실되도록 과도 식각으로 진행하는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조 방법.The etching process for forming the contact hole is a transistor manufacturing method of a semiconductor device, characterized in that to proceed in the excessive etching so that the part of the silicon substrate of the exposed portion is lost.
KR1019980061374A 1998-12-30 1998-12-30 Method of manufacturing transistor of semiconductor device KR100290486B1 (en)

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