JPH07221196A - High load driver and semiconductor integrated device for the same - Google Patents

Abstract

PURPOSE:To manufacture the title semiconductor integrated device for high load driver by a method wherein an n channel is formed between the boundary of n<+> diffused region and the boundary of p tab while p channel is formed between the boundary of p<+> diffused region and the high concentration N layer. CONSTITUTION:The channel of this n channel LD-MOS transistor is formed between the boundary of n<+> diffused region 2 and the boundary of a p tab. Likewise, the channel of p channel LD-MOS transistor is formed between the boundary of p<+> diffused region 6 beneath a gate oxide film 8a and an NH layer 20. Since the channel lengths L1, L2 are decided respectively by the diffusion of p tab layer 10 and NH layer 20, ON resistance can be lowered by decreasing the channel lengths without reducing the distance between n<+> diffused regions 2 and 3 or the distance between p<+> diffusion regions 6 and 7. Through these procedures, sufficient current can be fed to any load without increasing the die size at all.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high load driver device for controlling and driving a high load such as a motor.

[0002]

2. Description of the Related Art FIG. 1 is a diagram showing a circuit configuration of a driver device for driving and controlling a rotation direction of a motor. In the figure,
The transistors Q1 to Q4 are MOS (Metal Oxide Semi)
conductor) structure transistor. A load driving power supply voltage V _DD is applied to the drain electrodes D of the transistors Q1 and Q3, and GND is applied to the source electrodes S of the transistors Q2 and Q4. The source electrode S of the transistor Q1 and the drain electrode D of the transistor Q2 are connected at a load driving output terminal A. Source electrode S of transistor Q3 and transistor Q
The drain electrode D of No. 4 is connected to the load driving output terminal B. A motor M as a load is connected between the load driving output terminals A and B.

In such a structure, when a drive control signal is supplied to the gate electrodes of the transistors Q1 and Q4 to turn on these Q1 and Q4, a current flows in the direction indicated by the broken line to rotationally drive the motor M. Also, when a drive control signal is supplied to the gate electrodes of the transistors Q2 and Q3, these Q2 and Q3 are turned on, and a current flows in the direction indicated by the alternate long and short dash line. To drive.

When forming such a circuit on a silicon substrate to form a semiconductor integrated device, the transistors Q1 and Q3 are p-channel transistors, and the transistors Q2 and Q4 are n-channel transistors.
MOS (Complementary Metal Oxide Semiconductor)
A structure method can be considered. FIG. 2 shows a conventional CMOS
It is a figure which shows the structural example of the semiconductor integrated device by a structure.

In the figure, an n ⁺ diffusion region 2 and an n ⁺ diffusion region 3 are formed near the surface of a p-type semiconductor substrate 1. A gate oxide film 4a is formed by adhering to the surface of each of the p-type semiconductor substrate 1, the n ⁺ diffusion regions 2 and 3. The polysilicon layer 4 is attached to the gate oxide film 4a.
b is formed. The source electrode S is connected to the p-type semiconductor substrate 1 and the n ⁺ diffusion region 2. Gate electrode G
Are connected to the polysilicon layer 4b. The drain electrode D is connected to the n ⁺ diffusion region 2. With this configuration, the n-channel transistor is formed on the p-type semiconductor substrate 1. Further, an n well 5 is formed near the surface of the p type semiconductor substrate 1. A p ⁺ diffusion region 6 and a p ⁺ diffusion region 7 are formed near the surface of the n well 5, respectively. Such n well 5, p ⁺ diffusion region 6
A gate oxide film 8a is formed by adhering to the surfaces of the gate oxide films 8 and 7. A polysilicon layer 8b is formed on the gate oxide film 8a. The source electrode S is connected to the n well 5 and the p ⁺ diffusion region 6. Gate electrode G
Are connected to the polysilicon layer 8b. The drain electrode D is connected to the p ⁺ diffusion region 7. With this configuration, a p-channel transistor is formed on the p-type semiconductor substrate 1, and finally a p-channel transistor and an n-channel transistor are present on the same p-type semiconductor substrate 1, which is a so-called CMOS structure. .

Here, each of the transistors having the above-described structure has a relatively high on-resistance when switching on, and therefore has a low current supply capability. Therefore, in order to drive a load such as a motor that requires a high drive current, it is necessary to reduce the on-resistance by reducing the channel length or increasing the channel width. That is, as shown in FIG. 2, the distance L between the p ⁺ diffusion regions 6 and 7 (n ⁺ diffusion regions 2 and 3) is made smaller, or the p ⁺ diffusion regions 6 and 7 (n ⁺ diffusion regions 2 and 3) are formed. ) Is increased.

However, it is difficult in terms of process technology to reduce the distance between the diffusion regions, and if the width of each diffusion region is increased in order to increase the channel width, the overall die size increases. To do. Therefore, an n-channel LD (lateral LD) capable of supplying a relatively high current without reducing the distance between the diffusion regions.
diffused) -MOS structure transistors are known.

FIG. 3 is a diagram showing the structure of such an n-channel LD-MOS transistor. In the figure, an n well 9 is formed near the surface of the p-type semiconductor substrate 1, and a p-tab 10 is formed in the n-well 9 as a p-type semiconductor diffusion layer. An n ⁺ diffusion region 2 is formed near the surface of the p-tab 10. n-well 9
An n ⁺ diffusion region 3 is formed near the surface of the. A gate oxide film 4a is formed by adhering to the surface of each of the n ⁺ diffusion region 2, the p tub 10, the n well 9 and the n ⁺ diffusion region 3. The polysilicon layer 4b is formed by the gate oxide film 4
It is formed by adhering to a. The source electrode S is connected to the p tub 10 and the n ⁺ diffusion region 2. The gate electrode G is connected to the polysilicon layer 4b. The drain electrode D is connected to the n ⁺ diffusion region 3.

According to this structure, the channel is formed between the boundary of the n ⁺ diffusion region 2 and the boundary of the p-tab 10 under the gate oxide film 4a. Therefore, the channel length L is p tab 1
Since it is determined by the diffusion of 0, the channel length can be reduced and the on-resistance can be reduced without reducing the distance between the diffusion regions. Here, such an n-channel LD-
Consider applying a MOS transistor to each of the transistors Q1-Q4 as shown in FIG.

In the configuration as shown in FIG. 1, for example, in order to drive a motor M by rotating a drive current in the direction of a broken line, the transistors Q1 and Q4 are turned on and the load driving output terminal A is set to V _DD. The voltage and output terminal B for driving the load must be set to GND. At this time, since the transistors Q1 and Q4 are n-channel type transistors, in order to maintain the ON state as described above, the gate electrode G thereof has a voltage sufficiently higher than V _DD (for example, V _DD A drive control signal of 2 to 3 times the voltage) must be applied. Therefore, such an n-channel LD
When the MOS transistor is applied to a high load drive driver as shown in FIG. 1, the voltage level of the drive control signal must be raised to 2 to 3 times the load drive power supply voltage by using, for example, a charge pump circuit. The problem arises that it must be done.

Therefore, it is conceivable that, among the transistors Q1 to Q4 of the high load driver, the transistors Q1 and Q3 are p-channel LD-MOS transistors as shown in FIG. In the figure, an n-tab 10 'is formed near the surface of the p-type semiconductor substrate 1,
A p ⁺ diffusion region 6 is formed near the surface of the n-tab 10 ′. Furthermore, a p ⁺ diffusion region 7 is formed in the vicinity of the surface of the p-type semiconductor substrate 1, and a dielectric layer 11 is provided to electrically isolate the p ⁺ diffusion region 7 and the p-type semiconductor substrate 1 from each other. Has been formed. The p-type semiconductor substrate 1, the n-tab 10 ′, the dielectric layer 11, the p ⁺ diffusion region 6
A gate oxide film 8a is formed by adhering to the surfaces of the gate oxide films 8 and 7. A polysilicon layer 8b is formed on the gate oxide film 8a. The source electrode S is n tab 1
0'and p ⁺ diffusion regions 6 are connected. The gate electrode G is connected to the polysilicon layer 8b. The drain electrode D is connected to the p ⁺ diffusion region 7.

As described above, in the structure shown in FIG. 4, dielectric layer 11 is formed to electrically separate p type semiconductor substrate 1 and p ⁺ diffusion region 7 from each other. (Otherwise, the drain electrode D is fixed to the voltage applied to the p-type semiconductor substrate 1 itself, that is, the GND level, and does not operate normally.) However, in the existing CMOS manufacturing process, the above-mentioned operation is performed. There is no manufacturing process for forming such a dielectric layer. Therefore, at this time, a new manufacturing process for forming such a dielectric layer has to be added, which causes a problem of high manufacturing cost.

[0013]

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and can be used for a high load driving driver device and can be manufactured by an existing CMOS manufacturing process. An object of the present invention is to provide a semiconductor integrated device for a driver and a high load driving driver thereof.

[0014]

According to another aspect of the present invention, there is provided a semiconductor device for a high load driving driver, wherein a first well region of a second conductivity type is formed near a surface of a semiconductor substrate of a first conductivity type, and the first well region is formed. First formed near the surface in the well region
A conductive type first diffusion layer, a second conductive type first diffusion region formed near the surface in the first diffusion layer, and a second conductive type formed near the surface in the first well region. Second diffusion region, the first diffusion region, the first diffusion layer, the first diffusion region,
A first gate oxide film deposited on the well region and the second diffusion region, a first polysilicon layer deposited on the first gate oxide film, the first diffusion layer and the A first source electrode formed by connecting a first diffusion region, a first gate electrode formed by connecting to the first polysilicon layer, and a first gate electrode formed by connecting to a second diffusion region. A second conductivity type transistor including a drain electrode, a second well region of the second conductivity type formed in the vicinity of the surface of the semiconductor substrate, and the second well formed in the vicinity of the surface in the second well region. Higher concentration than area 2
A conductive type second diffusion layer, a first conductive type third diffusion region formed near the surface in the second diffusion layer, and a first conductive type formed near the surface in the second well region. Of the fourth diffusion region and a second conductivity type of a lower concentration than the second well region formed between the second diffusion layer and the fourth diffusion region near the surface in the second well region. A third diffusion layer and a second diffusion layer formed by adhering to each of the third diffusion region, the second diffusion layer, the third diffusion layer, and the fourth diffusion region.
A gate oxide film, a second polysilicon layer formed by adhering to the second gate oxide film, a second source electrode formed by connecting the second diffusion layer and the third diffusion region,
A second gate electrode formed to be connected to the second polysilicon layer and a second gate electrode formed to be connected to the fourth diffusion region.
A first conductivity type transistor including a drain electrode.

Further, the high load driving driver device according to the present invention comprises first and third transistors of the first conductivity type, wherein a high voltage for driving a load is applied to the drain electrode thereof.
A second transistor, a second transistor of the second conductivity type having a source electrode to which a low voltage for driving a load is applied, and a source electrode of the first transistor and a drain electrode of the second transistor. It has a first load drive output terminal connected thereto and a second load drive output terminal connecting the source electrode of the third transistor and the drain electrode of the fourth transistor.

[0016]

In the semiconductor integrated device for a high load driving driver according to the present invention, the first and second well regions of the second conductivity type are formed in the vicinity of the surface of the semiconductor substrate of the first conductivity type, and the first well is formed. A first diffusion layer of the first conductivity type and a second diffusion region of the second conductivity type are formed near the surface in the region. Further this first
A first diffusion region of the second conductivity type is formed in the vicinity of the surface in the diffusion layer, and a first gate oxide film attached to each of the first diffusion region, the first diffusion layer, the first well region and the second diffusion region, And forming a first polysilicon layer attached to the first gate oxide film. A second conductivity type transistor is formed using the above-mentioned first diffusion layer and first diffusion region as a source electrode, the first polysilicon layer as a gate electrode, and the second diffusion region as a drain electrode. Further, in the vicinity of the surface in the above-mentioned second well region, the second conductivity type second having a higher concentration than the second well region is formed.
A diffusion layer and a fourth diffusion region of the first conductivity type are formed. The third diffusion region of the first conductivity type is formed in the vicinity of the surface in the second diffusion layer, and the second well is formed between the second diffusion layer and the fourth diffusion region in the vicinity of the surface in the second well region. A third diffusion layer of the second conductivity type having a concentration lower than that of the region, and a second gate oxide film attached to each of the third diffusion region, the second diffusion layer, the third diffusion layer and the fourth diffusion region, and A second polysilicon layer attached to the second gate oxide film is formed.
The second diffusion layer and the third diffusion region described above are connected to the source electrode, the second diffusion layer and the third diffusion region.
A first conductivity type transistor is formed using the polysilicon layer as a gate electrode and the fourth diffusion region as a drain electrode.

The high load driver device according to the present invention is
First and third transistors composed of the first conductivity type transistor to which a high voltage for load driving is applied to its drain electrode, and the second conductivity type transistor to which a low voltage for driving load is applied to its source electrode. And a fourth transistor, a first load drive output terminal connecting the source electrode of the first transistor and the drain electrode of the second transistor, the source electrode of the third transistor and the drain electrode of the fourth transistor And a second load drive output terminal connected to.

[0018]

FIG. 5 is a diagram showing the structure of a semiconductor integrated device for a high load driver according to the present invention. As shown in the figure, an n well 9 is formed in the vicinity of the surface of the p-type semiconductor substrate 1. In the n well 9, a p-type semiconductor as a diffusion layer of p-type semiconductor is formed.
The tab 10 is formed. At this time, the p tab 10
The impurity concentration of is higher than that of the n-well 9. An n ⁺ diffusion region 2 is formed near the surface of the p-tab 10. An n ⁺ diffusion region 3 is formed near the surface of the n well 9. The n ⁺ diffusion region 2, the p-tab 10,
A gate oxide film 4a is formed by adhering to the surface of each of the n well 9 and the n ⁺ diffusion region 3. This gate oxide film 4
A polysilicon layer 4b is formed adhering to a. The source electrode S is connected to the p tub 10 and the n ⁺ diffusion region 2. The gate electrode G is connected to the polysilicon layer 4b. The drain electrode D is connected to the n ⁺ diffusion region 3.

With this structure, an n-channel LD-MOS transistor is formed on the p-type semiconductor substrate 1. The channel of the n-channel LD-MOS transistor is formed between the boundary of the n ⁺ diffusion region 2 below the gate oxide film 4a and the boundary of the p-tab 10. Therefore, since the channel length L ₁ shown in the figure is determined by the diffusion of the p-tab 10, the channel length can be reduced and the on-resistance can be reduced without reducing the distance between the n ⁺ diffusion regions 2 and 3. You can do it. Further, the impurity concentration of the p-tab 10 is n-well 9
Therefore, the source-drain breakdown voltage becomes a high breakdown voltage.

Further, n is provided near the surface of the p-type semiconductor substrate 1.
Well 5 is formed. An N _H layer 20 which is an n-type diffusion semiconductor layer having an impurity concentration higher than that of the n well 5 is formed in the n well 5. A p ⁺ diffusion region 6 is formed near the surface of the N _H layer 20. A p ⁺ diffusion region 7 is formed near the surface of the n well 5. n
_NH layer 20 and p ⁺ diffusion region 7 near the surface of well 5
And an N _L layer 21 which is an n-type semiconductor layer having an impurity concentration lower than that of the n-well 5. A gate oxide film 8a is formed by adhering to the surface of each of the p ⁺ diffusion region 6, the _NH layer 20, the N _L layer 21, and the p ⁺ diffusion region 7. The polysilicon layer 8 is attached to the gate oxide film 8a.
b is formed. The source electrode S is connected to the _NH layer 20 and the p ⁺ diffusion region 6. The gate electrode G is connected to the polysilicon layer 8b. Drain electrode D
Are connected to the p ⁺ diffusion region 7.

With this structure, a p-channel LD-MOS transistor is formed on the p-type semiconductor substrate 1. In this p-channel LD-MOS transistor, the source side is surrounded by the high-concentration _NH layer 20 to prevent punch-through due to the expansion of the depletion layer. Further, an N _L layer 21 is formed between the N _H layer 20 and the p ⁺ diffusion region 7 to reduce the concentration by implanting boron so that the depletion layer sufficiently spreads at a low drain voltage. At this time, the channel of the p-channel LD-MOS transistor is formed between the _NH layer 20 and the boundary of the p ⁺ diffusion region 6 under the gate oxide film 8a. Therefore, since the channel length L ₂ is determined by the diffusion of the _NH layer 20, a p-channel MOS transistor having a small channel length and a low on-resistance can be obtained without reducing the distance between the p ⁺ diffusion regions 6 and 7. It can be formed. Also, _NH layer 2
Since the impurity concentration of 0 is higher than that of the n-well 5, the source-drain breakdown voltage is high.

As described above, in the high load driver semiconductor integrated device according to the present invention, the first conductivity type (p type) is used.
Near the surface of the semiconductor substrate (p-type semiconductor substrate 1) of
Conductive type (n type) first and second well regions (n well 5
And 9) are formed, and a first conductivity type first diffusion layer (p tub 10) and a second conductivity type second diffusion region (n ⁺ diffusion region 3) are formed in the vicinity of the surface in the first well region. Form. Further, a second diffusion type first diffusion region (n ⁺ diffusion region 2) is formed near the surface in the first diffusion layer, and the first diffusion region,
A first polysilicon layer (polysilicon layer 4b) is formed sandwiching the gate oxide film attached to each of the first diffusion layer, the first well region and the second diffusion region. Here, using the above-mentioned first diffusion layer and first diffusion region as a source electrode, the first polysilicon layer as a gate electrode, and the second diffusion region as a drain electrode, a second conductivity type transistor (n-channel LD-MOS) is formed.
A transistor).

Further, in the vicinity of the surface in the above-mentioned second well region (n well 5), the second diffusion layer ( _NH layer 20) of the second conductivity type having a higher concentration than that of the second well region and the first diffusion layer are formed. A conductive type fourth diffusion region (p ⁺ diffusion region 7) is formed. Further, a third diffusion region (p ⁺ diffusion region 6) of the first conductivity type is formed near the surface in the second diffusion layer, and the second diffusion layer and the fourth diffusion region near the surface in the second well region. A third diffusion layer (N _L layer 21) of the second conductivity type having a lower concentration than that of the second well region is formed between the third diffusion region, the second diffusion layer, the third diffusion layer, and the third diffusion layer. A second polysilicon layer (polysilicon layer 8b) is formed sandwiching the gate oxide film attached to each of the four diffusion regions. Here, using the above-mentioned second diffusion layer and third diffusion region as a source electrode, the second polysilicon layer as a gate electrode, and the fourth diffusion region as a drain electrode, a first conductivity type transistor (p-channel LD-MOS) is formed.
Transistor).

Therefore, according to this structure, the p-channel LD-MOS is formed by the pn junction without performing the dielectric isolation.
The transistor and the n-channel LD-MOS transistor can be formed on the same p-type semiconductor substrate. Figure 6
FIG. 2 is a diagram showing a configuration of the semiconductor integrated device for a high load driving driver according to the present invention when the high load driving driver as shown in FIG. 1 is integrated into an integrated circuit.

As shown, the transistor Q1 in FIG.
And Q3 are p-channel LD-MO as shown in FIG.
Formed with S-transistors, and transistors Q2 and Q4
Is formed by an n-channel LD-MOS transistor as shown in FIG. In such a configuration, since the high-voltage side transistors that supply the load driving power supply V _DD to the load, that is, the transistors Q1 and Q3 are p-channel type, the signal level of the drive control signal for controlling the ON / OFF of these transistors is set to the load drive. It does not need to be higher than the power supply V _DD . Furthermore, all transistors are LD
-Since it has a MOS structure, the on-resistance is low. Therefore, a sufficient current can be supplied to the load without increasing the die size.

[0026]

As is apparent from the above, the semiconductor integrated device for a high load driver according to the present invention is an LD (lateral diffused) -M having a relatively high current supply capability.
This is a CMOS implementation of the OS structure transistor. In the high load drive driver device according to the present invention configured by such a semiconductor integrated device, a high voltage side transistor for supplying load drive power to a load is a p-channel LD-M.
It has an OS structure.

Therefore, according to the present invention, the signal level of the drive control signal for controlling the on / off control of the transistor for supplying the drive power to the load does not need to be higher than the load drive power supply voltage. This is preferable because a level shift circuit for control signals such as a pump circuit is unnecessary. Further, since all the transistors have the LD-MOS structure, the on resistance is low in the switching on state. Therefore, a sufficient current can be supplied to the load without increasing the die size, and the manufacturing yield can be increased. Furthermore, since all the manufacturing steps are performed by pn junction isolation, it is preferable because the manufacturing can be performed by the usual CMOS process technology.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of a high load drive driver.

FIG. 2 is a diagram showing an example of a conventional semiconductor integrated device having a CMOS structure.

FIG. 3 is a diagram showing a configuration of an n-channel LD-MOS transistor.

FIG. 4 is a diagram showing a configuration of a p-channel LD-MOS transistor.

FIG. 5 is a diagram showing a configuration of a semiconductor integrated device for a high load driver according to the present invention.

FIG. 6 is a diagram showing a configuration of a high load drive driver device according to the present invention.

[Explanation of symbols for main parts]

20 N _H layer 21 N _L layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location 7514-4M H01L 29/78 301 D

Claims (4)

[Claims] 1. A first well region of a second conductivity type formed in the vicinity of the surface of a semiconductor substrate of the first conductivity type, and a first well of the first conductivity type formed in the vicinity of the surface in the first well region. A diffusion layer, a second conductivity type first diffusion region formed near the surface in the first diffusion layer, and a second conductivity type second diffusion region formed near the surface in the first well region. And the first
A first gate oxide film formed by adhering to each of the diffusion region, the first diffusion layer, the first well region and the second diffusion region, and a first gate oxide film formed by adhering to the first gate oxide film. A polysilicon layer, a first source electrode formed by connecting the first diffusion layer and the first diffusion region, and the first source electrode
A second conductivity type transistor including a first gate electrode formed to be connected to a polysilicon layer and a first drain electrode formed to be connected to the second diffusion region, and formed near a surface of the semiconductor substrate. The second well region of the second conductivity type, the second diffusion layer of the second conductivity type having a higher concentration than the second well region formed near the surface in the second well region, and the second region. A third diffusion region of the first conductivity type formed near the surface in the diffusion layer, a fourth diffusion region of the first conductivity type formed near the surface in the second well region, and the second well region The second near the inner surface
The second diffusion layer formed between the diffusion layer and the fourth diffusion region;
A second diffusion type third diffusion layer having a concentration lower than that of the well region;
A second gate oxide film formed by adhering to each of the third diffusion region, the second diffusion layer, the third diffusion layer and the fourth diffusion region, and formed by adhering to the second gate oxide film. A second polysilicon layer, the second diffusion layer and the third diffusion layer.
A second source electrode formed by connecting a diffusion region, a second gate electrode formed by connecting to the second polysilicon layer, and a second drain electrode formed by connecting to the fourth diffusion region. And a first-conductivity-type transistor comprising: 2. The first and third transistors, which are composed of the first conductivity type transistor and have a drain electrode to which a high voltage for load driving is applied, and the second conductivity type transistor, which is composed of a source electrode for driving the load. Second and fourth transistors to which a low voltage is applied, a first load drive output terminal that connects the source electrode of the first transistor and the drain electrode of the second transistor, and the source electrode of the third transistor A high load drive driver device comprising a second load drive output terminal connected to the drain electrode of the fourth transistor. 3. The third diffusion layer is formed by implanting boron between the second diffusion layer and the fourth diffusion region in the vicinity of the surface of the second well region. The semiconductor integrated device for a high load driver according to claim 1. 4. The impurity concentration of the first diffusion layer is equal to that of the first diffusion layer.
2. The semiconductor integrated device for a high load drive driver according to claim 1, wherein the concentration is higher than that of the well region.