CN111628002B - MOS tube - Google Patents
MOS tube Download PDFInfo
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- CN111628002B CN111628002B CN202010513021.9A CN202010513021A CN111628002B CN 111628002 B CN111628002 B CN 111628002B CN 202010513021 A CN202010513021 A CN 202010513021A CN 111628002 B CN111628002 B CN 111628002B
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- well
- insulating layer
- source electrode
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- type silicon
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- 238000009792 diffusion process Methods 0.000 claims abstract description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- 239000010703 silicon Substances 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to the field of power semiconductor devices and discloses an MOS tube, which comprises an N-type silicon wafer, wherein the bottom of the N-type silicon wafer is provided with a drain electrode, the top of the N-type silicon wafer is provided with a first P well, a first N diffusion region is arranged in the first P well, the top of the N-type silicon wafer is also provided with a second P well, a second N diffusion region is arranged in the second P well, the top of the N-type silicon wafer is connected with an insulating layer, the insulating layer is provided with a control source electrode, the control source electrode penetrates through the insulating layer to be respectively and electrically connected with the first P well and the first N diffusion region, the insulating layer is also provided with a control grid electrode, the main source electrode penetrates through the insulating layer to be respectively and electrically connected with the second P well and the second N diffusion region, and the main grid electrode is also arranged in the insulating layer to be electrically connected with the control source electrode.
Description
Technical Field
The invention relates to the field of power semiconductor devices, in particular to a MOS tube.
Background
The MSO tube can be divided into low-power, medium-power and high-power MOS tubes according to the power, as shown in fig. 3, the sizes of the capacitors Cgs and Cdg of the MOS tubes with different powers are different, the larger the power is, the larger the capacitance values of the capacitors Cgs and Cdg are, and accordingly, the larger the electric charge amount required by the conduction of the MOS tubes is, so that in the application field of the high-power GOS tube, the requirement on driving I C is higher, and the high-requirement driving I C increases the application cost of the high-power MOS tube.
Disclosure of Invention
In view of the shortcomings of the background technology, the invention provides the MOS tube, and the technical problem to be solved is that the existing high-power MOS tube needs high-current driving when in practical application, the driving I C needs higher, and the application cost is increased.
In order to solve the technical problems, the invention provides the following technical scheme: the MOS tube comprises an N-type silicon wafer, wherein the bottom of the N-type silicon wafer is provided with a drain electrode, the top of the N-type silicon wafer is provided with at least one first P well, at least one first N diffusion region is arranged in the first P well, the top of the N-type silicon wafer is also provided with at least one second P well, and at least one second N diffusion region is arranged in the second P well;
the top of the N-type silicon wafer is connected with an insulating layer, a control source electrode is arranged on the insulating layer, the control source electrode passes through the insulating layer and is respectively and electrically connected with the first P well and the first N diffusion region, a control grid electrode is also arranged in the insulating layer, and the control grid electrode is used for receiving a control signal A for driving the drain electrode and controlling the conduction of the source electrode;
the insulating layer is also provided with a main source electrode, the main source electrode and the control source electrode are separated by the insulating layer, the main source electrode penetrates through the insulating layer to be respectively and electrically connected with the second P well and the second N diffusion region, the insulating layer is also internally provided with a main grid electrode, and the main grid electrode is electrically connected with the control source electrode and is used for receiving a control signal B for driving the drain electrode and the main source electrode to be conducted.
Further, two first N diffusion regions are arranged in parallel in the first P well.
Further, two second N diffusion regions are arranged in parallel in the second P well.
On the N-type silicon wafer, the drain electrode, the control source electrode and the control grid electrode are equivalent to a low-power MOS tube, the drain electrode, the main source electrode and the main grid electrode are equivalent to a high-power MOS tube, the drain electrode of the low-power MOS tube is electrically connected with the drain electrode of the high-power MOS tube, and the source electrode of the low-power MOS tube is electrically connected with the grid electrode of the high-power MOS tube.
Compared with the prior art, the invention has the following beneficial effects: when the MOS tube is applied, the driving current is connected to the control grid electrode, at the moment, the low-power MOS tube is conducted, a passage is formed between the drain electrode and the main grid electrode, the power supply connected with the drain electrode can directly drive the high-power MOS tube to conduct, and the electric charge required for driving the low-power MOS tube to conduct is much smaller than the electric charge required for driving the high-power MOS tube to conduct, so that compared with the direct driving of the high-power MOS tube to conduct, the requirement on driving I C is reduced, the control is easier, and the application cost of the high-power MOS tube is further reduced.
Drawings
The invention has the following drawings:
fig. 1 is a schematic structural diagram of a MOS transistor in embodiment 1;
fig. 2 is a schematic circuit structure of the MOS transistor of the present invention;
fig. 3 is a schematic diagram of a microscopic model of a MOS transistor.
Detailed Description
The invention will now be described in further detail with reference to the accompanying drawings. The drawings are simplified schematic representations which merely illustrate the basic structure of the invention and therefore show only the structures which are relevant to the invention.
As shown in fig. 1, a MOS transistor includes an N-type silicon wafer 1, a drain electrode 11 is disposed at the bottom of the N-type silicon wafer 1, at least one first P-well 2 is disposed at the top of the N-type silicon wafer 1, at least one first N diffusion region 3 is disposed in the first P-well 2, in this embodiment, two first N diffusion regions 3 are disposed in the first P-well 2, at least one second P-well 4 is further disposed at the top of the N-type silicon wafer 1, at least one second N diffusion region 5 is disposed in the second P-well 4, and in this embodiment, two second N diffusion regions 5 are disposed in the second P-well 4;
the top of the N-type silicon wafer 1 is connected with an insulating layer 6, a control source electrode 7 is arranged on the insulating layer 6, the control source electrode 7 penetrates through the insulating layer 6 to be respectively and electrically connected with the first P well 2 and the first N diffusion region 3, a control grid electrode 8 is also arranged in the insulating layer 6, and the control grid electrode 8 is used for receiving a control signal A for controlling the conduction of a driving drain electrode 11 and the control source electrode 7;
the insulating layer 6 is further provided with a main source electrode 9, the main source electrode 9 and the control source electrode 7 are separated by the insulating layer 6, the main source electrode 9 penetrates through the insulating layer 6 to be respectively electrically connected with the second P well 4 and the second N diffusion region 5, the insulating layer 6 is internally provided with a main grid electrode 10, and the main grid electrode 10 is electrically connected with the control source electrode 7 and is used for receiving a control signal B for conducting the driving drain electrode 11 and the main source electrode 9.
Further, two first N diffusion regions 3 are disposed in parallel in the first P well 2.
Further, two second N diffusion regions 5 are disposed in parallel in the second P-well 4.
On the N-type silicon wafer 1, the drain 11, the control source 7 and the control gate 8 are equivalent to a low-power MOS transistor, the drain 11, the main source 9 and the main gate 10 are equivalent to a high-power MOS transistor, and specific pin connection relationships are shown in fig. 3. In fig. 3, the MOS transistor on the left side is a low-power MOS transistor, the MOS transistor on the right side is a high-power MOS transistor, when the high-power MOS transistor is driven to be turned on, a driving power supply is connected to the gate of the low-power MOS transistor, and when the low-power MOS transistor is turned on, the power supply connected with the high-power MOS transistor can be directly connected to the gate of the low-power MOS transistor, so that the high-power transistor is driven to be turned on.
In summary, when the invention is actually used, the high-power MOS tube is conducted by triggering the conduction of the low-power MOS tube, and compared with the direct triggering of the conduction of the high-power MOS tube, the required electric charge quantity is less, the requirement on driving I C is reduced, and the control is easier.
The present invention has been made in view of the above-described circumstances, and it is an object of the present invention to provide a portable electronic device capable of performing various changes and modifications without departing from the scope of the technical spirit of the present invention. The technical scope of the present invention is not limited to the description, but must be determined according to the scope of claims.
Claims (3)
1. An MOS transistor, characterized in that: comprises an N-type silicon wafer,
the bottom of the N-type silicon wafer is provided with a drain electrode, the top of the N-type silicon wafer is provided with at least one first P well, at least one first N diffusion region is arranged in the first P well, the top of the N-type silicon wafer is also provided with at least one second P well, and at least one second N diffusion region is arranged in the second P well;
the top of the N-type silicon wafer is connected with an insulating layer, a control source electrode is arranged on the insulating layer and penetrates through the insulating layer to be electrically connected with the first P well and the first N diffusion region respectively, a control grid electrode is also arranged in the insulating layer and used for receiving a control signal A for driving the drain electrode to be conducted with the control source electrode, a main source electrode is also arranged on the insulating layer and is separated from the control source electrode by the insulating layer, the main source electrode penetrates through the insulating layer to be electrically connected with the second P well and the second N diffusion region respectively, a main grid electrode is also arranged in the insulating layer and is electrically connected with the control source electrode and used for receiving a control signal B for driving the drain electrode to be conducted with the main source electrode.
2. The MOS transistor of claim 1, wherein: and two first N diffusion regions are arranged in the first P well in parallel.
3. The MOS transistor of claim 1, wherein: and two second N diffusion regions are arranged in the second P well in parallel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010513021.9A CN111628002B (en) | 2020-06-08 | 2020-06-08 | MOS tube |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010513021.9A CN111628002B (en) | 2020-06-08 | 2020-06-08 | MOS tube |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111628002A CN111628002A (en) | 2020-09-04 |
| CN111628002B true CN111628002B (en) | 2023-05-23 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010513021.9A Active CN111628002B (en) | 2020-06-08 | 2020-06-08 | MOS tube |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111628002B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04127565A (en) * | 1990-09-19 | 1992-04-28 | Nec Corp | Semiconductor device provided with resistance element |
| US5202907A (en) * | 1991-06-04 | 1993-04-13 | Sony Corporation | Solid-state image sensor output mosfet amplifier with mosfet load |
| JPH07221196A (en) * | 1994-02-04 | 1995-08-18 | Nippon Motorola Ltd | High load driver and semiconductor integrated device for the same |
| CN200986919Y (en) * | 2006-12-08 | 2007-12-05 | 广州南科集成电子有限公司 | Vertical type self-aligning suspension drain triode |
-
2020
- 2020-06-08 CN CN202010513021.9A patent/CN111628002B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04127565A (en) * | 1990-09-19 | 1992-04-28 | Nec Corp | Semiconductor device provided with resistance element |
| US5202907A (en) * | 1991-06-04 | 1993-04-13 | Sony Corporation | Solid-state image sensor output mosfet amplifier with mosfet load |
| JPH07221196A (en) * | 1994-02-04 | 1995-08-18 | Nippon Motorola Ltd | High load driver and semiconductor integrated device for the same |
| CN200986919Y (en) * | 2006-12-08 | 2007-12-05 | 广州南科集成电子有限公司 | Vertical type self-aligning suspension drain triode |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111628002A (en) | 2020-09-04 |
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