JP2562419B2 - Method of manufacturing complementary thin film transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a complementary thin film transistor (hereinafter referred to as a CMOS circuit ) composed of a thin film transistor (hereinafter referred to as a TFT).

[0002]

2. Description of the Related Art In a conventional CMOS circuit comprising an N-type MOS transistor and a P-type MOS transistor formed on a silicon wafer, when each transistor is formed on the same wafer, a P-type transistor is used when an N-type wafer is used. When a P-type wafer is used, an N-type well is formed. Then, a MOS transistor is formed separately in addition to the well portion and the well portion in the wafer, and the common electrode region is formed of a conductive material such as aluminum. In this method, a wafer having a different type from the wafer is required, two contacts are required to draw an electrode from the common electrode region, and a transistor interval is required. There is a limit in terms of reduction, and there is a problem in miniaturization.

[0003]

SUMMARY OF THE INVENTION The present invention solves such a problem, and an object of the present invention is to form an N-type TFT and a P-type TFT on the same semiconductor to form a thin film C.
By configuring a MOS circuit, the interval between transistors can be reduced, and the common electrode can be
It is to measure the miniaturization of the OS circuit.

[0004]

SUMMARY OF THE INVENTION The complementary thin film transistor of the present invention.
The method of manufacturing the transistor is such that the first conductivity type and the second conductivity type are formed on the substrate.
The source / drain / channel regions of the electric transistor
Forming a composed non-single-crystal semiconductor layer, the first and second
Source / drain of 2 conductivity type transistor is formed
Implant one of P-type impurity and N-type impurity into the region
And the source / drain of the first conductivity type transistor.
The second conductivity type tiger is covered by covering the area where the rain is formed .
In the region where the source / drain of the transistor is formed, the P
Of implanting the other impurity of the N-type impurity and the N-type impurity
And the saw of the first conductivity type and second conductivity type transistors
Forming an interlayer insulating film on the scan-drain, the first
One of the source / drain of the conductivity type transistor and the first
One of the source and drain of the two conductivity type transistor
A common electrode to be connected is a common electrode formed on the interlayer insulating film.
A contact hole is formed.
And are characterized.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments.

Reference Example In the description, an inverter which is a basic circuit is used as a circuit. FIG. 1 shows an inverter formed on a conventional silicon wafer, and FIG. 2 shows an inverter formed by a TFT of a reference example of the present invention . 1a and 2a are top views of the inverter, and FIGS. 1b and 2b are AA 'and B, respectively.
It is sectional drawing when it cut | disconnects by B '.

The difference between the structure and fabrication of the CMOS circuit shown in FIGS. 1 and 2 is that a thin film CMOS circuit (FIG. 2B)
Then, the same semiconductor layer 12 is formed without forming the well 2.
In addition, the source and drain regions of the N-type TFT and the P-type TFT are formed, and a common electrode among the electrodes of the N-type transistor and the P-type transistor. However, this means that the drain electrode is taken out from the drain region of both transistors by only one contact.

Next, a method of manufacturing a thin film CMOS circuit will be described.

A reference example of the present invention will be described with reference to FIG.
Then , the semiconductor layer 12 is formed on the insulating substrate 11 and etched into an appropriate shape to form a gate film. Then
After the semiconductor layer is formed, the gate electrode 17 is formed by impurity diffusion or a highly conductive material to form an N-type TFT and a P-type TF.
The source and drain regions of T are formed by ion implantation of an impurity ion beam or the like. For the source and drain regions, the N-type T
The FT and the P-type TFT are separately formed. As shown in FIG. 2B, the source and drain regions are formed in the same semiconductor layer for both transistors. In particular, the drain regions are sufficiently close to each other to have a structure such as 13, 14, 15.
Next, after an interlayer insulating film 18 is formed, a contact is made with a conductive material to form an inverter.

[0010] In addition, in FIG. 3, a drain electrode is <br/> Eject is common than the overlap region 15 P-type and N-type impurity drain region formed by ion implantation or the like are mixed.

(Embodiment) An embodiment of the present invention will be described with reference to FIG. Except for the method of forming the source region and the drain region, the fabrication is performed in the same manner as the above reference example . When implanting impurities, the source region and the drain region are first implanted with N-type impurities or P-type impurities over the entire surface of the source region and drain region.
Type TFT, when injecting P-type impurities, the P-type TFT is masked with a resist or the like, and impurities of the opposite type are injected,
The source region and the drain region of the N-type TFT and the P-type TFT are formed. Therefore, both the N-type impurity and the P-type impurity are present in the region of the contacting regions 13 and 14 formed on the side formed by impurity implantation later.

As described above, according to the present invention, the thin film CM
In the N-type TFT and the P-type TFT of the OS circuit, by forming each source region and drain region on the same semiconductor thin film, it is possible to greatly reduce the transistor interval, miniaturize the thin-film CMOS circuit itself, and thin-film CMOS. This has a great effect on high integration of an integrated circuit using a circuit.

In addition, since the source region and the drain region are formed in a polycrystalline or amorphous non-single-crystal layer, the flow of carriers due to contact between the P-type region and the N-type region is formed in a single crystal. As compared with the case, the output can be sufficiently taken out by the common electrode.

In the configuration of FIG. 4, the structure of the boundary region between the N-type TFT and the P-type TFT is further simplified, so that further miniaturization can be achieved as compared with the case of FIG.

[0015]

The present invention, by adopting such a constitution, has the following remarkable operational effects.

According to the manufacturing method of the present invention, excellent characteristics can be obtained.
Very simple method for manufacturing complementary thin film transistor having
Can be obtained at That is, the present invention includes the first and second
Rather than manufacturing the conductive type TFT separately,
Of the region where the source / drain of the two conductivity type TFT is formed
One of P-type and N-type impurities is implanted into the whole
And the source and drain of the first conductivity type TFT are formed
The other of the P-type and N-type impurities
Since it has an injection process, it simplifies the manufacturing process.
To be done.

Further, the source drain of the first conductivity type TFT
Source region and drain region of the second conductivity type TFT
It is not necessary to provide a separate contact with one of the
Common contact holes to form more common electrodes
Since it can be formed, the process can be simplified.
It

A P-type TFT and an N-type TF are formed on the non-single crystal semiconductor layer.
To form the source / drain region of T and obtain the output
The regions that make PN junction by directly contacting each drain region
Even if it is formed, it is charged along the grain boundaries in the non-single crystal semiconductor layer.
Current leaks or current leaks through crystal defects in crystals
Therefore, the PN junction is formed by a single crystal semiconductor.
It does not show the remarkable diode characteristics when formed. Obey
By directly connecting the P-type TFT and N-type TFT with a PN junction
P-type source / drain region and N-type source / drain
The in regions may not be formed separately.

[Brief description of drawings]

FIG. 1A is a top view showing a structure of a conventional CMOS inverter. (B) is sectional drawing which shows the structure of the conventional CMOS inverter.

FIG. 2A is a top view showing a structure of a thin film CMOS inverter of a reference example . (B) is sectional drawing which shows the structure of the thin film CMOS inverter of a reference example .

FIG. 3 is a diagram showing a structure in which the contact position of the drain electrode is taken out from the overlapping portion of the drain in the reference example of FIG.

FIG. 4 is a diagram showing a structure of a thin film CMOS inverter according to an embodiment of the present invention .

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Silicon wafer 2 ... Well 3 ... Source (right) and drain (left) area 4 ... Source (right) and drain (left) area 5 ... Gate film 6 ... Gate Electrode 7 ... Insulating film 8 ... Output line (drain electrode) 9 ... Power supply line (source electrode) 10 ... Input line (gate electrode) 11 ... Insulating substrate 12 ... Semiconductor layer 13 Source (right) and drain (left) regions 14 ... Source (right) and drain (left) regions 15 ... Drain overlap region 16 ... Gate film 17 ... Gate electrode 18 ... Insulating film 19 ... Output line (drain electrode) 20 ... Power supply line (source electrode) 21 ... Input line (gate electrode)

 ─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-52-113177 (JP, A) JP-A-57-50463 (JP, A) JP-A-57-102047 (JP, A) JP-A-58- 25266 (JP, A) JP 58-118154 (JP, A) JP 57-21855 (JP, A) JP 57-71170 (JP, A) JP 57-103358 (JP, A) JP-A-58-91675 (JP, A)

Claims (1)

(57) [Claims] 1. A first-conductivity type and a second-conductivity type transistor on a substrate.
Non-single connection for source / drain / channel region of transistor
And a source / drain of the first and second conductivity type transistors
Of P-type impurities or N-type impurities in the region where
Step of implanting impurities and forming the source / drain of the first conductivity type transistor
The region of the second conductivity type transistor,
In the region where the source / drain is formed, the P-type impurity and
Implanting the other of the N-type impurities , and the source / source of the first conductivity type and second conductivity type transistors.
A step of forming an interlayer insulating film on the drain, and one of the source / drain of the first conductivity type transistor
And one of the source / drain of the second conductivity type transistor
A common electrode connected to the
And the step of forming via a common contact hole
Method of manufacturing complementary thin film transistor characterized by
Law.