JPS60186053A - Thin film complementary mos circuit - Google Patents

Abstract

PURPOSE:To microminiaturize a CMOS circuit by forming N type TFT and P type TFT on the same semiconductor to form a thin film CMOS circuit, thereby reducing a transistor interval and connecting a common electrode with only one contact. CONSTITUTION:A semiconductor layer 12 is formed on an insulating substrate 11, etched in the suitable shape, and a gate film is formed. Then, after a semiconductor layer is formed, a gate electrode 17 is formed by impurity diffusing or highly conductive material, the source and drain regions of N type TFT and P type TFT are coupled by ion implanting of an impurity ion beam. The source and drain regions are separately formed at the N type and P type TFTs with the TFT of one side with a resist as a mask. The source and drain regions are formed on the same semiconductor layer of both the transistors, and particularly in the drain regions are sufficiently approached between the both transistors in a structure like 13, 14, 15. Then, after an interlayer insulating layer 18 is formed, a contact is formed by a conductive material, thereby forming an inverter.

Description

[Detailed description of the invention] 〔Technical field〕 The present invention relates to a thin film transistor (hereinafter referred to as Tll'T).

) consisting of a thin film complementary MO8 circuit (hereinafter referred to as thin film 0M0
It is written as 8 circuits. ) regarding the structure of the common electrode section.

[Prior art]

OM consisting of N-type MOS transistors and P-type MO8) transistors formed on a conventional silicon wafer
In an OS circuit, when forming each transistor on the same wafer, a P-type well is formed when an N-type wafer is used, and an N-type well is formed when a P-type wafer is used. 1. In addition to the well part, MOEI) transistors are formed separately and the common electrode area is connected with a conductive material such as aluminum to form an OMOS structure. In this method, the wafer is always separated from the mold. This requires wafers with different sizes, requires two contacts to lead out the electrode from the common electrode region, and limits the reduction in the distance between transistors, which poses problems in advancing miniaturization.

〔the purpose〕

The present invention is intended to solve these problems, and its purpose is to form a thin film transistor by forming an N-type TFT, a P-type TFT, and an FT on the same semiconductor. The goal is to reduce the spacing and make the common electrode the only contact (!to miniaturize MOS circuits).

〔overview〕

A feature is that the common electrode portion of the thin film CM08 circuit composed of an N-type thin film transistor and a P-made thin film transistor is formed in the same semiconductor, and the electrode is formed by a unique contact.

〔Example〕

Hereinafter, the present invention will be described in detail based on examples.

In the explanation, an inverter, which is a basic circuit, will be used as the circuit. FIG. 1 shows an inverter fabricated on a conventional silicon wafer, and the second line shows an inverter made of TPT. Figures 1 (α) and 2 (α) are top views of the inverter, and Figures 1 (b) and 2 (b) are A
FIG. 3 is a cross-sectional view taken along lines A' and BB'.

The difference in structure and diameter between the 0MO8 circuits shown in FIG. 1 and FIG.
N type T? Forming the source and drain regions of T and P type TFTs, as well as N type transistors and P type transistors? The width of the electrode is a common electrode, which is the drain electrode and gate electrode in the figure, and the drain electrode is taken out from the drain regions of both transistors by a single contact.

Next, the method for manufacturing the thin film 0M08 circuit will be explained.

A semiconductor layer 12 is formed on an insulating substrate 11, etched into a suitable shape, and then a gate film is formed.

Next, the gate electrode 17 is formed by impurity diffusion after forming the semiconductor N or by using a highly conductive material, and the source and drain regions of the N-type TFT and P-type TFT are formed by ion implantation with an impurity ion beam or the like. The source and drain regions are separately formed using an N-type TFT and a P-type TFT by masking the TIFT on one side with a resist or the like. As shown in FIG. 2, the source and drain regions of both transistors are formed in the same semiconductor layer, and in particular, the drain regions are placed sufficiently close to each other between both transistors, and the angle of 13°14.1
The structure is as shown in 5. Next, after forming an interlayer insulating layer 18, contact is made with a conductive material to form an inverter.

In addition, Fig. 3 shows that the manufacturing method is as described above, but
FIG. 3 is a diagram showing that a common drain electrode is taken out from an overlapping region 15 in which P-type and N-type impurities coexist in a drain region formed by ion implantation or the like.

The structure shown in FIG. 4 is manufactured in the same manner as described above except for the method of forming the source region and drain region. When implanting impurities into the source and drain regions, first, N-type impurities or P-type impurities are implanted into the entire surface of the source and drain regions.
When implanting type impurities, N-type TPT and when implanting P-type impurities, P-type 'fFT are masked with a resist, etc., and the opposite type impurity Th is implanted. '
Form source and drain regions of FT.

〔effect〕

As described above, according to the present invention, the thin film 0M08
N-type TFT and P-type TT in the circuit! In T, by forming each source region and drain region in the same semiconductor thin film, it is possible to significantly reduce the transistor spacing, and the thin film CMO8 circuit itself can be miniaturized and the thin film zero
This has a great effect on increasing the degree of integration of integrated circuits using M08 circuits.

In addition, as shown in FIG. 3, since the source region and drain region are formed in a polycrystalline or amorphous layer,
Restrictions on carrier flow due to contact between the P-type region and the N-type region are relaxed compared to when forming in a single crystal, and sufficient contact can be made by drawing out the electrodes as shown in Figure 3. I can do it.

In FIG. 4, the structure of the boundary between the common electrode regions of the N-type TPT and P-type TFT is simplified, so as shown in FIG.
The common electrode 19 is taken out using N type TNT and P type T1.
In the case of extracting across 1T, since there is no region where impurities of different types are mixed, it is possible to reduce the common electrode portion, and further miniaturization is possible.

[Brief explanation of the drawing]

FIG. 1 shows the structure of a conventional CMOS inverter, and FIG. 2 shows a thin film CMOS inverter. In both figures, (-) is a top view, and (h) is a cross-sectional view. FIG. 5 is a diagram showing a structure in which the contact position of the drain electrode is taken out from the overlapping portion of the drain in FIG. 2. FIG. 4 shows the structure of a thin film CMOS inverter in which the drain and source regions are formed in different ways.
Silicon wafer 2... Well 6... Source (right) and drain (left) region 4... Source (left) and drain (right) region 5...・Gate film 6... Gate electrode 7... Insulating film 8... Output line (drain electrode) 9...
...Power line (source electrode) 10...Input line (
Gate electrode) 11... Insulating substrate 12... Semiconductor layer 13... Source (right) and drain (left) region 14
...Source (left) and drain (right) region 15...
・Drain overlapping region 16...Gate film 17...Gate electrode 18...Insulating film 19...Output line (drain electrode) 20...Power line (source electrode) 21...Input line ( (Gate electrode) Applicant Suwa Seikosha Co., Ltd. Representative Patent Attorney - Tsutomu Mogami Figure 1 Figure 2 Figure 4

Claims (1)

[Claims] In a thin film complementary MO8 circuit composed of an N thin film transistor and a P type thin film transistor, a common source region or drain region of the N type thin film transistor and the P type thin film transistor is formed in the same semiconductor thin film, and is the only contact. A thin film complementary MO8 circuit characterized in that a common electrode is formed from a hole.