JP2001068680A - Semiconductor device and fabrication thereof - Google Patents

Semiconductor device and fabrication thereof

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Publication number
JP2001068680A
JP2001068680A JP2000101787A JP2000101787A JP2001068680A JP 2001068680 A JP2001068680 A JP 2001068680A JP 2000101787 A JP2000101787 A JP 2000101787A JP 2000101787 A JP2000101787 A JP 2000101787A JP 2001068680 A JP2001068680 A JP 2001068680A
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Japan
Prior art keywords
tft
film
region
formed
channel
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JP2000101787A
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JP2001068680A5 (en
JP4651773B2 (en
Inventor
Kenji Kasahara
Ritsuko Kawasaki
Hideto Kitakado
英人 北角
律子 河崎
健司 笠原
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Semiconductor Energy Lab Co Ltd
株式会社半導体エネルギー研究所
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Priority to JP11-99481 priority
Priority to JP11-176120 priority
Priority to JP17612099 priority
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Priority to JP2000101787A priority patent/JP4651773B2/en
Publication of JP2001068680A publication Critical patent/JP2001068680A/en
Publication of JP2001068680A5 publication Critical patent/JP2001068680A5/ja
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Publication of JP4651773B2 publication Critical patent/JP4651773B2/en
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Abstract

PROBLEM TO BE SOLVED: To enhance operational characteristics and reliability of a semiconductor device by employing a bottom gate type or an inversely staggered TFT structure being disposed in each circuit of a semiconductor device appropriately depending on the function of the circuit. SOLUTION: The LDD regions 159-162 of an n-channel TFT 169 in a pixel TFT are arranged not to lap over the protective insulation film of channel but to lap over a gate electrode at least partially. The LDD regions 153-154 of an n-channel TFT 168 for a drive circuit are arranged not to lap over the protective insulation film of channel but to lap over the gate electrode at least partially. The LDD regions 148-149 of a p-channel TFT 167 for the drive circuit are arranged to lap over the protective insulation film of channel and the gate electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a circuit composed of thin film transistors (hereinafter referred to as TFTs) on a substrate having an insulating surface. In particular, the present invention relates to an electro-optical device typified by a liquid crystal display device in which a pixel TFT provided in a display region and a drive circuit provided in the periphery of the display region are provided on the same substrate, and such an electro-optical device It can be suitably used for an electronic device equipped with the device. Note that in this specification, a semiconductor device generally refers to a device that functions by utilizing semiconductor characteristics, and includes the above-described electro-optical device and an electronic device equipped with the electro-optical device in its category.

[0002]

2. Description of the Related Art A TFT in which an active layer is formed of a crystalline silicon film on a substrate having an insulating surface (hereinafter referred to as a crystalline silicon TFT) has a high field-effect mobility and therefore forms various functional circuits. The electro-optical device has been developed in which such a functional circuit is integrally formed on the same substrate. An active matrix liquid crystal display device is well known as a typical example.

In an active matrix type liquid crystal display device using a crystalline silicon TFT, a pixel TFT is formed for each pixel in an image display area, and a drive circuit is provided around the image display area. The drive circuit includes a shift register circuit, a level shifter circuit, a buffer circuit, a sampling circuit, and the like, which are formed based on a CMOS circuit. Such circuits are formed over the same substrate, and a display device is completed as one.

[0004] Since the operating conditions of the pixel TFT and the driving circuit are not always the same, the characteristics required for the TFT are not less different. For example, a pixel TFT is required to function as a switch element for applying a voltage to liquid crystal. Since the liquid crystal is driven by alternating current, a method called frame inversion drive is often used. In this method, the pixel TF
The characteristic required for T was to sufficiently reduce the off-current value (drain current flowing when the TFT was turned off). On the other hand, a high driving voltage is applied to the buffer circuit of the driving circuit.
It was necessary to increase the breakdown voltage of the FT. Further, in order to increase the current driving capability, it is necessary to sufficiently secure an on-current value (a drain current flowing when the TFT is turned on).

However, there is a problem that the off-current value of the crystalline silicon TFT tends to be high. Also, I
As with the MOS transistor used for C and the like, a deterioration phenomenon such as a decrease in the on-current value is observed in the crystalline silicon TFT. The main cause is hot carrier injection, and it is considered that hot carriers generated by a high electric field near the drain cause a deterioration phenomenon.

As a structure of a TFT for reducing an off-current value, a lightly doped drain (LDD) is used.
ain) The structure is known. In this structure, a region to which an impurity element is added at a low concentration is provided between a channel formation region and a source or drain region formed by adding an impurity element at a high concentration. This region is referred to as an LDD region. Calling.

A method of manufacturing a TFT having an LDD region is disclosed in, for example, Japanese Patent No. 2564725, in which a gate insulating film is formed to be wider than a gate electrode in a channel width direction, and an insulating film thinner than the gate insulating film is formed beside the gate electrode. do it,
A method is disclosed in which an LDD region is formed in a semiconductor film between an end of a gate electrode and a source or drain region by utilizing a difference in thickness between the insulating film and the gate insulating film.

As means for preventing deterioration due to hot carriers, a so-called GOLD in which an LDD region is arranged so as to overlap a gate electrode with a gate insulating film interposed therebetween.
(Gate-drain Overlapped LDD) structure is known. With such a structure, a high electric field in the vicinity of the drain is relaxed to prevent hot carrier injection, which is effective in preventing a deterioration phenomenon. For example, "Mutuko Hatano, Hajime
Akimoto and Takeshi Sakai, IEDM97 TECHNICAL DIGEST,
p523-526, 1997 "discloses a GOLD structure formed by a sidewall formed of silicon, but it has been confirmed that extremely superior reliability can be obtained as compared with TFTs having other structures.

The introduction of an impurity element into a semiconductor layer for forming an impurity region such as a source region and a drain region and an LDD region of a TFT having such a structure is performed by using a gate electrode provided on the semiconductor layer or a mask. It is desirable to perform the method in a self-aligned manner using an insulating film. further,
In order to reduce the number of masks, an impurity element of one conductivity type is first introduced over the entire surface by using a gate electrode or an insulating film for a mask, and one of a p-channel TFT and an n-channel TFT with a higher concentration than that. (Hereinafter referred to as a cross-doping method) in which an impurity element of a conductivity type opposite to one conductivity type is introduced into the impurity region of the TFT.

[0010]

However, the pixel T
The required characteristics of an FT and a TFT of a driver circuit such as a shift register circuit or a buffer circuit are not necessarily the same. For example, a large reverse bias (negative voltage for an n-channel TFT) is applied to the gate of the pixel TFT, but the TFT of the driving circuit does not basically operate in the reverse bias state. Also, the operation speed of the pixel TFT was 1/100 or less of the TFT of the driving circuit, which was good.

Although the GOLD structure has a high effect of preventing the deterioration of the ON current value, it has a problem that the OFF current value becomes larger than that of the ordinary LDD structure. Therefore, it was not a preferable structure to be applied to the pixel TFT. Conversely, the ordinary LDD structure has a high effect of suppressing the off-current value, but has a low effect of relaxing the electric field near the drain to prevent deterioration due to hot carrier injection. As described above, in a semiconductor device having a plurality of integrated circuits having different operating conditions, such as an active matrix liquid crystal display device, it is not always preferable to form all the TFTs with the same structure. Such problems are particularly problematic in crystalline silicon TF
At T, the characteristics have been enhanced, and the performance required for the active matrix type liquid crystal display device has been enhanced.

Although there are some means for reducing the off-current value of the TFT, it is necessary to form a good junction between the channel forming region and the impurity region (LDD region, source region or drain region). there were. For that purpose, it is necessary to precisely control the distribution of the impurity element at the interface between the channel formation region and the impurity region in contact with the channel formation region. However, when the above-mentioned cross doping method is performed,
One conductivity type impurity element and the opposite conductivity type impurity element are introduced into the impurity region of one TFT, and it is difficult to precisely control the distribution of the impurity element at the interface.

[0013] Such an LDD structure is an n-channel type TF.
It was formed with emphasis on the characteristics of T. CMOS
A p-channel TFT formed on the same substrate for forming a circuit or the like is often formed in a single drain structure in order to minimize the number of masks.
However, in this case, phosphorus (P) for forming an LDD of an n-channel TFT is doped into the source or drain region of the p-channel TFT, a defect is formed at a junction with the channel formation region, and the off-current value increases. There was a problem.

The present invention is a technique for solving such a problem, and includes a TFT arranged in each circuit of a semiconductor device.
The object of the present invention is to improve the operating characteristics and reliability of the semiconductor device by making the structure of the semiconductor device appropriate according to the function of the circuit.

[0015]

According to an aspect of the present invention, there is provided a display device comprising: a pixel TFT provided in a display area;
An n-channel type TF of a driving circuit provided around the display area
In a semiconductor device having a T-type and a p-channel type TFT on the same substrate, the pixel TFT and the TFT of the driving circuit include an active layer, an LDD region provided in the active layer, the active layer and the substrate. A gate insulating film provided between the
A gate electrode provided between the gate insulating film and the substrate; and the pixel TFT and an LDD region of an n-channel TFT of the driver circuit are arranged so as to at least partially overlap the gate electrode. The LDD region of the p-channel TFT of the driving circuit is disposed so as to entirely overlap the gate electrode. Also,
N-channel TFT between the pixel TFT and the driving circuit
Is arranged so as not to overlap with the channel protection insulating film provided in the TFT and at least partially overlap with the gate electrode, and the LDD region of the p-channel TFT of the driving circuit is And the gate insulating film is overlapped with the protective insulating film.

In another aspect of the present invention, the p-channel TFT of the driving circuit includes an impurity element imparting p-type and an n-type TFT.
An impurity region (A) containing both an impurity element imparting a type and an impurity region (B) containing only an impurity element imparting a p-type, and the impurity region (B) is formed of the impurity region ( A) and between the LDD region of the p-channel TFT of the driving circuit.

In this structure, phosphorus (P) doped in the source or drain region of the p-channel TFT without increasing the number of masks is not doped in the junction with the channel forming region, and the off-state current is reduced. The aim is to reduce the value.

The storage capacitor connected to the pixel TFT is formed of a capacitor wiring formed on the substrate, an insulating film formed on the capacitor wiring, and a semiconductor layer formed on the insulating film. Or an organic resin film is formed on the pixel TFT, a light-shielding film formed on the organic resin film, and a dielectric film formed in close contact with the light-shielding film; A capacitor is formed from a pixel electrode provided so as to overlap with the light-shielding film and connected to the pixel TFT.

In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention includes a method of manufacturing a semiconductor device, comprising the steps of:
An n-channel type TF of a driving circuit provided around the display area
In a method for manufacturing a semiconductor device having a T and a p-channel TFT on the same substrate, a step of forming an LDD region at least partially overlapping the gate electrode in the pixel TFT and the n-channel TFT; Drive circuit p
L which overlaps the gate electrode with the channel type TFT
Forming a DD region. Further, the pixel TFT and the n-channel TFT
Forming an LDD region that does not overlap with the channel protection insulating film of the TFT and at least partially overlaps with the gate electrode; and a p-channel TFT of the drive circuit.
In addition, all of the TFT and the channel protection insulating film overlap,
And forming an LDD region overlapping with the gate electrode.

In the above-described method for fabricating a semiconductor device, the p-channel TFT of the driving circuit may further include: an impurity region (A) containing both an impurity element imparting p-type and an impurity element imparting n-type; Forming an impurity region (B) containing an impurity element for imparting the impurity, wherein the impurity region (B) is formed between the impurity region (A) and the LDD region of the p-channel TFT of the driving circuit. It is desirable to form it.

According to another aspect of the present invention, there is provided a semiconductor device having a pixel TFT provided in a display region and an n-channel TFT and a p-channel TFT of a driving circuit provided around the display region on the same substrate. In a method for manufacturing a device, a first step of forming a gate electrode on a substrate, a second step of forming a gate insulating film on the gate electrode, and first and second semiconductors on the gate insulating film A third step of forming a layer, a fourth step of forming a channel protective film on the first and second semiconductor layers, and introducing an impurity element imparting n-type into the first semiconductor layer. A fifth step of forming an LDD region of an n-channel TFT that does not overlap with the channel protective film; and introducing an impurity element imparting n-type into the first semiconductor layer to form a source of the n-channel TFT. Region or drain A sixth step of forming a region, and introducing an impurity element imparting p-type into the second semiconductor layer to form an LDD region and a source region or a drain region of the p-channel TFT overlapping the channel protective film. And a seventh step of forming.

In the method of manufacturing a semiconductor device according to the present invention, a step of forming a capacitor wiring on the substrate, a step of forming an insulating layer on the capacitor wiring, and a step of forming a semiconductor layer on the insulating layer Forming a storage capacitor connected to the pixel TFT, or forming an organic resin layer on the pixel TFT, forming a light-shielding film on the organic resin, and closely contacting the light-shielding film. The step of forming a dielectric film and the step of forming a pixel electrode provided so as to partially overlap the light-shielding film and connected to the pixel TFT form a capacitor. Preferably, the light-shielding film is formed of a material containing one or more kinds selected from aluminum, tantalum, and titanium, and the dielectric film is formed of an oxide of a material for forming the light-shielding film. It is most preferable to use an anodic oxidation method as a method of forming a product.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail with reference to the following examples.

[Embodiment 1] An embodiment of the present invention will be described with reference to FIGS. Here, the pixel TFT in the display area and
A method for simultaneously manufacturing TFTs of a driver circuit provided around the display region will be described in detail according to steps.

(Formation of Gate Electrode, Gate Insulating Film, and Crystalline Semiconductor Film: FIG. 1A) In FIG.
For 01, a low alkali glass substrate or a quartz substrate can be used. An insulating film such as a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film may be formed on a surface of the substrate 101 on which a TFT is formed (not shown). The gate electrodes 102 to 104 and the capacitor wiring 105 are made of an element selected from tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), and aluminum (Al) or a material containing any one of them as a main component. After forming a film by using a known film forming method such as a sputtering method or a vacuum evaporation method, a pattern was formed by performing an etching process so that an end face was tapered. For example, a Ta film is formed to a thickness of 200 nm by a sputtering method, a resist mask is formed in a predetermined shape, and then a plasma etching process is performed with a mixed gas of CF 4 and O 2 to process the film into a desired shape. it can. The gate electrode is made of tantalum nitride (Ta).
N) and Ta or a two-layer structure of tungsten nitride (WN) and W (not shown). Although not shown here, a gate wiring connected to the gate electrode is also formed at the same time.

The gate insulating film 106 is made of a material containing silicon oxide and silicon nitride and has a thickness of 10 to 200 nm, preferably 50 to 150 nm. For example, by a plasma CVD method, a silicon nitride film 106a using SiH 4 , NH 3 , and N 2 as raw materials is formed to a thickness of 50 nm, and a silicon nitride oxide film 106b using SiH 4 and N 2 O as raw materials is formed to a thickness of 75 nm. It may be used as a gate insulating film. Of course, a single layer made of a silicon nitride film or a silicon oxide film may be used. In addition, in order to obtain a clean surface, it is preferable to perform plasma hydrogen treatment before forming the gate insulating film.

Next, a crystalline semiconductor film to be an active layer of the TFT was formed. Silicon was used as the material of the crystalline semiconductor film. First, in close contact with the gate insulating film 106, 20
Amorphous silicon film with plasma CV thickness of ~ 150 nm
It was formed by a known film forming method such as a D method or a sputtering method. Although there is no particular limitation on the conditions for forming the amorphous silicon film, the impurity elements of oxygen and nitrogen contained in the film are set to 5 × 10 18 cm
It is desirable to reduce it to -3 or less. Further, since the gate insulating film and the amorphous silicon film can be formed by the same film formation method, both may be formed continuously. After forming the gate insulating film, it is possible to prevent the surface from being contaminated by not once exposing it to the air atmosphere.
And variations in threshold voltage can be reduced. Then, a crystalline silicon film 107 is formed using a known crystallization technique. For example, a laser crystallization method, a thermal crystallization method (solid phase growth method), or JP-A-7-13
The crystalline silicon film 107 may be formed by a crystallization method using a catalytic element according to the technique disclosed in Japanese Patent No. 0652.

The n-channel type T of the crystalline silicon film 107
In the region where the FT is formed, boron (B) of about 1 × 10 16 to 5 × 10 17 cm −3 is used for controlling the threshold voltage.
May be added. Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of the amorphous silicon film.

(Formation of Mask Insulating Film, Formation of n Region: FIG. 1B) Next, in order to form an LDD region of an n-channel TFT, an impurity element imparting n-type was added. First, a mask insulating film 108 made of a silicon oxide film or a silicon nitride film is formed on the surface of the crystalline silicon film 107 by one step.
It was formed to a thickness of 00 to 200 nm, typically 120 nm. After a photoresist film is formed on the entire surface, the gate electrode 1 is exposed from the back surface of the substrate 101 by an exposure method.
Photoresist films were exposed using the masks 02 to 104 as masks to form resist masks 109 to 112 on the gate electrodes. According to this method, a resist mask could be formed on the gate electrode and inside the gate electrode.

Then, an impurity element imparting an n-type is added to the crystalline silicon film thereunder via the mask insulating film 108 by an ion doping method (an ion implantation method may be used). In the technical field of semiconductors, phosphorus (P), arsenic (As), antimony (Sb), or the like is applied to the impurity element imparting n-type from the elements of Group 15 of the periodic table. Using. Impurity regions 113-1 formed
The phosphorus (P) concentration of 18 is 1 × 10 17 to 5 × 10 18 cm −3.
, And here, 5 × 10 17 c
m -3 . In this specification, the impurity regions 113 to 11
The concentration of the impurity element imparting n-type contained in 8 is represented by (n ).

(Formation of Channel Protecting Film: FIG. 1C) Next, using this resist mask, a mask insulating film 108 is formed.
Was removed by etching to form channel protective films 119 to 122. In order to etch the mask insulating film 108 with high selectivity with respect to the underlying crystalline silicon film 107, a wet etching method using a hydrofluoric acid-based solution is employed here. Needless to say, the etching may be performed by a dry etching method. For example, the insulating film 108 can be etched with CHF 3 gas. In any case, in this step, over-etching is performed so that the channel protective films 119 to 122 are formed inside the end faces of the resist masks 109 to 112.

(Formation of n + region: FIG. 2A) Next, a step of forming an impurity region functioning as a source region or a drain region in the n-channel TFT was performed. Here, resist masks 123 to 125 were formed by a normal exposure method. Then, using the resist mask, the channel protection film 122 on the capacitor wiring 105 was removed by etching. Next, the crystalline silicon film 1
Impurity regions 126 to 130 in which an impurity element imparting n-type to 07 was added were formed by ion doping (or ion implantation). The impurity regions 126 to 130 have 1 ×
What is necessary is just to set it to 10 20 -1 × 10 21 cm -3 , here 5 ×
An impurity element was contained at a concentration of 10 20 cm -3 . This concentration is referred to herein as (n + ).

(P+Formation of region: FIG. 2 (B))
Region and drain of p-channel type TFT of dynamic circuit
In order to form a p-type region, an impurity element imparting p-type
An addition step was performed. P-type in the field of semiconductor technology
Is an element belonging to Group 13 of the periodic table
From boron (B), aluminum (Al), gallium (G
a) is applied, and here, boron (B) is used.
Mask so as to be located inside on channel protection film 119
131 and the region where the n-channel TFT is formed
All were covered with resist masks 132 and 133. Soshi
And diborane (BTwoH6Ion doping method using)
The impurity regions 134 to 136 may be used.
Was formed. Impurity regions 135a, 135b, 136
a, 136b are impurity elements from the surface of the crystalline silicon film
Is added, and the boron (B) concentration in this region is set to 1.5 × 1
020~ 3 × 10 twenty onecm-3And here is 2 × 10
twenty onecm-3And In this specification, the
Pure regions 135a, 135b, 136a, and 136b
The concentration of the impurity element imparting p-type+) And table
You. On the other hand, the impurity region 134 forms the channel protective film 119.
Impurity element is added to the crystalline silicon film through
Therefore, the boron (B) concentration in this region is 1 × 1016~ 1 × 1
018cm-3It became. As used herein,
Of p-type impurity contained in the doped impurity region 134
Element concentration (p-).

As shown in FIGS. 1B and 2A,
Since phosphorus (P) is added to the impurity regions 135b and 136b in the previous step, a region in which boron (B) and phosphorus (P) are mixed is formed. ) By setting the concentration to 1.5 to 3 times that, p-type conductivity was ensured, and there was no influence on the characteristics of the TFT. In this specification, this region is referred to as an impurity region (B). Then, the impurity region (B) 135
b, 136b impurity region 1 on the channel forming region side
35a and 136a are regions containing only boron (B), and in this specification, these regions are referred to as impurity regions (A). Further, an impurity region 134 overlapping with the gate electrode 103 and overlapping with the channel protective film 120 is also formed as a region containing only boron (B), and this region is formed by LDD.
Functions as an area.

(Formation of First Interlayer Insulating Film, Step of Thermal Activation, Step of Hydrogenation: FIG. 2C) When each impurity element is selectively added to the crystalline silicon film, the crystalline silicon film is removed. Was divided into islands by etching, and a protective insulating film 137 which later became a part of the first interlayer insulating film was formed.
The protective insulating film 137 includes a silicon nitride film, a silicon oxide film,
What is necessary is just to form with a silicon nitride oxide film or the laminated film which combined those. Further, the film thickness may be 100 to 400 nm.

Thereafter, a heat treatment step was performed to activate the n-type or p-type imparting impurity elements added at the respective concentrations. This process is furnace annealing,
It can be performed by a laser annealing method, a rapid thermal annealing method (RTA method), or the like. Here, the activation step was performed by the furnace annealing method. The heat treatment is
300-650 ° C., preferably 5 in a nitrogen atmosphere
The heat treatment was performed at 00 to 550 ° C, here 525 ° C, for 4 hours. Further, heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen,
A step of hydrogenating the active layer was performed. In this step, dangling bonds in the active layer are terminated by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

The crystalline silicon film 107 serving as an active layer is
When the amorphous silicon film is formed by a crystallization method using a catalytic element, approximately 1
× 10 17 to 5 × 10 19 cm −3 of the catalytic element remained. Of course, there is no problem in completing and operating the TFT even in such a state, but it was more preferable to remove the remaining catalyst element from at least the channel formation region. One of the means for removing the catalytic element is a means utilizing the gettering action of phosphorus (P). The concentration of phosphorus (P) necessary for gettering is almost the same as that of the impurity region (n + ) formed in FIG. 2B, and the heat treatment in the activation step performed here causes the n-channel TFT and the p-type. The catalyst element could be gettered from the channel forming region of the channel type TFT to the peripheral impurity region to which phosphorus (P) was added. As a result, the concentration of the catalyst element in the channel forming region can be made 5 × 10 17 cm −3 or less, and the impurity region has a concentration of 1 × 10 18 to 5 × 10 20 cm -3
-3 catalytic element segregated.

(Formation of interlayer insulating film, formation of source / drain wiring, formation of passivation film, formation of pixel electrode: FIG. 3) After the activation step, a thickness of 500 to 1500 nm is formed on protective insulating film 137. Was formed. A laminated film including the protective insulating film 137 and the interlayer insulating film 138 was used as a first interlayer insulating film. Thereafter, contact holes reaching the source region or the drain region of each TFT are formed, and the source wirings 139 to 139 are formed.
1 and drain wirings 142 and 143 were formed. Although not shown, in this embodiment, this electrode is
nm, aluminum film containing Ti 300 nm, Ti film 1
A three-layer laminated film having a thickness of 50 nm was formed continuously by a sputtering method.

The protective insulating film 137 and the interlayer insulating film 138 may be formed of a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or the like. In any case, it is preferable to set the internal stress of the film as a compressive stress. Was.

Next, a silicon nitride film, a silicon oxide film,
Alternatively, a silicon nitride oxide film is used, and the passivation film 144 is formed to a thickness of 50 to 500 nm (typically, 100 to 300 nm).
nm). Thereafter, when hydrogenation treatment was performed in this state, favorable results were obtained for improving the characteristics of the TFT. For example, heat treatment may be performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen, or the same effect is obtained by using a plasma hydrogenation method. Note that an opening may be formed in the passivation film 144 at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed later.

Thereafter, a second interlayer insulating film 145 made of an organic resin film was formed to a thickness of about 1 μm. Applicable organic resin materials include polyimide, acrylic, polyamide, polyimide amide, and BCB (benzocyclobutene)
Etc. can be used. Here, after coating on the substrate,
It was formed by sintering at 300 ° C. using a polyimide of a type that undergoes thermal polymerization. Then, a contact hole reaching the drain wiring 143 was formed in the second interlayer insulating film 145 and the passivation film 144, and the pixel electrode 146 was provided. The pixel electrode 146 may use a transparent conductive film in the case of a transmissive liquid crystal display device, and may use a metal film in the case of a reflective liquid crystal display device. Here, in order to obtain a transmission type liquid crystal display device, an indium tin oxide (ITO) film is formed by one film.
It was formed to a thickness of 00 nm by a sputtering method. Pixel electrode 19
0 is an electrode of an adjacent pixel.

Through the above steps, the pixel TFT in the display area and the TF of the driving circuit provided around the display area are formed on the same substrate.
And T could be formed. An n-channel TFT 168 and a p-channel TFT 167 are formed in the driving circuit, so that a logic circuit based on a CMOS circuit can be formed. The pixel TFT 169 is an n-channel type T
FT, and furthermore, the capacitor wiring 105 and the semiconductor layer 166.
And the insulating film formed between them and the storage capacitor 17.
0 is connected to the pixel TFT 169.

The p-channel TFT 167 of the driving circuit is
Channel formation region 147, source regions 150a and 150
b, drain regions 151a and 151b, and LDD regions 148 and 149. The source region 150b and the drain region 151b are formed of an impurity region (B), and the boron (B) concentration in this region is 1.5 to 3 times the phosphorus (P) concentration. The source region 150a and the drain region 151a formed inside the impurity region (B), that is, on the side of the channel formation region 147, are impurity regions (A), and only boron (B) is formed at the same concentration as the impurity region (B). It is the area that includes. In addition, the gate electrode 103
Which overlaps with the channel protection film 120
The D regions 148 and 149 are also formed as regions containing only boron (B). As described above, by separating the impurity region (B) from the channel formation region, the junction formation between the channel formation region and the LDD region in contact with the channel formation region and between the LDD region and the source region or the drain region is ensured.
The characteristics of the p-channel TFT could be kept good.

The n-channel type TFT 168 of the driving circuit is
The semiconductor device includes a channel formation region 152, a source region 155, a drain region 156, and LDD regions 153 and 154. The pixel TFT 169 includes a channel forming region 1
57, 158 and a source or drain region 163
To 165 and LDD regions 159 to 162. The LDD region of the n-channel TFT of the drive circuit is provided mainly for the purpose of relaxing the high electric field near the drain to prevent the deterioration of the on-current value due to hot carrier injection. The concentration of the impurity element to be applied should be 5 × 10 17 to 5 × 10 18 cm −3 . On the other hand, the LDD region of the pixel TFT is provided for the main purpose of reducing the off-current value, and the concentration of the impurity element is determined by the L-type of the n-channel TFT of the driving circuit.
The density may be the same as the density of the DD region, but 1 /
It may be 2 to 1/10. In FIG. 3, the pixel TFT 169
Has been completed as a double gate structure, but may be a single gate structure or a multi-gate structure provided with a plurality of gate electrodes.

As described above, according to the present invention, the pixel TFT and the TFT constituting each circuit according to the specifications required by the driving circuit are provided.
Has been optimized, and the operating performance and reliability of the semiconductor device can be improved.

[Embodiment 2] An example of providing a storage capacitor connected to a pixel TFT with a structure different from that of Embodiment 1 will be described with reference to FIG. P-channel type T of drive circuit
FT167, n-channel TFT 168, and pixel T
FT169 was produced in the same manner as in Example 1. Hereinafter, differences from the first embodiment will be described.

At least on the pixel TFT, a light shielding film 171 was formed on the second interlayer insulating film 145. Light shielding film 17
Reference numeral 1 denotes a film mainly composed of one or a plurality of elements selected from Al, Ti, and Ta, which was formed to have a thickness of 100 to 300 nm and was patterned into a predetermined shape. Further, a third interlayer insulating film 172 was formed thereon using an organic resin film similarly to the second interlayer insulating film. Third interlayer insulating film 1
72 had a thickness of 0.5 to 1 μm. Then, a contact hole reaching the drain wiring 143 was formed in the third interlayer insulating film 172, the second interlayer insulating film 145, and the passivation film 144, and the pixel electrode 173 was provided. The pixel electrode 173 may be formed using a transparent conductive film in the case of a transmissive liquid crystal display device or a metal film in the case of a reflective liquid crystal display device. Here, in order to form a transmissive liquid crystal display device, an indium tin oxide (ITO) film having a thickness of 100 nm was used.
m was formed by a sputtering method. Thus, the storage capacitor 174 connected to the pixel TFT 169 is connected to the light shielding film 1.
71, the third interlayer insulating film 172, and the pixel electrode 173.

[Embodiment 3] In this embodiment, a process of forming a crystalline semiconductor film to be an active layer of the TFT shown in Embodiments 1 and 2 will be described with reference to FIGS. First, 100 to 40 substrates are placed on a substrate (a glass substrate in this embodiment) 1101.
Gate electrodes 1102 and 1103 having a thickness of 0 nm are formed. The gate electrode is formed from a material containing one or more kinds of elements selected from Al, Ti, Ta, Mo, and W, and is patterned so that an end face is tapered. Although not shown, a laminated structure of the above materials may be used. For example, tantalum nitride (TaN) and Ta
It may be a two-layer structure. Further, the surface of the gate electrode may be coated with an oxide by an anodic oxidation method or the like.
The gate insulating film 1104 is formed using a silicon nitride film, a silicon oxide film, or a silicon oxynitride film, and has a thickness of 20
To 200 nm, preferably 75 to 125 nm. Then, an amorphous semiconductor film (amorphous silicon film in this embodiment) 110 having a thickness of 50 nm is formed on the gate insulating film 1104.
5 is continuously formed without opening to the atmosphere.

Next, an aqueous solution (aqueous nickel acetate solution) containing 10 ppm by weight of a catalytic element (nickel in this embodiment) is applied by spin coating to form a catalytic element-containing layer 1106 on the amorphous semiconductor film 1105. Formed over the entire surface.
The catalyst elements usable here are germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), and cobalt (C) in addition to nickel (Ni).
o), platinum (Pt), copper (Cu), and gold (Au). In this embodiment, a method of adding nickel by a spin coating method is used. However, a thin film made of a catalytic element (a nickel film in this embodiment) is formed on an amorphous semiconductor film by a vapor deposition method, a sputtering method, or the like. Means for forming may be taken. (FIG. 5 (A))

Next, before crystallization, at 400 to 500 ° C., 1
After performing a heat treatment process for about an hour to desorb hydrogen from the film, the temperature is 500 to 650 ° C. (preferably 550 to 570 ° C.).
C.) for 4 to 12 hours (preferably 4 to 6 hours). In this embodiment, a heat treatment is performed at 550 ° C. for 4 hours to form a crystalline semiconductor film (a crystalline silicon film in this embodiment).
1107 is formed. (Fig. 5 (B))

The active layer 110 formed as described above
7 is a catalytic element that promotes crystallization (here, nickel)
By using, a crystalline semiconductor film having excellent crystallinity can be formed. Further, in order to further enhance the crystallinity, a laser crystallization method may be used in combination. For example, a linear beam is formed using XeF excimer laser light (wavelength 308 nm), and the oscillation frequency is 5 to 50 Hz.
The crystalline semiconductor film 1107 manufactured in FIG. 5B was irradiated with an energy density of 100 to 500 mJ / cm 2 and an overlap ratio of the linear beam of 80 to 98%. As a result, the crystalline semiconductor film 1 having more excellent crystallinity
108 could be formed. (FIG. 5 (C))

By using the crystalline semiconductor film formed on the substrate 1101 as described above, TFTs are manufactured according to the procedure shown in Embodiments 1 and 2, and good characteristics can be obtained. The characteristics of a TFT can be typically represented by a field-effect mobility, and the characteristics of a TFT formed from a crystalline semiconductor film manufactured as in this embodiment are n-channel TFTs.
150~220cm 2 / V · sec in FT, a p-channel type TFT 90~120cm 2 / V · sec can be obtained,
Moreover, even when the device was continuously operated, almost no deterioration in characteristics from the initial value was observed, and excellent characteristics were obtained from the viewpoint of reliability.

[Embodiment 4] In this embodiment, another configuration of the storage capacitor connected to the pixel TFT will be described with reference to FIGS. Here, the manufacturing steps in FIGS. 6 and 7 are the same up to the point where the second interlayer insulating film 145 made of an organic resin film is formed in accordance with the manufacturing steps described in Embodiment 1, and the structure up to that point is the same. This has already been described with reference to FIGS. Therefore, in the present embodiment, description will be made focusing on only the differences from the first embodiment.

Referring to FIG. 6A, first, when the second interlayer insulating film 145 is formed according to the steps of the first embodiment, Al,
Light shielding film 301 made of a material containing an element selected from Ta and Ti
To form Then, 30 to 150 nm (preferably 50 to 75 nm) is formed on the surface of the light shielding film 301 by an anodic oxidation method.
The dielectric film 302 (the oxide of the material forming the light-shielding film) is formed.

When forming the dielectric film 302 by the anodic oxidation method, first, an ethylene glycol tartrate solution having a sufficiently low alkali ion concentration was prepared. It consists of a 15% aqueous solution of ammonium tartrate and ethylene glycol:
It is a solution mixed in 8, ammonia water is added to this,
The pH was adjusted to be 7 ± 0.5. Then, a platinum electrode serving as a cathode was provided in the solution, the substrate on which the light-shielding film 301 was formed was immersed in the solution, and a constant (several mA to several tens mA) DC current was passed using the light-shielding film 301 as an anode. .
The voltage between the cathode and the anode in the solution changes with time as the oxide grows.However, the voltage is adjusted so that the current becomes constant, and the voltage is not maintained when the voltage reaches 150 V, or the voltage is maintained. The holding time was set to several seconds to several tens of seconds to terminate the anodizing treatment. By doing so, the light-shielding film 301 can be formed without going around the dielectric film up to the surface in contact with the second interlayer insulating film.

In this embodiment, the dielectric film is provided only on the surface of the light-shielding film.
It may be formed by a gas phase method such as a D method or a sputtering method. Also in that case, the film thickness is preferably 30 to 150 nm (preferably 50 to 75 nm). Also, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, DL
A C (Diamond like carbon) film or an organic resin film may be used. Further, a stacked film combining these may be used.

Thereafter, the pixel electrode 303 is formed in the same manner as in the first embodiment.
To form Thus, the light shielding film 301 and the pixel electrode 303
In the region where the storage capacitor 30 overlaps with the dielectric film 302 interposed therebetween.
4 are formed.

In the structure shown in FIG. 6B, a light-shielding film 301 and a dielectric film 302 are formed in the same manner as in FIG. 6A, and then a spacer 305 made of an organic resin is formed. As the organic resin film, a film selected from polyimide, polyamide, polyimide amide, acrylic, and BCB (benzocyclobutene) can be used. Then, the spacer 305, the second
Then, the interlayer insulating film 145 and the passivation film 143 are etched to form contact holes, and the pixel electrode 306 is formed using the same material as in the first embodiment. Thus, a storage capacitor 307 is formed in a region where the light shielding film 301 and the pixel electrode 306 overlap with the dielectric film 302 interposed therebetween. By providing the spacer 305 in this manner, the light shielding film 30 can be formed.
Short-circuit (short-circuit) generated between the pixel electrode 306 and the pixel electrode 306
Can be prevented.

In the structure of FIG. 6C, a light-shielding film 301 is formed as in FIG. 6A, and a spacer 308 made of an organic resin is formed so as to cover an end of the light-shielding film 301. As the organic resin, a film selected from polyimide, polyamide, polyimide amide, acrylic, and BCB (benzocyclobutene) can be used. Next, a dielectric film 309 is formed on the exposed surface of the light shielding film 301 by an anodic oxidation method. Note that a dielectric film is not formed in a portion in contact with the spacer 308. Then, the spacer 308, the second
The interlayer insulating film 145 and the passivation film 143 are etched to form a contact hole, and the pixel electrode 310 is formed using the same material as in the first embodiment. Thus, a storage capacitor 311 is formed in a region where the light shielding film 301 and the pixel electrode 310 overlap with the dielectric film 309 interposed therebetween. By providing the spacer 308 in this manner, the light shielding film 30 can be formed.
Short-circuit (short-circuit) occurring between the pixel electrode 310 and the pixel electrode 310
Can be prevented.

In FIG. 7A, first, after a second interlayer insulating film 145 is formed according to the steps of the first embodiment, an insulating film 312 of a material such as a silicon nitride film, a silicon oxide film or a silicon nitride oxide film is formed thereon. To form Insulating film 312
Is formed by a known film forming method, and among them, the sputtering method is preferably used. Thereafter, a light-shielding film, a dielectric film, and a pixel electrode are formed and a storage capacitor 313 is provided in the same manner as in FIG. The provision of the insulating film 312 improves the adhesion of the light-shielding film to the base, and prevents the dielectric film from forming around the interface with the base of the light-shielding film when forming the dielectric film by anodic oxidation. it can.

In FIG. 7B, after an insulating film and a light-shielding film are similarly formed, a region of the insulating film which is not in close contact with the light-shielding film is removed by etching, so that the insulating film 314 overlaps the light-shielding film.
Was formed. Then, a pixel electrode 315 was provided. With such a configuration, the adhesion of the light-shielding film to the base is improved, and when the dielectric film is formed by the anodic oxidation method, the wraparound of the dielectric film at the interface with the base of the light-shielding film is prevented. In addition, the light transmittance of the pixel region where the light shielding film is formed can be improved.

The configuration shown in FIGS. 7A and 7B is the same as that shown in FIG.
It is also possible to combine with the structure of providing the spacer shown in (B) and (C). Further, the configuration of the present embodiment shown in FIGS. 6 and 7 can be combined with the configuration of the first embodiment or the second embodiment.

[Fifth Embodiment] Fabrication of a semiconductor device in which pixel TFTs formed in a display area and TFTs of a driving circuit provided around the display area described in the first and second embodiments are provided on the same substrate. In the method, a crystalline semiconductor film as an active layer, an insulating film such as a gate insulating film or an interlayer insulating film and a base film, and a conductive film such as a gate electrode, a source wiring, a drain wiring, and a pixel electrode are all formed by sputtering. Can be made. An advantage of using a sputtering method is that a DC (direct current) discharge method can be employed in forming a conductive film or the like, and thus it is suitable for forming a uniform film on a large-area substrate. In addition, it is not necessary to use silane (SiH4) which requires great care in handling to form a silicon-based material such as an amorphous silicon film or a silicon nitride film,
Work safety is ensured. Such a point can be utilized as a very merit particularly in a production site. Hereinafter, a manufacturing process using a sputtering method will be described according to the first embodiment.

The gate electrodes 102 to 104 and the capacitor wiring 105 shown in FIG. 1A can be easily formed by a known sputtering method using a target material such as Ta, Ti, W, and Mo. W
When a compound material such as -Mo or Ta-Mo is used,
Similarly, a compound target may be used. Also, Ta
When forming N or WN, nitrogen (N 2 ) or ammonia (NH 3 ) in addition to argon (Ar) is used in the sputtering atmosphere.
Can be produced by appropriately adding In addition, there is a method in which helium (He), krypton (Kr), and xenon (Xe) are added to a sputtering gas in addition to Ar to control the internal stress of a film to be formed.

Silicon nitride used for gate insulating film 106
The film 106a is formed by using a silicon (Si) target.
r, NTwo, Hydrogen (HTwo), NHThreeIf properly mixed with the formation
Wear. Alternatively, using a silicon nitride target material
It can be formed similarly. Silicon nitride oxide film 10
6b, using a Si target, Ar, NTwo, HTwo, N Two
It is prepared by appropriately mixing O and sputtering.

Similarly, an amorphous silicon film is produced by using a Si target and using Ar and H 2 as a sputtering gas.
If a small amount of boron (B) is to be added to the amorphous silicon film, several tens ppm
Boron (B) of up to several thousand ppm may be added, or diborane (B 2 H 6 ) may be added to the sputtering gas.

A silicon oxide film applicable to the channel protective films 119 to 122 can be formed by sputtering with Ar or a mixed gas of Ar and oxygen (O 2) using silicon oxide (or quartz) as a target material. Protective insulating film 137, interlayer insulating film 138, passivation film 14
The silicon nitride film, silicon oxide film, and silicon nitride oxide film used for 4 may be formed as described above.

In the case where Al is used for the source wirings 139 to 141 and the drain wirings 142 and 143, T
i, Si, scandium (Sc), vanadium (V),
When Cu or the like is contained in an amount of about 0.01 to 5% by weight, hillocks are effectively prevented. Ti used for the light shielding film 171,
Ta, Al, etc., ITO, Zn used for the pixel electrode 146
O, SnO 2 and the like may be formed by a known sputtering method.

As described above, any film other than the second interlayer insulating film 145 and the third interlayer insulating film 172 made of an organic resin can be formed by the sputtering method. The detailed experimental conditions may be appropriately determined by the practitioner.

[Embodiment 6] This embodiment shows a pixel TFT and a TFT of a driving circuit, particularly another example of a p-channel TFT. First, the steps from FIG. 1A to FIG. 2A described in the first embodiment are performed in the same manner.
FIG. 12A is a diagram corresponding to FIG. 2A, and shows a state in which resist masks 1123 to 1125 and impurity regions 1126 to 1130 to which an impurity element imparting n-type is added are formed.

Then, ap + region is formed as shown in FIG. A mask 1131 is formed so as to be located inside the channel protective film 1119, and an n-channel type T
All regions where the FT is to be formed are resist masks 1132,
Covered with 1133. Further, the channel protective film 1119 is etched by a wet etching method using a hydrofluoric acid-based solution so that the end portion of the channel protective film 1119 substantially coincides with the end portion of the mask 1131.
9b was formed. Then, to form a high-concentration impurity regions 1134 to 1,136 in diborane (B 2 H 6) Ion doping using (or by ion implantation). In the impurity regions 1134 to 1136, an impurity element is added from the surface of the crystalline silicon film, and the boron (B) concentration in this region is set to a range of 1.5 × 10 20 to 3 × 10 21 cm −3. It was set to 10 21 cm -3 . In this specification, the concentration of the impurity element imparting p-type contained in the impurity regions 1134 to 1136 formed here is expressed as (p + ). In this manner, by providing the end of the high-concentration impurity region of the p-channel TFT in contact with the channel formation region, closer to the channel formation region than the end of the low-concentration impurity regions 1113 and 1114 formed in the previous step. The joining state at this portion can be improved.

As shown in FIGS. 1B and 2A,
Since phosphorus (P) is added to the impurity regions 1135 and 1136 in the previous step, a region in which boron (B) and phosphorus (P) are mixed is formed. ) By setting the concentration to 1.5 to 3 times that, p-type conductivity was ensured, and there was no influence on the characteristics of the TFT. In this specification, this region is referred to as a region (B). The impurity region 134 on the channel formation region side is a region containing only boron (B), and is referred to as a region (A) in this specification.

After the respective impurity elements are selectively added to the crystalline silicon film, the crystalline silicon film is etched to be divided into islands, and a protective insulating film 1137 which will later become a part of the first interlayer insulating film. Was formed. Protective insulating film 113
7 may be formed of a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a stacked film combining these. Further, the film thickness may be 100 to 400 nm.

Thereafter, a heat treatment step was performed to activate the n-type or p-type imparting impurity element added at each concentration. When the activation is performed by the furnace annealing method, the activation is performed at 300 to 650 ° C. in a nitrogen atmosphere.
The heat treatment was preferably performed at 500 to 550 ° C, here 525 ° C, for 4 hours. When the laser annealing method is applied, an excimer laser is used as a light source, and the laser light is converted into a linear beam by an optical system with a line width of 100 to 500 μm, an oscillation frequency of 10 to 100 Hz, and an oscillation pulse width of 20 to
Irradiation is performed at 50 nsec (preferably 30 nsec) at an energy density of 100 to 500 mJ / cm2. further,
300 to 450 in an atmosphere containing 3 to 100% hydrogen.
A heat treatment was performed at a temperature of 1 to 12 hours to hydrogenate the active layer. In this step, dangling bonds in the active layer are terminated by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

After the activation step, the protective insulating film 113
7, an interlayer insulating film 11 having a thickness of 500 to 1500 nm
38 was formed. A laminated film including the protective insulating film 1137 and the interlayer insulating film 1138 was used as a first interlayer insulating film. Thereafter, a contact hole reaching the source region or the drain region of each TFT is formed, and the source wiring 1 is formed.
139 to 1141, and drain wirings 1142 and 1143
Was formed. Although not shown, in this embodiment, this electrode is formed of a Ti film having a thickness of 100 nm and a Ti-containing aluminum film 3.
A three-layer laminated film was formed by continuously forming a Ti film of 00 nm and a Ti film of 150 nm by a sputtering method.

Protective insulating film 1137 and interlayer insulating film 1138
What is necessary is just to form a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or the like. In any case, it is preferable to set the internal stress of the film as a compressive stress.

Next, a silicon nitride film, a silicon oxide film,
Alternatively, a silicon nitride oxide film is used, and the passivation film 1144 is formed to a thickness of 50 to 500 nm (typically, 100 to 30 nm).
0 nm). Thereafter, when hydrogenation treatment was performed in this state, favorable results were obtained for improving the characteristics of the TFT. For example, heat treatment may be performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen, or the same effect is obtained by using a plasma hydrogenation method. Note that an opening may be formed in the passivation film 1144 at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed later.

Thereafter, a second interlayer insulating film 1145 made of an organic resin film was formed to a thickness of about 1 μm as in Example 1. Then, a contact hole reaching the drain wiring 1143 was formed in the second interlayer insulating film 1145 and the passivation film 1144, and a pixel electrode 1146 was provided. The pixel electrode 1146 may be formed using a transparent conductive film in the case of a transmissive liquid crystal display device or a metal film in the case of a reflective liquid crystal display device. Here, an indium tin oxide (ITO) film was formed to a thickness of 100 nm by a sputtering method in order to obtain a transmission type liquid crystal display device. Pixel electrode 1
Reference numeral 190 denotes an electrode of an adjacent pixel.

Through the above steps, the pixel TFT in the display area and the TF of the driving circuit provided around the display area are formed on the same substrate.
And T could be formed. An n-channel TFT 1168 and a p-channel TFT 1167 are formed in the driver circuit, so that a logic circuit based on a CMOS circuit can be formed. The pixel TFT 1169 is an n-channel TFT, and further includes a capacitor wiring 105 and a semiconductor layer 1.
The storage capacitor 1170 is connected to the pixel TFT 1169 from 166 and the insulating film formed therebetween.

P-channel TFT 1167 of drive circuit
Has a channel formation region 1147, source regions 1148 and 1150 formed of high-concentration impurity regions, and drain regions 1149 and 1151. Source area 11
50 and the drain region 1151 are formed in the region (B),
The boron (B) concentration in this region is 1.5 times the phosphorus (P) concentration.
Up to 3 times. Source region 1 formed inside impurity region (B), that is, on the side of channel formation region 1147
The region 148 and the drain region 1149 are the region (A) and are regions containing only boron (B) at the same concentration as the region (B). The entire region (A) overlaps with the gate electrode 1103, while the region (B) partially overlaps with the gate electrode 1103. Thus, the p-channel type T
By forming the high concentration impurity region of the FT from the region (B) and the region (A), and keeping the region (B) away from the channel formation region, the junction between the channel formation region and the high concentration impurity region is improved. can do.

N-channel TFT 1168 of drive circuit
Represents a channel formation region 1152 and a source region 1155
And the drain region 1156, the LDD region 1153,
1154. The pixel TFT 1169 includes channel forming regions 1157 and 1158, source or drain regions 1163 to 1165, and an LDD region 11.
59 to 1162. The LDD region of the n-channel TFT of the drive circuit is provided mainly for the purpose of relaxing the high electric field near the drain to prevent the deterioration of the on-current value due to hot carrier injection. The concentration of the impurity element to be provided is 5 × 10 17 to 5
It should have been × 10 18 cm -3 . On the other hand, the LDD region of the pixel TFT is provided for the main purpose of reducing the off current value, and the concentration of the impurity element may be the same as the concentration of the LDD region of the n-channel TFT of the driving circuit. , The concentration may be 2〜 to 1/10. In FIG. 3, the pixel TFT 1169 is completed as a double gate structure, but may be a single gate structure or a multi-gate structure provided with a plurality of gate electrodes.

The TFT manufactured by the above steps
Are channel protection insulating films 1119b, 1120 to 112
2 is formed without being damaged by the ion doping method or the like, so that the characteristics of the TFT can be stabilized. For example, bias / heat stress (BT
S) As a test, even if a voltage of -1.7 MV is applied to the gate electrode and left at 150 ° C. for 1 hour, the threshold voltage, the field effect mobility, the subthreshold constant, the on-current value, etc. Fluctuations are rarely observed. Further, according to the present invention, it is possible to optimize the structure of the TFT constituting each circuit according to the specifications required by the pixel TFT and the driving circuit, and to improve the operation performance and reliability of the semiconductor device.

The structure of the storage capacitor shown in FIG. 13 includes a light-shielding film and a dielectric layer formed on the surface thereof by anodic oxidation as described in Embodiment 4 with reference to FIGS.
It may be formed from a pixel electrode.

[Embodiment 7] In this embodiment, a process for manufacturing an active matrix liquid crystal display device from a substrate on which pixel TFTs and a driving circuit are formed will be described. As shown in FIG. 8, an alignment film 601 is formed on the substrate in the state shown in FIG. Usually, a polyimide resin is often used for an alignment film of a liquid crystal display element. Opposite substrate 6
In 02, a light-shielding film 603, a transparent conductive film 604, and an alignment film 605 are formed. After forming the alignment film, a rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. Then, the one substrate on which the pixel TFT and the driving circuit are formed and the opposite substrate are bonded to each other via a sealing material or a spacer (both not shown) by a known cell assembling process. Thereafter, a liquid crystal material 606 was injected between the two substrates, and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material.
Thus, the active matrix type liquid crystal display device shown in FIG. 8 is completed.

Next, the structure of the active matrix type liquid crystal display device will be described with reference to the perspective view of FIG. 9 and the top view of FIG. 9 and 10 correspond to FIGS. 1 to 3 and FIG.
In order to correspond to the cross-sectional structure diagram of FIG. The cross-sectional structure along AA ′ shown in FIG.
This corresponds to the cross-sectional view of the pixel TFT 169 and the storage capacitor 170 shown in FIG.

The perspective view shown in FIG. 9 includes a display area 701, a scanning (gate) line driving circuit 702, and a signal (source) line driving circuit 703 formed on the glass substrate 101. A pixel TFT 169 is provided in the display area, and a driving circuit provided in the periphery of the display area is configured based on a CMOS circuit. Scanning (gate) line drive circuit 7
02 and a signal (source) line driver circuit 703 are connected to the gate wiring 104 (connected to the gate electrode and represented by the same reference numerals in the sense that they extend and are formed) and the source wiring 141, respectively.
Are connected to the pixel TFTs in the display area 701. Further, the FPC 731 is connected to the external input / output terminal 734.

FIG. 10 is a top view showing almost one pixel in the display area 701. FIG. The gate wiring 104 intersects an active layer therebelow via a gate insulating film (not shown). Although not shown, an LDD region including a source region, a drain region, and an n region is formed in the active layer. Reference numeral 180 denotes a source wiring 141 and a source region 16.
3, 181 is a contact portion between the drain wiring 143 and the drain region 165, and 182 is a contact portion between the drain wiring 143 and the pixel electrode 146. The storage capacitor 170 is connected to the drain region 16 of the pixel TFT 169.
5 is formed in a region where the semiconductor layer 166 connected to the capacitor wiring 105, the capacitor wiring 105, and the insulating film formed therebetween overlap.

Although the active matrix type liquid crystal display device of this embodiment has been described with reference to the structure described in the first embodiment, the active matrix type liquid crystal display device can be freely combined with any of the configurations of the first to sixth embodiments. A display device can be manufactured.

[Embodiment 8] A substrate in which pixel TFTs and a driving circuit manufactured by carrying out the present invention are integrally formed on the same substrate can be used in various electro-optical devices (active matrix type liquid crystal display devices, active matrix type EL display device, active matrix type EC display device). That is, the present invention can be applied to all electronic devices incorporating these electro-optical devices as display media.

Examples of such electronic devices include a video camera, a digital camera, a projector (rear or front type), a head mounted display (goggle type display), a car navigation system, a personal computer, a mobile phone, and an electronic book. Can be One example of them is shown in FIG.

FIG. 11A shows a mobile phone,
01, audio output unit 9002, audio input unit 9003, display device 9004, operation switch 9005, antenna 900
6. The present invention is an audio output unit 900
2. The present invention can be applied to an active matrix display device 9004 including a sound input portion 9003 and a display region and a driver circuit in the periphery thereof.

FIG. 11B shows a video camera, which includes a main body 9101, a display device 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 91.
06. The present invention provides a voice input unit 9103,
And an active matrix type display device 9102 having a driving circuit in and around a display area and an image receiving portion 9106
Can be applied to

FIG. 11C shows a mobile computer, which includes a main body 9201, a camera section 9202, and an image receiving section 920.
3, an operation switch 9204, and a display device 9205. The present invention can be applied to the image receiving portion 9203 and an active matrix display device 9205 including a display region and a driver circuit in the periphery thereof.

FIG. 11D shows a goggle type display, which includes a main body 9301, a display device 9302, and an arm 93.
03. The present invention can be applied to an active matrix display device 9302 including a display region and a driver circuit in the periphery thereof. Although not shown, it can be used for other signal control circuits.

FIG. 11E shows a rear type projector, which includes a main body 9401, a light source 9402, a display device 9403,
Polarizing beam splitter 9404, reflector 940
5, 9406 and a screen 9407. The present invention can be applied to an active matrix display device 9403 including a display region and a driver circuit in the periphery thereof.

FIG. 11F shows a portable book, and a main body 95.
01, display devices 9502 and 9503, storage medium 950
4. It comprises an operation switch 9505 and an antenna 9506, and displays data stored on a mini disk (MD) or digital video disk (DVD) or data received by the antenna. Display device 950
Reference numeral 29503 denotes an active matrix type direct-view display device including a display region and a driving circuit in the periphery thereof;
The present invention can be applied to this.

Although not shown here, the present invention is also applicable to a car navigation system and a display unit of an image sensor personal computer. As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields. Further, the electronic apparatus of the present embodiment can be realized by using a configuration composed of any combination of the first to seventh embodiments.

[0098]

According to the present invention, in a semiconductor device in which a plurality of functional circuits are formed on the same substrate (specifically, an electro-optical device in this case) according to specifications required by the functional circuits. It is possible to arrange TFTs having appropriate performance, and the operating characteristics and reliability thereof can be greatly improved.

In particular, in a bottom gate type or inverted stagger type TFT provided with an LDD region, the off current value can be greatly reduced by forming the LDD region of the pixel TFT with n concentration and Loff, This can contribute to lower power consumption of the pixel TFT. Further, an LDD region of the n-channel TFT of the driver circuit n - concentration at and Lov +
By forming Loff, current driving capability can be increased, deterioration due to hot carriers can be prevented, and deterioration of the on-current value can be reduced.

Further, in the p-channel TFT of the driver circuit, an impurity region (B) containing both an impurity element imparting p-type and an impurity element imparting n-type, and an impurity element imparting p-type are included. An impurity region (A), and the impurity region (A) is formed between the impurity region (A) and the LDD region of the p-channel TFT of the driver circuit, so that a channel formation region is formed. And the LDD region in contact therewith, as well as the junction between the LDD region and the source region or the drain region can be reliably formed, and the characteristics of the p-channel TFT can be kept good.

Further, a semiconductor device having such an electro-optical device as a display medium (specifically, electronic equipment in this case)
Operating performance and reliability can also be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 2 is a diagram illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 3 is a diagram illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 4 is a diagram illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 5 illustrates a manufacturing process of a crystalline semiconductor film.

FIG. 6 illustrates an example of a cross-sectional structure of a storage capacitor.

FIG. 7 illustrates an example of a cross-sectional structure of a storage capacitor.

FIG. 8 is a diagram showing a cross-sectional structure of an active matrix liquid crystal display device.

FIG. 9 is a perspective view of an active matrix liquid crystal display device.

FIG. 10 is a top view of a pixel.

FIG. 11 illustrates an example of a semiconductor device.

FIG. 12 is a diagram illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 13 is a diagram illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Substrate 102-104 Gate electrode 105 Capacitance wiring 106 Gate insulating film 107 Crystalline silicon film 108 Mask insulating film 119-121 Channel protective film 139-141 Source electrode 142-143 Drain electrode 137 Protective insulating film 138 Interlayer insulating film 144 Passivation film 145 second interlayer insulating film 146 pixel electrode

Continued on the front page F term (reference) 2H092 GA29 JA26 JA34 JA37 JA46 JB22 JB31 JB51 JB57 JB69 KA04 KA10 KB24 KB25 MA08 MA10 MA15 MA19 MA27 MA29 MA30 NA25 NA26 PA03 RA05 5C094 AA13 BA03 BA43 EA04 EA07 EB05 A04 BB05 A04 DDB DD03 DD13 DD14 DD15 EE01 EE03 EE04 EE06 EE14 EE23 EE28 EE29 EE34 EE43 EE44 EE48 FF02 FF03 FF04 FF09 FF28 FF30 FF35 GG02 GG13 GG07 GG32 GG13 GG13 GG13 GG12 NN12 NN22 NN23 NN24 NN27 NN34 NN36 NN41 NN42 NN44 NN46 NN47 NN54 NN58 NN72 NN78 PP02 PP03 PP04 PP06 PP10 PP34 PP35 QQ09 QQ12 QQ24 QQ25 QQ28 5G435 AA14 AA16 AA17 CC09 KK05 KK09

Claims (16)

[Claims]
1. A semiconductor device comprising: a pixel TFT provided in a display region; and an n-channel TFT and a p-channel TFT of a driving circuit provided around the display region on the same substrate. Each of the channel type TFT and the p-channel type TFT includes an active layer, an LDD region provided in the active layer, a gate insulating film provided between the active layer and the substrate, A gate electrode provided between the substrate and a substrate, wherein an LDD region of the pixel TFT and the n-channel TFT is disposed so as to at least partially overlap the gate electrode, and a p-channel TFT of the drive circuit is provided. Wherein the LDD region is disposed so as to entirely overlap the gate electrode.
2. A semiconductor device comprising: a pixel TFT provided in a display region; and an n-channel TFT and a p-channel TFT of a driving circuit provided in the periphery of the display region on the same substrate. TFT and p-channel TFT
Each of the FTs has an active layer and an L provided on the active layer.
A DD region, a protective insulating film provided on the active layer, a gate insulating film provided between the active layer and the substrate, and a gate electrode provided between the gate insulating film and the substrate. And the LDD regions of the pixel TFT and the n-channel TFT do not overlap with the protective insulating film and are arranged so as to at least partially overlap with the gate electrode. A semiconductor device, wherein an LDD region of a TFT is arranged so as to overlap with the protective insulating film and to entirely overlap with the gate electrode.
3. The p-channel TFT of claim 1, wherein the p-channel TFT of the driving circuit includes an impurity region (A) containing both an impurity element imparting p-type and an impurity element imparting n-type. , An impurity region (B) containing an impurity element imparting p-type conductivity, wherein the impurity region (B) is located between the impurity region (A) and the LDD region of the p-channel TFT of the driving circuit. A semiconductor device characterized by being formed.
4. The storage capacitor according to claim 1, wherein the storage capacitor connected to the pixel TFT includes a capacitor wiring formed on the substrate, an insulating film formed on the capacitor wiring, and the insulating film. And a semiconductor layer formed on the semiconductor layer.
5. The light-emitting device according to claim 1, wherein an organic resin film is formed on at least the pixel TFT, and a light-shielding film formed on the organic resin film is formed in close contact with the light-shielding film. From the dielectric film and the pixel electrode that is provided so as to partially overlap the light-shielding film and that is connected to the pixel TFT.
A semiconductor device comprising a capacitor.
6. The light-shielding film according to claim 5, wherein the light-shielding film is made of a material containing one or more kinds selected from aluminum, tantalum, and titanium, and the dielectric film is an oxide of a material forming the light-shielding film. A semiconductor device comprising:
7. The semiconductor device according to claim 1, wherein the semiconductor device is a mobile phone, a video camera, a mobile computer, a goggle type display, a projector, a mobile book, a digital camera, a car navigation, a personal computer. A semiconductor device, which is one selected from the group consisting of:
8. A method for manufacturing a semiconductor device having a pixel TFT provided in a display region and an n-channel TFT and a p-channel TFT of a driver circuit provided around the display region on the same substrate, N-channel TFT between pixel TFT and the driving circuit
Forming a LDD region that at least partially overlaps with the gate electrode of the semiconductor device, and forming an LDD region that entirely overlaps with the gate electrode of the p-channel TFT of the drive circuit. Method.
9. A method for manufacturing a semiconductor device having a pixel TFT provided in a display region and an n-channel TFT and a p-channel TFT of a driver circuit provided around the display region on the same substrate. Forming an LDD region that does not overlap the pixel TFT and the channel protection insulating film of the n-channel TFT of the drive circuit and at least partially overlaps the gate electrode; and channel protection of the p-channel TFT of the drive circuit. Forming an LDD region which overlaps with the insulating film and which overlaps with the gate electrode entirely.
10. The p-channel TFT according to claim 8, wherein the p-channel TFT of the driving circuit includes an impurity region (A) containing both an impurity element imparting p-type and an impurity element imparting n-type. Forming an impurity region (B) containing an impurity element imparting p-type conductivity. The impurity region (B) is formed of the impurity region (A) and the LDD region of a p-channel TFT of the driving circuit. And a method for manufacturing a semiconductor device.
11. A pixel TFT provided in a display region, and an n-channel TFT and a p-type TFT of a driving circuit provided around the display region.
In a method for manufacturing a semiconductor device having a channel type TFT on the same substrate, a first step of forming a gate electrode on the substrate, a second step of forming a gate insulating film on the gate electrode, A third step of forming a first semiconductor layer and a second semiconductor layer on a gate insulating film, a fourth step of forming a channel protective film on the first and second semiconductor layers, A fifth step of introducing an impurity element imparting n-type into the first semiconductor layer to form an LDD region of an n-channel TFT which does not overlap with the channel protective film; A sixth step of forming a source region or a drain region of an n-channel TFT by introducing an impurity element for imparting a type, and introducing an impurity element for imparting a p-type to the second semiconductor layer. Heavy on the channel protective film P-channel type TF
A method for manufacturing a semiconductor device, comprising: a seventh step of forming an LDD region of T and a source region or a drain region.
12. The method according to claim 8, wherein a step of forming a capacitor wiring on the substrate, a step of forming an insulating layer on the capacitor wiring, and a step of forming a semiconductor on the insulating layer are performed. A method for manufacturing a semiconductor device, comprising: a step of forming a layer; and a step of forming a storage capacitor connected to the pixel TFT.
13. The method according to claim 8, wherein an organic resin layer is formed on the pixel TFT, a light shielding film is formed on the organic resin, and Forming a capacitor from a step of closely forming a dielectric film and a step of forming a pixel electrode provided so as to partially overlap the light-shielding film and connected to the pixel TFT; Production method.
14. The light-shielding film according to claim 13, wherein the light-shielding film is formed of a material containing one or more kinds selected from aluminum, tantalum, and titanium, and the dielectric film is formed by oxidizing a material forming the light-shielding film. A method for manufacturing a semiconductor device, comprising forming an object.
15. The method according to claim 14, wherein the dielectric film is formed by an anodic oxidation method.
16. The semiconductor device according to claim 8, wherein the semiconductor device is a mobile phone, a video camera, a mobile computer, a goggle type display,
A method for manufacturing a semiconductor device, which is one selected from a projector, a portable book, a digital camera, a car navigation, and a personal computer.
JP2000101787A 1999-04-06 2000-04-04 Method for manufacturing semiconductor device Expired - Fee Related JP4651773B2 (en)

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JPH1174535A (en) * 1997-08-29 1999-03-16 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacture

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JP2013174885A (en) * 1999-04-06 2013-09-05 Semiconductor Energy Lab Co Ltd Liquid crystal display device
JP2001007343A (en) * 1999-04-20 2001-01-12 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacture
KR100915148B1 (en) * 2003-03-07 2009-09-03 엘지디스플레이 주식회사 Method for fabricating switching and driving device for liquid crystal display device with driving circuit
KR100924493B1 (en) * 2003-06-27 2009-11-03 엘지디스플레이 주식회사 Method of fabricating an array substrate for Liquid Crystal Display Device with driving circuit
US7859187B2 (en) 2003-11-14 2010-12-28 Semiconductor Energy Laboratory Co., Ltd. Display device and method for fabricating the same
JP2005190992A (en) * 2003-11-14 2005-07-14 Semiconductor Energy Lab Co Ltd Display device and its fabrication method
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JP2006054416A (en) * 2004-08-13 2006-02-23 Samsung Sdi Co Ltd Thin film transistor and manufacturing method therefor
JP4558476B2 (en) * 2004-08-13 2010-10-06 三星モバイルディスプレイ株式會社 Thin film transistor manufacturing method
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JP2007164183A (en) * 2005-12-09 2007-06-28 Samsung Sdi Co Ltd Flat panel display and method of fabricating the same
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JP2015092620A (en) * 2011-02-02 2015-05-14 株式会社半導体エネルギー研究所 Semiconductor device
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JP2016219802A (en) * 2015-05-14 2016-12-22 エルジー ディスプレイ カンパニー リミテッド Thin film transistor and backplane substrate of display device including the same

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