KR100915148B1 - Method for fabricating switching and driving device for liquid crystal display device with driving circuit - Google Patents

Method for fabricating switching and driving device for liquid crystal display device with driving circuit

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Publication number
KR100915148B1
KR100915148B1 KR1020030014492A KR20030014492A KR100915148B1 KR 100915148 B1 KR100915148 B1 KR 100915148B1 KR 1020030014492 A KR1020030014492 A KR 1020030014492A KR 20030014492 A KR20030014492 A KR 20030014492A KR 100915148 B1 KR100915148 B1 KR 100915148B1
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South Korea
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layer
formed
driving circuit
liquid crystal
polysilicon
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KR1020030014492A
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Korean (ko)
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KR20040079564A (en
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양준영
유상희
오금미
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엘지디스플레이 주식회사
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Publication of KR20040079564A publication Critical patent/KR20040079564A/en
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Publication of KR100915148B1 publication Critical patent/KR100915148B1/en

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    • EFIXED CONSTRUCTIONS
    • E04BUILDING
    • E04HBUILDINGS OR LIKE STRUCTURES FOR PARTICULAR PURPOSES; SWIMMING OR SPLASH BATHS OR POOLS; MASTS; FENCING; TENTS OR CANOPIES, IN GENERAL
    • E04H15/00Tents or canopies, in general
    • E04H15/32Parts, components, construction details, accessories, interior equipment, specially adapted for tents, e.g. guy-line equipment, skirts, thresholds
    • E04H15/34Supporting means, e.g. frames
    • E04H15/44Supporting means, e.g. frames collapsible, e.g. breakdown type having connecting nodes
    • EFIXED CONSTRUCTIONS
    • E04BUILDING
    • E04HBUILDINGS OR LIKE STRUCTURES FOR PARTICULAR PURPOSES; SWIMMING OR SPLASH BATHS OR POOLS; MASTS; FENCING; TENTS OR CANOPIES, IN GENERAL
    • E04H15/00Tents or canopies, in general
    • E04H15/32Parts, components, construction details, accessories, interior equipment, specially adapted for tents, e.g. guy-line equipment, skirts, thresholds
    • E04H15/56Floors
    • EFIXED CONSTRUCTIONS
    • E04BUILDING
    • E04HBUILDINGS OR LIKE STRUCTURES FOR PARTICULAR PURPOSES; SWIMMING OR SPLASH BATHS OR POOLS; MASTS; FENCING; TENTS OR CANOPIES, IN GENERAL
    • E04H15/00Tents or canopies, in general
    • E04H15/20Tents or canopies, in general inflatable, e.g. shaped, strengthened, or supported by fluid pressure
    • E04H2015/208Tents or canopies, in general inflatable, e.g. shaped, strengthened, or supported by fluid pressure with inflatable mattresses

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pixel portion switching element for a liquid crystal display device and a method of manufacturing the driving circuit portion for simultaneously forming a driving circuit using polysilicon.
Conventional thin film transistors for driving circuit-integrated liquid crystal display devices are manufactured by performing eight mask processes including a pixel electrode in a top gate structure. However, the more the mask process proceeds, the greater the defect and the higher the manufacturing cost, the less competitive.
According to the present invention, a thin film transistor is formed in a bottom gate structure using polysilicon, and a photoresist pattern used as a blocking mask during n-doping is used for doping by using a photoresist pattern used for n + doping. The mask can be saved. In addition, the number of masks can be reduced by simultaneously etching the source and drain electrodes and the semiconductor layer using diffraction exposure.
Accordingly, the present invention provides a method for manufacturing a switching device and a driving device of a liquid crystal display device integrated with a driving circuit by performing five or six mask processes including pixel electrodes.

Description

Method for fabricating switching and driving device for liquid crystal display device with driving circuit}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a method for manufacturing a switching element and a driving element for a liquid crystal display device using polysilicon.

Recently, liquid crystal displays have been spotlighted as next generation advanced display devices having low power consumption, good portability, technology-intensive, and high added value.

The liquid crystal display device injects a liquid crystal between an array substrate including a thin film transistor (TFT) and a color filter substrate to obtain an image effect by using a difference in refractive index of light according to the anisotropy of the liquid crystal. Means an image display device by a non-light emitting element.

Currently, an active matrix liquid crystal display (AM-LCD) in which the thin film transistor and the pixel electrode are arranged in a matrix manner has been attracting the most attention because of its excellent resolution and video performance. Hydrogenated amorphous silicon (a-Si: H) is mainly used because the low-temperature process is possible, so that an inexpensive insulating substrate can be used.

However, because hydrogenated amorphous silicon has disordered atomic arrangements, weak Si-Si bonds and dangling bonds exist, which are converted into a quasi-stable state when irradiated with light or applied with an electric field, and used as a thin film transistor device. It is difficult to use as a driving circuit due to poor stability and low electrical characteristics (low field effect mobility: 0.1 to 1.0 cm2 / V · s).

On the other hand, recently, liquid crystal display devices employing thin film transistors using poly-Si (poly-Si) have been researched and developed. Since the polysilicon has a field effect mobility of about 100 to 200 times greater than that of amorphous silicon, the response speed is fast and the stability to temperature and light is excellent. In addition, there is an advantage that the driving circuit can be formed on the same substrate.

Hereinafter, a manufacturing method of a switching device and a driving device of a liquid crystal display using polysilicon will be described with reference to the accompanying drawings.

1 is a schematic diagram of an array substrate on which a driving circuit is formed using polysilicon.

As shown, the driving circuit portion 5 and the pixel portion 3 are formed on the insulating substrate 1 together. The pixel portion 3 is positioned at the center of the substrate 1, and the gate and data driving circuit portions 5a and 5b are positioned at one side of the pixel portion 3 and the other side not parallel thereto. In the pixel portion 3, a plurality of gate lines 7 connected to the gate driving circuit part 5a and a plurality of data lines 9 connected to the data driving circuit part 5b cross each other, and the two wires cross each other. The pixel electrode 10 is formed in the pixel region P defined by the pixel region, and the thin film transistor T connected to the pixel electrode 10 is positioned at the intersection of the two wires.

In addition, the gate and data driving circuit unit are connected to an external signal input terminal 12.

The gate and data driver circuits 5a and 5b internally adjust an external signal input through the external signal input terminal 12 to control the display to the pixel unit 3 through the gate and data lines 7 and 9, respectively. Apparatus for supplying signals and data signals.

Accordingly, the gate and data driver circuits 5a and 5b are formed with a complementary metal-oxide semiconductor (CMOS) structure thin film transistor (not shown), which is an inverter, to properly output an input signal. It is.

The CMOS is a semiconductor technology used in a thin film transistor for driving circuits requiring high-speed signal processing. The CMOS uses extra electrons (n-type semiconductor) and negatively charged holes (p-type semiconductor) charged with negative electricity. One conductor is formed and driven in a complementary manner to form a current gate by effective electrical control of the two kinds of semiconductors.

Next, the configuration of the n-type and p-type thin film transistors, which are the pixel portion switching element and the driving circuit portion CMOS, of the array substrate including the above-described driving circuit portion will be described.

2A and 2B are cross-sectional views showing cross sections of the pixel switching element and the driving circuit CMOS driving element, respectively.

As shown in FIG. 2A, a buffer layer 25 made of an inorganic insulating material such as silicon oxide (SiO 2 ) is formed on an entire surface of the substrate 20 on the insulating substrate 20, and is disposed on the buffer layer 25. The semiconductor layer 30 is formed, and the gate insulating layer 45 is formed on the entire surface of the semiconductor layer 30. In addition, a gate electrode 50 is formed on the gate insulating film 45, and an interlayer 70 is formed on the gate electrode 50. Semiconductor layer contact holes 73a and 73b for contacting the semiconductor layer 30 are formed in the gate insulating layer 45 and the interlayer insulating layer 70, and the semiconductor layer contact hole 73a is disposed on the interlayer insulating layer 70. , 73b), and the source and drain electrodes 80a and 80b are formed to be spaced apart from the gate electrode 50 by a predetermined distance. A protective layer 90 including a drain electrode contact hole 95 is formed on the drain electrode 80b, and the drain electrode 80 is formed on the protective layer 90 through the drain electrode contact hole 95. ) Is connected to the pixel electrode 97.

In the semiconductor layer 30, a portion of the lower region of the gate insulating layer 45 corresponding to the gate electrode 50 forms an active layer 30a, and a portion of the semiconductor layer 30 contacting the source and drain electrodes 80a and 80b is n +. Doped to form an n-type ohmic contact layer 30c, and an n doped Lightly Doped Drain (LDD) layer 30b is formed between the active layer 30a and the n-type ohmic contact layer 30c.

Next, referring to FIG. 2B, which is a cross-sectional view of the CMOS structure thin film transistor of the driving circuit portion. In this case, the CMOS structure thin film transistor of the driving circuit unit includes a thin film transistor unit II including a semiconductor layer 35 doped with n + and a thin film transistor unit III including a semiconductor layer 40 doped with p +. For the sake of convenience, the same elements are denoted by the numerals in the order of II and III.

As illustrated, the n-type semiconductor layer 35 and the p-type semiconductor layer 40 are formed on the transparent insulating substrate 20 having the buffer layer 25 spaced apart from each other by a predetermined distance, and the n-type and p-type semiconductor layers The gate insulating layer 45 is formed on the entire surface of the upper portion 35 and 40, and the gate electrodes 55 and 60 are formed on the gate insulating layer 45. An interlayer insulating layer 70 including semiconductor layer contact holes 75a, 75b, 77a, and 77b is formed on the entire surface of the substrate 20 on the gate electrodes 55 and 60, and the interlayer insulating layer 70 is formed. Source and drain electrodes (83a, 87a, 83b, 87b) contacting the n-type and p-type semiconductor layers 35, 40, respectively, through the semiconductor layer contact holes 75a, 75b, 77a, and 77b, respectively. Is formed, and a protective layer 90 is formed over the entire surface of the source and drain electrodes 83a, 87a, 83b, 87b.

A region of the n-type semiconductor layer 35 corresponding to the gate electrode 55 and formed under the gate insulating layer 45 forms an active layer 35a and contacts the source and drain electrodes 83a and 83b. The semiconductor layer including the region forms an n + doped n-type ohmic contact layer 35c, and forms an n doped LDD layer 35b between the active layer 35a and the n-type ohmic contact layer 35c. have. In addition, since the p-type semiconductor layer 40 uses holes as carriers, since the deterioration of the carrier and the leakage current are less affected than the n-type thin film transistors, the pD semiconductor layer 40 does not form an LDD layer, The semiconductor layer region under the corresponding gate insulating layer 45 forms the active layer 40a, and the outer region of the active layer 40a forms the p-type ohmic contact layer 40c.

Next, a method of manufacturing the pixel switching element and the driving circuit unit driving element of the liquid crystal display device will be described.

3A to 3F and FIGS. 4A to 4F are cross-sectional views illustrating manufacturing processes in the pixel portion thin film transistor portion I and the driving circuit portion n-type and p-type thin film transistor portions II and III, respectively, in manufacturing steps.

As shown in FIGS. 3A and 4A, an inorganic insulating material such as silicon oxide (SiO 2 ) is deposited on the transparent insulating substrate 20 to form a buffer layer 25. After depositing amorphous silicon (a-Si) on the substrate 20 on which the buffer layer 25 is formed, and performing a dehydrogenation process, a laser crystallization process is performed to crystallize the amorphous silicon layer into a polysilicon layer. . Thereafter, a first mask process is performed to pattern the polysilicon layer to form semiconductor layers 30, 35, and 40.

3B and 4B, a silicon oxide (SiO 2 ) is deposited on the entire surface of the substrate 20 on which the semiconductor layers 30, 35, and 40 are formed to form a gate insulating layer 45. Subsequently, a metal material, for example, molybdenum (Mo) is deposited on the gate insulating layer 45 and then subjected to a second mask process to form gate electrodes 50, 55, and 60. The gate electrodes 50, 55, and 60 are used as masks to n-do lightly doped drain (LDD) doping by ion implantation on the entire surface of the substrate 20. In this case, the dose of LDD doping is approximately 1E13 / cm 2 to 5E13 / cm 2. At this time, the semiconductor layers 30a, 35a, and 40a under the gate electrodes 50, 55, and 60 of the pixel unit and the driving circuit unit are not doped, and all of the other semiconductor layers 30b, 35b, and 40b are n-doped. Is done.

Next, as shown in FIGS. 3C and 4C, PR is applied to the entire surface of the n-doped substrate 20 and a third mask process is performed to form a PR pattern 62. The PR pattern 62 is formed to include the gate electrodes 50 and 55 in the I and II regions so as to block the upper portion of the gate insulating layer 45 extending from the gate electrodes 50 and 55 at both sides. In the p-type thin film transistor unit III, the PR pattern 63 is formed to completely cover the gate insulating layer 45 corresponding to the semiconductor layer 40 including the gate electrode 60. Thereafter, n + doping by ion implantation having a high concentration of dose is performed on the entire surface of the substrate 20 on which the PR patterns 62 and 63 are formed. At this time, the semiconductor layer of the portion not blocked by the PR patterns 62 and 63 is n + doped to form n-type ohmic contact layers 30c and 35c. At this time, the dose of the n + doping has a value of approximately 1E15 / ㎠ to 9E15 / ㎠. In addition, the portions of the semiconductor layers 30 and 35 in the I and II regions, in which n − and n + doping are blocked by the gate electrodes 50 and 55, form the active layers 30 a and 35 a, and the active layers 30 a, The n-doped portion between 35a) and n-type ohmic contact layers 30c, 35c forms LDD layers 30b, 35b. Thereafter, the PR patterns 62 and 63 are removed.

Next, as shown in FIGS. 3D and 4D, PR is applied to the entire surface of the substrate 20 on which the n-type ohmic contact layers 30c and 35c are formed, and the fourth mask process is performed to form the gate electrode 50 in the I and II regions. And a PR pattern 65 formed to cover the gate insulating layer 45 of the portion corresponding to the semiconductor layers 30 and 35, including 55, and a gate of the portion corresponding to the p-type semiconductor layer 40 in the region III. The PR film is exposed without forming a PR pattern. Thereafter, p + doping is performed by ion implantation having a high dose of 1E15 / cm 2 to 9E15 / cm 2. The semiconductor layer 40 in which the ion doping is blocked by the gate electrode 60 in the III region forms an active layer 40a, and p + doped portions other than the active layer 40a are p-type ohmic contact layer 40c. ). Thereafter, the PR pattern 65 is removed.

3E and 4E, an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO 2 ) is deposited on the entire surface of the substrate 20 on which the p-type ohmic contact layer 40c is formed. The mask process is performed to form the interlayer insulating film 70. At this time, the gate insulating layer 45 is also etched to form semiconductor layer contact holes 73a, 73b, 75a, 75b, 77a, 77b exposing a part of the ohmic contact layers 30c, 35c, 40c to the outside. Thereafter, molybdenum (Mo) and aluminum neodymium (AlNd) are sequentially deposited on the substrate on which the interlayer insulating film 70 is formed, and are collectively etched by a sixth mask process to form the semiconductor layer contact holes 73a and 73b. Source and drain electrodes 80a, 83a, 87a, and 80b, 83b, and 87b connected to the ohmic contact layers 30c, 35c, and 40c through 75a, 75b, 77a, and 77b.

Next, as shown in FIGS. 3F and 4F, silicon nitride (SiNx) is formed on the substrate 20 on which the source and drain electrodes (80a, 83a, 87a, 80b, 83b, and 87b) are formed. After the deposition, the hydrogen nitride heat treatment of the silicon nitride (SiNx) is performed, a seventh mask process is performed to form a protective layer 90 having a drain contact hole 95. Since it belongs to the manufacturing process on the array substrate, but will be briefly described as it is associated with the thin film transistor manufacturing process. After the deposition of indium tin oxide (ITO) on the substrate on which the protective layer 90 is formed in a process corresponding to the pixel portion thin film transistor portion of the region I, an eighth mask process is performed to perform the drain contact hole 95. The pixel electrode 97 connected to the drain electrode 90b is formed through the pixel electrode 97.

A total of eight mask processes are performed in the switching device and the driving device manufacturing process of the conventional driving circuit-integrated liquid crystal display device. Since the mask process includes a photo resist coating, an exposure, and a development, the manufacturing cost and the processing time increase as the mask process is added. Therefore, there is a problem that the production yield is lowered, and the more the mask process, the higher the probability of generating defects of the thin film transistor element.

In addition, in the manufacture of the thin film transistor having the top gate structure as described above, a defect may occur in which the ohmic contact layer doped with n + is lost due to overetching when the semiconductor layer contact hole is formed.

In order to solve the above problems, the present invention fabricates a switching device and a driving device with a bottom gate structure, which is generally a thin film transistor structure using amorphous silicon, to reduce the doping mask for forming the LDD layer, source and drain The electrode and the semiconductor layer are etched simultaneously.

Therefore, the loss of the ohmic contact layer can be prevented by contacting the source and drain electrodes with the polysilicon semiconductor layer without contact holes, and the driving circuit-integrated liquid crystal display manufactured through the conventional eight mask processes including the pixel electrode. The purpose of the present invention is to reduce the manufacturing cost by reducing the mask and simplifying the process by manufacturing the switching element and the driving element of the device by performing only five or six mask processes.

In order to achieve the above object, according to the present invention, there is provided a switching element for a liquid crystal display device and a method of manufacturing the driving circuit-integrated liquid crystal display device, comprising: a pixel portion including a plurality of pixels including a switching portion on which a switching element is formed; On a substrate in which a CMOS element composed of n-type and p-type thin film transistors is configured, and a driving circuit portion including an n-type region where the n-type thin film transistor is formed and a p-type region where the p-type thin film transistor is formed, Forming a first gate electrode and a second gate electrode spaced apart from each other in correspondence with the driving circuit unit in correspondence with the switching unit of the pixel unit; Forming a gate insulating film over the first to third gate electrodes; Forming a polysilicon layer over the gate insulating film; First and second photoresist patterns may be formed over the switching layer and the n-type region, respectively, on the polysilicon layer, and in the p-type region, the polysilicon layer corresponding to the third gate electrode may be covered. Forming a third photoresist pattern; P + doping the polysilicon layer exposed to the outside of the first to third photoresist patterns by implanting a first dose of ions; After removing the first to third photoresist patterns, in the switching unit and the n-type region, fourth and fifth photoresist patterns, respectively, to cover the polysilicon layer corresponding to the first and second gate electrodes. Forming a sixth photoresist pattern in the p-type region to cover the polysilicon layer in a portion corresponding to the third gate electrode; N + doping the polysilicon layer exposed to the outside of the fourth to sixth photoresist patterns by implanting a second dose of ions; Performing a dry etch to reduce the width of the fourth and fifth photoresist patterns; N-doping the newly exposed polysilicon layer by implanting a third dose of ions by reducing the width of the fourth and fifth photoresist patterns; Removing the fourth to sixth photoresist patterns, and then forming a metal layer on the polysilicon layer; Etching the metal layer and the polysilicon layer thereunder to form a semiconductor layer of polysilicon separated from the first to third source and drain electrodes by a predetermined distance from the pixel portion and the driving circuit portion.

delete

In this case, before forming the first to third gate electrodes, forming a buffer layer on the entire surface of the substrate.

In addition, after the n-doping comprises the step of performing an activation process on the polysilicon layer.

The first dose to be implanted is 2E15 / cm 2 to 1E16 / cm 2, the second dose is 1E15 / cm 2 to 9E15 / cm 2, and the third dose has a value of 1E13 / cm 2 to 5E13 / cm 2.

Forming a protective layer over the first to third source and drain electrodes.

In this case, after the protective layer is formed, a step of hydrogenating heat treatment is included.

Hereinafter, a switching device and a driving device manufacturing process of a driving circuit-integrated liquid crystal display device according to an exemplary embodiment of the present invention will be described with reference to the drawings.

5A and 5B are cross-sectional views illustrating n-type and p-type thin film transistors, which are the pixel portion thin film transistors and the CMOS elements of the driving circuit portion, respectively, of the driving circuit integrated liquid crystal display according to the exemplary embodiment of the present invention. For convenience of description, the thin film transistor forming portion of the pixel portion is defined as region IV, the n-type thin film transistor forming portion of the driving circuit portion CMOS elements is defined as the V region and the p-type thin film transistor forming portion is region VI.

As shown in FIG. 5A, in the region IV, a buffer layer 105 made of an inorganic insulating material such as silicon oxide (SiO 2 ) is formed on the entire surface of the substrate 100, and the chromium layer is formed on the buffer layer 105. A gate electrode 110 of a single layer or a double layer of (Cr), aluminum (Al), or molybdenum (Mo) is formed. The gate insulating layer 117 and the semiconductor layer 123 are formed thereon, and the source and drain electrodes 140a and 140b are formed on the semiconductor layer 123 by a predetermined interval. In this case, the semiconductor layers 123b and 123c disposed under the source and drain electrodes 140a and 140b include an n-type ohmic contact layer 123c and an LDD layer (Lightly doped drain) 123b. The semiconductor layer 123a exposed to the spaced portion between the 140a and 140b forms the active layer 123a.

In addition, a passivation layer 150 including a drain contact hole 155 exposing the drain electrode 140b is formed on the source and drain electrodes 140a and 140b and drains through the drain contact hole 155. The pixel electrode 160 in contact with the electrode 140b is formed.

As shown in FIG. 5B, in the regions V and VI, a buffer layer 105 made of an inorganic insulating material such as silicon oxide (SiO 2 ) is formed on the entire surface of the substrate 100, and the buffer layers of each region are formed. Gate electrodes 112 and 114 are formed on the upper portion 105. The gate insulating film 117 and the semiconductor layers 126 and 129 of polysilicon are formed thereon. In addition, source and drain electrodes 142a and 144a and 142b and 144b are formed on the semiconductor layers 126 and 129 by a predetermined interval. In this case, the semiconductor layers 126b and 126c disposed under the source and drain electrodes 142a and 142b of the semiconductor layer 126 in the V region are composed of an n-type ohmic contact layer 126c and an LDD layer 126b. The exposed semiconductor layer 126a between the drain electrodes 142a and 142b forms the active layer 126a. In addition, the p-type ohmic contact layer 129b is formed under the source and drain electrodes 144a and 144b of the semiconductor layer 129 in the VI region, and the exposed portion between the source and drain electrodes 144a and 144b is formed as an active layer ( 129a). In addition, the passivation layer 150 is formed on the source and drain electrodes 142a and 144a and 144b and 144b in the V and VI regions.

Hereinafter, a description will be given of the switching element for a drive circuit-integrated liquid crystal display device and a method of manufacturing the drive element.

6A through 6F and 7A through 7F illustrate cross-sections of manufacturing processes of switching elements and driving elements for a liquid crystal display integrated with a driving circuit according to an embodiment of the present invention.

First, as shown in FIGS. 6A and 7A, silicon oxide (SiO 2 ) is deposited on the substrate 100 to form the buffer layer 105. Thereafter, chromium, aluminum, or molybdenum is deposited on the buffer layer 105 to the entire surface, and a mask process is performed to form gate electrodes 110, 112, and 114 in regions IV, V, and VI, respectively.

6B and 7B, an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO 2 ) is deposited on the entire surface of the substrate 100 on which the gate electrodes 110, 112, and 114 are formed. A gate insulating film 117 is formed, and amorphous silicon is deposited thereon to form an amorphous silicon layer. After the dehydrogenation of the amorphous silicon layer, the polysilicon layers 123, 126, and 129 are formed by crystallizing the amorphous silicon layer using a laser or the like.

Next, the photoresist is applied on the entire surface of the polysilicon layers 123, 126, and 129 and a mask process is performed to apply photoresist patterns 133a and 133b to the entire polysilicon layers 123 and 126 in the IV and V regions. In the VI region, the photoresist pattern 133c is formed to cover only the polysilicon layer 129a corresponding to the gate electrode 114.

Thereafter, the photoresist patterns 133a, 133b, and 133c are used as blocking masks, and p + is formed by ion implantation of a first dose into the polysilicon layer 129_ exposed to the outside of the photoresist patterns 133a, 133b, and 133c. The doping is preferably carried out from 2E15 / cm 2 to 1E16 / cm 2, wherein the polysilicon layers 123 and 126 in the IV and V regions are formed of photoresist patterns 133a and 133b. ) Is not doped as a blocking mask, and the polysilicon layer 129a of the portion of the polysilicon layer 129 of the VI region that corresponds to the gate electrode 114 is doped by the photoresist pattern 133c formed thereon. Other portions are p + doped to form a p-type ohmic contact layer 129b.

Next, as shown in FIGS. 6C and 7C, the photoresist patterns 133a, 133b, and 133c used as the p + doping blocking masks are removed by an etching or stripping process. Thereafter, photoresist is applied on the polysilicon layers 123, 126, and 129 in the IV, V, and VI regions and a mask process is performed to form the photoresist patterns 135a, 135b, and 135c. In this case, the IV and V regions are formed of the polysilicon layers 123a and 126a corresponding to the gate electrodes 110 and 112 and the polysilicon layers 123b and 126b having a predetermined interval to the outside of the polysilicon layers 123a and 126a. The photoresist patterns 135a and 135b are formed to cover the added portion, and the VI region forms the photoresist pattern 135c to completely cover the entire polysilicon layer 129.

Next, n + doping is performed by implanting a second dose into the exposed polysilicon layers 123c and 126c using the photoresist patterns 135a, 135b and 135c as blocking masks. The second dose is preferably selected from 1E15 / cm 2 to 9E15 / cm 2 values. At this time, among the polysilicon layers 123 and 126 in the IV and V regions, the polysilicon layers 123a and 126a and the poly on the gate electrodes 110 and 112 where ion implantation is blocked by photoresist patterns 135a and 135b are blocked. The polysilicon layers 123b and 126b at predetermined intervals outside the silicon layers 123a and 126a are not doped, and the other portions are n + doped to form n-type ohmic contact layers 123c and 126c. The polysilicon layer 129 in the region VI is not doped because the ion implantation is blocked by the photoresist pattern as a whole.

Next, as shown in FIGS. 6D and 7D, a portion of the photoresist patterns 135a and 135b used as blocking masks for the n + doping of the IV and V regions may be partially etched using dry etching equipment. It removes and exposes the polysilicon layer 123b of the predetermined space which is not doped below. At this time, the photoresist pattern 135c of the VI region is also etched by the dry etching to expose a portion of the p + doped polysilicon layer 129 below.

Thereafter, n-doping is performed on the partially exposed polysilicon layers 123b and 126b in the IV, V, and VI regions by ion implantation of a third dose. The third dose is preferably selected from the value of 1E13 / cm 2 to 5E13 / cm 2.

At this time, the photoresist patterns 135a and 135b in the IV and V regions are partially etched to remove the p + and n + undoped polysilicon layers 123b and 126b at the lower portions, and n-doped LDD layer 123b. 126b).

Other exposed p + or n + doped polysilicon layers 123c, 126c, and 129c are also n-doped but have no effect since they are doped with higher doses.

Next, as shown in FIGS. 6E and 7E, the photoresist patterns remaining on the polysilicon layers 123, 126, and 129 (135a, 135b, and 135c of FIGS. 6d and 7d) are subjected to etching or stripping. Remove it completely. Thereafter, an activation process of the polysilicon layers 123, 126, and 129 is performed.

Next, a metal layer is formed by depositing a metal material of aluminum or an aluminum alloy on the polysilicon layers 123, 126, and 129, and then masks the film using a diffraction exposure to be spaced apart from the IV, V, and VI regions by a predetermined interval. Source and drain electrodes 140a, 142a and 144a and 140b, 142b and 144b are formed. The non-doped polysilicon layers 123a and 126a may be exposed to the spaced portions between the source and drain electrodes 140a and 142a and 140b and 142b in regions IV and V. N + doped n-type ohmic contact layers 123c and 126c and n-doped LDD layers 123b and 126b are disposed under the drain electrodes 140a and 142a and 140b and 142b. In the region VI, an undoped polysilicon layer 129a is exposed between the source and drain electrodes 144a and 144b, and a p + doped p-type ohmic contact layer is disposed below the source and drain electrodes 144a and 144b. Let 129c be located. In addition, the source and drain electrodes 140a, 142a, 142a, 142b, 144b, 140b, 142b, 144b are not electrically connected to the respective regions in the IV, V, and VI regions. 144a), (140b, 142b, and 144b) and a metal layer other than the exposed polysilicon layers 123a, 126a, and 129a between the two electrodes and the polysilicon layer under the metal layer are removed to expose the gate insulating layer 117. do.

Although not shown, a thick photoresist pattern (not shown) is formed in the source and drain electrodes (140a, 142a, 144a, 140b, 142b, and 144b) forming portions of the respective regions during the mask process using the diffraction exposure after forming the metal layer. A thin photoresist pattern (not shown) is formed on a portion to be spaced apart between the drain electrode and the source electrode (140a, 142a, 144a), (140b, 142b, 144b), and on the other portion of the photo. No resist pattern is formed. The exposed metal layer other than the photoresist pattern is then etched away. In addition, the polysilicon layer under the removed metal layer is also removed by etching. Thereafter, the thin photoresist pattern is removed through etching, and the metal layer under the thin photoresist pattern is removed by etching to form independent source drain electrodes in each region.

At this time, the polysilicon layers 123 and 126 below the non-etched regions IV and V of the source and drain electrodes 140a and 142a and 140b and 142b may be n-type ohmic contact layers 123c and 126c and LDD. The semiconductor layers of the layers 123b and 126b are formed, and the polysilicon layer 129c under the source and drain electrodes 144a and 144b in the region VI forms a semiconductor layer that is a p-type ohmic contact layer 129c. In addition, the semiconductor layers in the spaced apart portions between the source and drain electrodes 140a, 142a and 144a and 140b, 142b and 144b in each region are active layers 123a, 126a and 129a.

Next, as illustrated in FIGS. 6F and 7F, silicon nitride (SINx) or silicon oxide is disposed over the source and drain electrodes 140a, 142a, 144a, 140b, 142b, and 144b in regions IV, V, and VI. A protective layer 150 is formed by depositing an inorganic insulating material (SiO 2 ). Thereafter, a hydrogenation heat treatment process is performed on the substrate 100 on which the protective layer 150 is formed. This is to improve contact characteristics between the semiconductor layers 123, 126, and 129 and the source and drain electrodes 140a, 142a, 144a, and 140b, 142b, and 144b.

Next, a mask process is performed on the protective layer 150 in a process corresponding only to region IV, that is, the pixel portion switching element, to form a drain contact hole 155 exposing the drain electrode. Thereafter, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the entire surface of the protective layer 150 and subjected to a mask process to drain the electrode through the drain contact hole 155. The pixel electrode 160 in contact with 140b is formed.

8A and 8B illustrate another example of forming the pixel electrode.

Since the formation of the source and drain electrodes proceeds in the same manner as described above with reference to FIGS. 6A to 6E and 7A to 7E, the description is omitted.

As shown in Figs. 8A and 8B, indium-tin is not formed over the source and drain electrodes (140a, 142a, 144a, 140b, 142b, and 144b) in regions IV, V, and VI. A transparent conductive material such as -oxide (ITO) or indium-zinc-oxide (IZO) is deposited over the source and drain electrodes (140a, 142a, 144a), (140b, 142b, 144b) and the mask process is performed. Proceeding to form a pixel electrode 165 in direct contact with the drain electrode 140b in region IV. In this case, since the pixel electrode 165 is formed in direct contact with the drain electrode 140b, an etchant used for etching the pixel electrode 165 may be a source and a drain electrode (140a, 142a, 144a), or 140b. , 142b, 144b)) shall be used that does not affect the metallic material of which they are made.

As described above, when forming the pixel electrode without the protective layer, a total of five mask processes may be performed to fabricate an array substrate including a thin film transistor.

As described above, the bottom gate thin film transistor is formed by the method of manufacturing the thin film transistor of the liquid crystal display integrated with the driving circuit according to the present invention, and the semiconductor layer is directly contacted with the source and drain electrodes without forming contact holes. It is possible to prevent the loss of the ohmic contact layer due to etching.

In addition, the number of masks may be reduced by dry etching the photoresist pattern used as the blocking mask during n + doping and removing a part of the photoresist pattern, and again removing the blocking mask process for forming the LDD layer using the blocking mask during n-doping.

Therefore, the pixel switching element and the driving circuit driving element of the driving circuit-integrated liquid crystal display device, which are manufactured using a total of eight masks including the conventional pixel electrode, can be manufactured in six or five mask processes, thereby simplifying the manufacturing process and It reduces the manufacturing time by shortening the process time.

1 is a schematic diagram of an array substrate of a general driving circuit-integrated liquid crystal display device.

2A and 2B are cross-sectional views of a pixel portion switching element and a driving circuit portion CMOS driving element of a conventional drive circuit integrated liquid crystal display device;

3A to 3F and FIGS. 4A to 4F are cross-sectional views illustrating stages of manufacturing a switching element of a conventional pixel unit and a CMOS driving element of a driving circuit unit, respectively.

5A and 5B are sectional views of a bottom gate type pixel portion thin film transistor and a driving circuit portion CMOS driving element according to a first embodiment of the present invention;

6A to 6F and 7A to 7F are cross-sectional views illustrating manufacturing steps of a switching device of a pixel unit and a CMOS driving device of a driving circuit unit according to a first embodiment of the present invention, respectively.

8A and 8B are cross-sectional views of a bottom gate type pixel portion thin film transistor and a driving circuit portion CMOS thin film transistor showing a modification example according to the first embodiment of the present invention;

<Description of Symbols for Main Parts of Drawings>

100 substrate 105 buffer layer

112 and 114: gate electrode 117: gate insulating film

126 (126a, 126b, 126c) and 129 (129a, 129b): semiconductor layer

126a and 129a active layer 126b LDD layer

126c: n-type ohmic contact layer 129b: p-type ohmic contact layer

Ⅴ: n-type thin film transistor unit

Ⅵ: P-type thin film transistor unit

Claims (6)

  1. A n-type region including a pixel portion including a plurality of pixels including a switching portion in which a switching element is formed, a CMOS element including n-type and p-type thin film transistors outside the pixel portion, wherein the n-type thin film transistor is formed; A second gate and a second gate spaced apart from each other in correspondence with the first gate electrode corresponding to the switching unit of the pixel unit on a substrate on which a driving circuit unit including a p-type region in which the p-type thin film transistor is formed is defined; Forming a three gate electrode;
    Forming a gate insulating film over the first to third gate electrodes; Forming a polysilicon layer over the gate insulating film;
    First and second photoresist patterns may be formed over the switching layer and the n-type region, respectively, on the polysilicon layer, and in the p-type region, the polysilicon layer corresponding to the third gate electrode may be covered. Forming a third photoresist pattern;
    P + doping the polysilicon layer exposed to the outside of the first to third photoresist patterns by implanting a first dose of ions;
    After removing the first to third photoresist patterns, in the switching unit and the n-type region, fourth and fifth photoresist patterns, respectively, to cover the polysilicon layer corresponding to the first and second gate electrodes. Forming a sixth photoresist pattern in the p-type region to cover the polysilicon layer in a portion corresponding to the third gate electrode;
    N + doping the polysilicon layer exposed to the outside of the fourth to sixth photoresist patterns by implanting a second dose of ions;
    Performing a dry etch to reduce the width of the fourth and fifth photoresist patterns;
    N-doping the newly exposed polysilicon layer by implanting a third dose of ions by reducing the width of the fourth and fifth photoresist patterns;
    Removing the fourth to sixth photoresist patterns, and then forming a metal layer on the polysilicon layer;
    Etching the metal layer and the polysilicon layer below the semiconductor layer to form a semiconductor layer of polysilicon separated from the first to third source and drain electrodes by a predetermined distance from the pixel portion and the driving circuit portion;
    Switching element for a drive circuit-integrated liquid crystal display device comprising a; and a method of manufacturing a drive element.
  2. The method of claim 1,
    And forming a buffer layer on the entire surface of the substrate before forming the first to third gate electrodes.
  3. The method of claim 1,
    And a process of activating the polysilicon layer after the n-doping.
  4. The method of claim 1,
    The first dose to be implanted is 2E15 / cm 2 to 1E16 / cm 2, the second dose is 1E15 / cm 2 to 9E15 / cm 2, and the third dose is 1E13 / cm 2 to 5E13 / cm 2 Method of manufacturing a switching and driving device for a liquid crystal display device.
  5. The method of claim 1,
    And a protective layer formed over the first to third source and drain electrodes.
  6. The method of claim 5, wherein
    After the protective layer is formed, the switching element and driving device manufacturing method for a drive circuit-integrated liquid crystal display device comprising the step of hydrogenation heat treatment.
KR1020030014492A 2003-03-07 2003-03-07 Method for fabricating switching and driving device for liquid crystal display device with driving circuit KR100915148B1 (en)

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JP2001007342A (en) * 1999-04-20 2001-01-12 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacture
KR20010014785A (en) * 1999-04-20 2001-02-26 야마자끼 순페이 Semiconductor device and manufacturing method thereof
JP2001068680A (en) * 1999-04-06 2001-03-16 Semiconductor Energy Lab Co Ltd Semiconductor device and fabrication thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001068680A (en) * 1999-04-06 2001-03-16 Semiconductor Energy Lab Co Ltd Semiconductor device and fabrication thereof
JP2001007342A (en) * 1999-04-20 2001-01-12 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacture
KR20010014785A (en) * 1999-04-20 2001-02-26 야마자끼 순페이 Semiconductor device and manufacturing method thereof

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