JPH0775246B2 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0775246B2 JPH0775246B2 JP62157704A JP15770487A JPH0775246B2 JP H0775246 B2 JPH0775246 B2 JP H0775246B2 JP 62157704 A JP62157704 A JP 62157704A JP 15770487 A JP15770487 A JP 15770487A JP H0775246 B2 JPH0775246 B2 JP H0775246B2
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- island
- semiconductor integrated
- integrated circuit
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、制御回路部と高耐圧出力回路部とが集積され
たパワーICに係り、特に高耐圧出力回路部のオン抵抗を
下げ、消費電力を低減し、しかも誤動作の生じない半導
体集積回路装置に関する。Description: TECHNICAL FIELD The present invention relates to a power IC in which a control circuit section and a high breakdown voltage output circuit section are integrated, and particularly to reduce the on-resistance of the high breakdown voltage output circuit section and to reduce the consumption. The present invention relates to a semiconductor integrated circuit device that reduces power and does not cause malfunction.
従来の制御回路部と、高耐圧出力回路部とを有する半導
体集積回路装置は、例えば第４図に示すようにCMOS論理
回路からなる制御回路部10と、縦型ｎ−MOS201と横型ｐ
−MOS202とからなる高耐圧出力回路20部とから構成さ
れ、制御回路部の任意のブロツク間及び高耐圧出力回路
部の縦型ｎ−MOS201と横型ｐ−MOS202との間は接合分離
技術により電気的に分離された構成を採つている（富士
時報Vol.59No.11 1986の第703〜706頁）。しかしなが
ら、この種半導体集積回路装置においては、変位電流な
どによるラツチアツプが発生する可能性があり、また縦
型ｎ−MOSの埋込層の部分を含めたMOSオン抵抗を下げる
ことに関しては配慮されていなかつた。A semiconductor integrated circuit device having a conventional control circuit section and a high breakdown voltage output circuit section has a control circuit section 10 including a CMOS logic circuit, a vertical n-MOS 201, and a horizontal p-type as shown in FIG.
-MOS202 and high breakdown voltage output circuit 20 section, and between the arbitrary block of the control circuit section and between the vertical n-MOS201 and horizontal p-MOS202 of the high breakdown voltage output circuit section by the junction separation technology. The structure is separated into two parts (Fuji Jikho Vol.59 No.11 1986, pages 703-706). However, in this type of semiconductor integrated circuit device, there is a possibility that a latchup may occur due to a displacement current or the like, and consideration is given to lowering the MOS on-resistance including the buried layer portion of the vertical n-MOS. Nakatsuta.
上述の従来技術では、縦型ｎ−MOSの埋込層の部分を含
めたMOSのオン抵抗を下げる点で充分配慮がされておら
ず、また、接合分離技術を採用しているためラツチアツ
プが発生する可能性がある等の問題があつた。In the above-mentioned conventional technology, sufficient consideration has not been given to reducing the on-resistance of the MOS including the buried layer portion of the vertical n-MOS, and since the junction isolation technology is adopted, ratcheting occurs. There was a problem such as possible.
本発明の目的は、制御回路部と高耐圧出力回路部とを備
える新規な構造の半導体集積回路装置を提供することに
ある。An object of the present invention is to provide a semiconductor integrated circuit device having a novel structure including a control circuit section and a high breakdown voltage output circuit section.
本発明の他の目的は、オン抵抗を大幅に低減しラツチア
ツプの生じない半導体集積回路装置を提供することにあ
る。Another object of the present invention is to provide a semiconductor integrated circuit device in which the on-resistance is significantly reduced and no latch-up occurs.
上記目的は、同一チップ上に低圧制御回路部と高耐圧出
力回路部が集積され、おのおのが誘導体により電気的に
分離された半導体集積回路装置において、高耐圧出力部
は、第１の単結晶島に形成した一方導電型の縦型MOSト
ランジスタと、第２の単結晶島に形成した他方導電型の
横型MOSトランジスタのトーテムポール接続から成り、
第１の単結晶島の底部からチップの他方面まで達する単
結晶層と、第１及び第２の単結晶島に隣接する第３の単
結晶島の底部からチップの他方面まで達する単結晶層と
を形成し、これら単結晶層を他方面に形成されたドレイ
ン電極としての金属膜にオーミック接触し、横型MOSト
ランジスタのドレインと第３の単結晶島とをチップの一
方面に設けた電極で接続することにより達成できる。In the semiconductor integrated circuit device in which the low-voltage control circuit unit and the high-voltage output circuit unit are integrated on the same chip and each is electrically separated by the dielectric, the high-voltage output unit is the first single crystal island. Consisting of a vertical MOS transistor of one conductivity type formed in and a lateral MOS transistor of the other conductivity type formed on the second single crystal island,
A single crystal layer extending from the bottom of the first single crystal island to the other surface of the chip, and a single crystal layer extending from the bottom of the third single crystal island adjacent to the first and second single crystal islands to the other surface of the chip Is formed, and these single crystal layers are ohmic-contacted with the metal film as the drain electrode formed on the other surface, and the drain of the lateral MOS transistor and the third single crystal island are provided on one surface of the chip. It can be achieved by connecting.
誘電体分離技術を採用することにより、接合分離技術に
見られるような寄生のpnpn構造が存在しないので、ラツ
チアツプの発生が皆無となる。また、縦型MOSの島底か
ら基板裏面まで達する単結晶層はドレイン電流の通路と
して作用し、主表面にドレイン電極を設けたものに比
べ、通路の実効的な断面積を大きくし、かつ長さを短く
することが可能となるので、オン抵抗を大幅に低減する
ことができる。By adopting the dielectric isolation technology, since there is no parasitic pnpn structure as found in the junction isolation technology, the occurrence of ratchet is eliminated. Also, the single crystal layer of the vertical MOS that reaches from the island bottom to the back surface of the substrate acts as a passage for the drain current, making the effective cross-sectional area of the passage larger and longer than that in the case where the drain electrode is provided on the main surface. Since it is possible to shorten the length, the on-resistance can be significantly reduced.
以下、本発明半導体集積回路装置を実施例として示した
図面により説明する。Hereinafter, the semiconductor integrated circuit device of the present invention will be described with reference to the drawings showing examples.
第１図は本発明半導体集積回路装置の一実施例で、
（ａ）は半導体集積回路装置の高耐圧出力回路部の斜視
断面図、（ｂ）は（ａ）の電気回路図、（ｃ）は半導体
集積回路装置の電気回路図である。図において、１は一
対の主表面11,12を有する誘電体分離基板で、大部分が
多結晶半導体基材13からなり、その基材内に一方の主表
面11側に誘電体膜14を介して単結晶半導体領域15,16,17
が島状に埋設された構成となつている。単結晶半導体領
域15,16,17はｐ型で誘電体膜14に隣接する個所が高不純
物濃度p+となつており、領域15にはその一方の主表面11
に露出する個所に隣接する２個のｎ型層及びそのｎ型層
内にソースとなるp+型層を形成して縦型ｐ−MOSを構成
し、領域17にはその一方の主表面11に露出する個所にソ
ース，ドレインとなる２個のn+型層を形成して横型ｐ−
MOSを構成し、領域16にはその一方の主表面11に露出す
る個所にp+型層を形成してコンタクト領域を構成してい
る。また、領域15,16はその底部の誘電体膜を貫通して
ｐ型単結晶層15′,16′が他方の主表面12まで延在して
いる。この実施例ではｐ型単結晶層15′,16′と多結晶
半導体基材13との間に誘電体膜は形成されていない。２
は一方の主表面11に形成された絶縁膜、31及び32は周囲
が絶縁膜４で被覆され領域15,16上に載置されたゲー
ト、５は絶縁面２を貫通して縦型ｐ−MOSの２個のp+層
にオーミツク接触した第１の金属膜、６は絶縁膜２を貫
通して領域の16のp+型層及び領域17の一方のn+型層にオ
ーミツク接触した第２の金属層、７は絶縁膜２を貫通し
て領域17の他方のn+型層にオーミツク接触した第３の金
属層、８は他方の主表面12に形成した第４の金属層であ
る。ゲート31,32はゲートと同材質の導体33で接続され
ている。FIG. 1 shows an embodiment of the semiconductor integrated circuit device of the present invention.
(A) is a perspective sectional view of a high breakdown voltage output circuit portion of the semiconductor integrated circuit device, (b) is an electric circuit diagram of (a), and (c) is an electric circuit diagram of the semiconductor integrated circuit device. In the figure, reference numeral 1 denotes a dielectric isolation substrate having a pair of main surfaces 11 and 12, which is mostly made of a polycrystalline semiconductor base material 13 and has a dielectric film 14 on one main surface 11 side in the base material. Single crystal semiconductor region 15,16,17
It is constructed so that it is buried like an island. The single crystal semiconductor regions 15, 16 and 17 are p-type, and a portion adjacent to the dielectric film 14 has a high impurity concentration p + , and the region 15 has one main surface 11 thereof.
A vertical p-MOS is formed by forming two n-type layers adjacent to the exposed portion and a p + -type layer serving as a source in the n-type layer, and in the region 17, one of the main surfaces 11 is formed. Two n + -type layers, which will be the source and drain, are formed on the exposed area of
A MOS region is formed, and a p + type layer is formed in a region exposed on one main surface 11 of the region 16 to form a contact region. In regions 15 and 16, p-type single crystal layers 15 'and 16' extend to the other main surface 12 through the dielectric film at the bottom thereof. In this embodiment, no dielectric film is formed between the p-type single crystal layers 15 'and 16' and the polycrystalline semiconductor substrate 13. Two
Is an insulating film formed on one main surface 11, 31 and 32 are gates which are covered with an insulating film 4 on the periphery and are placed on the regions 15 and 16, and 5 is a vertical p-type penetrating the insulating surface 2. The first metal film in ohmic contact with the two p + layers of MOS, 6 penetrates through the insulating film 2 and comes into ohmic contact with 16 p + type layers in the region and one n + type layer in the region 17. 2 is a metal layer, 7 is a third metal layer which penetrates the insulating film 2 and is in ohmic contact with the other n + -type layer in the region 17, and 8 is a fourth metal layer formed on the other main surface 12. . The gates 31 and 32 are connected by a conductor 33 made of the same material as the gate.
次に、かかる半導体集積回路装置の製造方法を第２図の
工程図により説明する。Next, a method of manufacturing such a semiconductor integrated circuit device will be described with reference to the process chart of FIG.
ｐ型Si単結晶基板を準備し、その一方面に異方性エツチ
ングを施し所望のＶ字形溝9aを形成した後p+型埋込み層
を形成する（第２図ａ）。基板の一方面に誘電体膜14と
なるSiO2膜14′を選択的形成する（第２図ｂ）。そして
基板の一方面上にｐ型不純物をドープしながらシリコン
層を堆積させる。シリコン層はSiO2膜上では基材13とな
る多結晶基板の露出部上では層15′,16′となる単結晶
となる（第２図ｃ）。次に基板を上下反転させＶ溝部底
部が露出するまで基板を研磨し本発明で使用する誘電体
分離基板が完成する（第２図ｄ）。その上に、ゲート絶
縁膜４となるSiO2膜４′とゲート31,32となるポリSi層3
1′,32′を形成する（第２図ｅ）。更に、SiO2より成る
エツチングマスク9bを形成し、その開口部より縦型ｐ−
MOSチヤネル部分となるｎ型層を形成する（第２図
ｆ）。さらにSiO2よりなるエツチングマスク9cを形成
し、その開口部より横型ｎ−MOSのソース，ドレイン領
域となるn+型層を形成する（第２図ｇ）。A p-type Si single crystal substrate is prepared, and anisotropic etching is applied to one surface of the p-type Si single-crystal substrate to form a desired V-shaped groove 9a, and then a p + -type buried layer is formed (FIG. 2a). A SiO 2 film 14 ′ serving as a dielectric film 14 is selectively formed on one surface of the substrate (FIG. 2B). Then, a silicon layer is deposited on one surface of the substrate while being doped with p-type impurities. Silicon layer is a layer 15 ', 16' to become single crystals on the exposed portion of the polycrystalline substrate as a base material 13 on the SiO 2 film (FIG. 2 c). Next, the substrate is turned upside down and polished until the bottom of the V-groove is exposed to complete the dielectric isolation substrate used in the present invention (FIG. 2d). On top of that, a SiO 2 film 4 ′ that will become the gate insulating film 4 and a poly-Si layer 3 that will become the gates 31 and 32.
1 ', 32' are formed (Fig. 2e). Further, an etching mask 9b made of SiO 2 is formed, and a vertical p-type is formed through the opening.
An n-type layer to be a MOS channel portion is formed (Fig. 2f). Further, an etching mask 9c made of SiO 2 is formed, and n + type layers to be the source and drain regions of the lateral n-MOS are formed from the opening (FIG. 2g).
次に、SiO2よりなるエツチングマスク9dを形成し、その
開口部より縦型ｐ−MOSのソース領域及び領域16のp+型
層となるｐ型高濃度層を形成する（第２図ｈ）。しかる
後、CVD−SiO2又はCVD−PSG膜を全面に形成し、コンタ
クト用の開口部を設け、Al等の第1,第2,第３の金属層5,
6,7を形成し、裏面に第４の電極層８形成する（第２図
ｉ）。以上の工程により第１図（ａ）に示す高耐圧相補
形MOSの出力段が得られる。Next, an etching mask 9d made of SiO 2 is formed, and a p-type high-concentration layer serving as a p + -type layer of the vertical p-MOS source region and the region 16 is formed from the opening (FIG. 2h). . After that, a CVD-SiO 2 or CVD-PSG film is formed on the entire surface, an opening for contact is provided, and the first, second, and third metal layers 5, such as Al,
6 and 7 are formed, and the fourth electrode layer 8 is formed on the back surface (FIG. 2i). Through the above steps, the output stage of the high breakdown voltage complementary MOS shown in FIG. 1 (a) is obtained.
本実施例においては、縦型ｐ−MOSのドレインが、単結
晶島15の底から成長した単結晶層15′を通じて基板裏面
12に達し、さらに横型ｎ−MOSのドレインが、一方主表
面11の第２の金属層６を介して隣接する単結晶島16に接
続され、裏面12の第４の金属層８により共通となつてお
り、第１図（ｂ）に示すようなCMOS構造を構成してい
る。In this embodiment, the drain of the vertical p-MOS is formed on the back surface of the substrate through the single crystal layer 15 ′ grown from the bottom of the single crystal island 15.
12, the drain of the lateral n-MOS is further connected to the adjacent single crystal island 16 via the second metal layer 6 on the main surface 11 on the one hand, and is made common by the fourth metal layer 8 on the back surface 12. Therefore, a CMOS structure as shown in FIG. 1 (b) is formed.
第３図は本発明に関する参考例であり、横型ｎ−MOSの
ドレインを裏面12に落とすための島領域16,16′を設け
ずに、縦型ｐ−MOSを形成する領域15の主表面にp+埋込
層を形成し、この埋込層に第２の金属層６をオーミツク
接触させた構造としている。FIG. 3 is a reference example related to the present invention, in which the main surface of the region 15 where the vertical p-MOS is formed is not provided with the island regions 16 and 16 'for dropping the drain of the lateral n-MOS to the back face 12. A p + buried layer is formed, and the second metal layer 6 is brought into ohmic contact with this buried layer.
トーテムポール接続の高耐圧低オン抵抗CMOSにおいて
は、Al等の金属層の配線抵抗が無視できないレベルにあ
り、第４図に示す従来例の様に主表面のみにおいてドレ
イン電極をつなげる構造では、蒸着等の方法によりAl電
極を形成する際その厚さには限界があり〜４μｍ程度で
ある。そのため、配線を極力短くする必要があるが、従
来の構造では、第１図（ｂ）に示すトーテムポール接続
の内ソース配線S1,ドレイン配線D,ソース配線S2のそれ
ぞれ３つの電位を持つ配線を交差することなくレイアウ
トする必要があるため、配線が複雑となりオン抵抗成分
の一つである配線抵抗が大きくなるという問題がある。
参考例では、ドレイン電極を基板裏面で共通することに
より、主表面でのレイアウトを簡略化し、配線抵抗を大
幅に低減できる。また、裏面ドレイン電極は、抵抗金属
板に半田等により低抵抗接続できるのでさらに低抵抗化
が可能であるという効果がある。In a high withstand voltage low on-resistance CMOS with a totem pole connection, the wiring resistance of a metal layer such as Al is at a level that cannot be ignored, and with the structure in which the drain electrode is connected only on the main surface as in the conventional example shown in FIG. When the Al electrode is formed by the method described above, the thickness thereof is limited and is about 4 μm. Therefore, it is necessary to make the wiring as short as possible, but in the conventional structure, each of the source wiring S 1 , the drain wiring D, and the source wiring S 2 of the totem pole connection shown in FIG. 1B has three potentials. Since it is necessary to lay out the wiring without intersecting the wiring, there is a problem that the wiring becomes complicated and the wiring resistance, which is one of the on-resistance components, becomes large.
In the reference example, the drain electrode is commonly used on the back surface of the substrate, so that the layout on the main surface can be simplified and the wiring resistance can be significantly reduced. Further, since the back surface drain electrode can be connected to the resistance metal plate with low resistance by soldering or the like, there is an effect that the resistance can be further reduced.
本発明によれば、誘電体分離構造をとりながら高耐圧出
力回路部のCMOSドレイン電極を基板裏面にとることがで
きるので、ラツチアツプ耐量にすぐれ、しかも、縦型MO
Sのオン抵抗及び、主表面での横型MOSのドレイン電極配
線抵抗を大巾に下げることができ、さらに主表面での電
極配線部の面積を最小とすることができるので、高集積
化が可能な高性能パワーICを提供することができる。According to the present invention, the CMOS drain electrode of the high breakdown voltage output circuit section can be formed on the back surface of the substrate while adopting the dielectric isolation structure.
The on resistance of S and the drain electrode wiring resistance of the lateral MOS on the main surface can be greatly reduced, and the area of the electrode wiring section on the main surface can be minimized, enabling high integration. It is possible to provide a high performance power IC.
第１図は本発明半導体集積回路装置の１実施例を示す概
略斜視図及び電気回路図、第２図は、第１図に示す半導
体集積回路装置の製造工程を示す断面図、第３図は、本
発明の参考例を示す断面図、第４図は、従来例装置の概
略断面図である。 １……誘電体分離基板、５……第１の金属層、６……第
２の金属層、７……第３の金属層、８……第４の金属
層、15,16,17……単結晶半導体領域、15′,16′……ｐ
型単結晶層。1 is a schematic perspective view and an electric circuit diagram showing one embodiment of a semiconductor integrated circuit device of the present invention, FIG. 2 is a sectional view showing a manufacturing process of the semiconductor integrated circuit device shown in FIG. 1, and FIG. FIG. 4 is a sectional view showing a reference example of the present invention, and FIG. 4 is a schematic sectional view of a conventional device. 1 ... Dielectric isolation substrate, 5 ... first metal layer, 6 ... second metal layer, 7 ... third metal layer, 8 ... fourth metal layer, 15,16,17 ... … Single crystal semiconductor region, 15 ′, 16 ′ …… p
Type single crystal layer.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 松崎 均 茨城県日立市幸町３丁目１番１号 株式会 社日立製作所日立工場内 (56)参考文献 特開 昭60−80243（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hitoshi Matsuzaki 3-1-1 Sachimachi, Hitachi, Ibaraki Inside Hitachi factory, Hitachi Ltd. (56) References JP-A-60-80243 (JP, A)
Claims (1)
力回路部が集積され、おのおのが誘導体により電気的に
分離された半導体集積回路装置において、 高耐圧出力部は、第１の単結晶島に形成した一方導電型
の縦型MOSトランジスタと、第２の単結晶島に形成した
他方導電型の横型MOSトランジスタのトーテムポール接
続から成り、 第１の単結晶島の底部からチップの他方面まで達する単
結晶層と、 第１及び第２の単結晶島に隣接する第３の単結晶島の底
部からチップの他方面まで達する単結晶層と、 を形成し、 これら単結晶層を他方面に形成されたドレイン電極とし
ての金属膜にオーミック接触し、横型MOSトランジスタ
のドレインと第３の単結晶島とをチップの一方面に設け
た電極で接続したことを特徴とする半導体集積回路装
置。1. A semiconductor integrated circuit device in which a low-voltage control circuit section and a high-breakdown-voltage output circuit section are integrated on the same chip, and each is electrically separated by a dielectric, in which the high-breakdown-voltage output section is a first single crystal. Totem pole connection of one conductivity type vertical MOS transistor formed on the island and another conductivity type horizontal MOS transistor formed on the second single crystal island, and the other surface of the chip from the bottom of the first single crystal island. And a single crystal layer reaching from the bottom of the third single crystal island adjacent to the first and second single crystal islands to the other surface of the chip, and forming these single crystal layers on the other surface. A semiconductor integrated circuit device characterized in that an ohmic contact is made to a metal film formed as a drain electrode, and the drain of the lateral MOS transistor and the third single crystal island are connected by an electrode provided on one surface of the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62157704A JPH0775246B2 (en) | 1987-06-26 | 1987-06-26 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62157704A JPH0775246B2 (en) | 1987-06-26 | 1987-06-26 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS644058A JPS644058A (en) | 1989-01-09 |
| JPH0775246B2 true JPH0775246B2 (en) | 1995-08-09 |
Family
ID=15655549
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62157704A Expired - Lifetime JPH0775246B2 (en) | 1987-06-26 | 1987-06-26 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0775246B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5874341A (en) * | 1996-10-30 | 1999-02-23 | Advanced Micro Devices, Inc. | Method of forming trench transistor with source contact in trench |
| US5796143A (en) * | 1996-10-30 | 1998-08-18 | Advanced Micro Devices, Inc. | Trench transistor in combination with trench array |
| US6100146A (en) | 1996-10-30 | 2000-08-08 | Advanced Micro Devices, Inc. | Method of forming trench transistor with insulative spacers |
| US5780340A (en) * | 1996-10-30 | 1998-07-14 | Advanced Micro Devices, Inc. | Method of forming trench transistor and isolation trench |
| US5801075A (en) * | 1996-10-30 | 1998-09-01 | Advanced Micro Devices, Inc. | Method of forming trench transistor with metal spacers |
| US7763974B2 (en) | 2003-02-14 | 2010-07-27 | Hitachi, Ltd. | Integrated circuit for driving semiconductor device and power converter |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6080243A (en) * | 1983-10-08 | 1985-05-08 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and manufacture thereof |
-
1987
- 1987-06-26 JP JP62157704A patent/JPH0775246B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS644058A (en) | 1989-01-09 |
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