JPS6080243A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a high resistance voltage semiconductor device which can process a high power and high voltage signal by allowing the bottom surface of island region at the center to be in contact with the substrate through elimination of an insulating film at the time of forming a plurality of island regions on the semiconductor substrate through an insulating film and by providing input/output electrodes thereto. CONSTITUTION:An n<+> type buried layer 2 is formed on an n type Si substrate 1 by the diffusion, a composite mask 31 of which lower layer is Si3N4 while the upper layer is SiO2 is provided at the center of this surface and the SiO2 mask 3 is provided in both sides of such composite mask. A V-shaped groove reaching the substrate 1 is formed by the anisotropic etching and the SiO2 film of the masks 3 and 31 is removed. Thereafter, the SiO2 film 6 is deposited from the wall surface of V-groove to both sides thereof with the remaining Si3N4 film used as the mask, the Si3N4 film is removed, an nn<+> type support Si layer 7 is deposited on the entire part, and thereby a polycrystalline layer 72 is generated on the V-groove and a single crystal layer 71 on the region surrounded by such polycrystalline layer. Thereafter, upper and lower layers are reversed, the substrate 1 is polished until the bottom part of V-groove is exposed and the layer 71 is used as the signal electrode attaching part.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device applied to high power and high voltage applications and a method for manufacturing the same. [Prior Art] Conventionally, this type of semiconductor device has It was formed by a manufacturing method as shown in FIGS. 1(a) to (e). That is, as shown in FIG. 2(a), υ A8 is implanted into the surface of an n-type semiconductor substrate 1 made of, for example, ist by ion implantation.
After forming the buried layer 2, a mask material layer 3 of, for example, 5iOz is formed on the substrate 1 by thermal oxidation, and a groove etching window 4 necessary for the trench 1711 is formed by photolithography. Next, so-called anisotropic etching was performed using an alkaline etching solution containing KOH, as shown in Figure (b).
A separation groove 5 is formed in the substrate 1 as shown in FIG. Next, after removing the mask material layer 3, as shown in FIG. 3(e), the entire surface of the substrate 1 is coated with, for example, an 8102 film, a 5iaN4 film, a semi-insulating film, or a multilayer or composite film thereof (for example, an oxynitride film). An insulating film 6 such as the following is formed, and then polycrystalline silicon is deposited on this insulating film 6 to form a supporting substrate material T. Next, as shown in FIG. 1D, the back surface of the substrate 1 is removed by polishing or etching, and the insulating film 6 is exposed. As a result, islands 8 in which semiconductor regions that were part of the substrate 1 are surrounded by the insulating film 6 are isolated from each other and formed on the same substrate. Next, impurities are doped into this island 8 to form base, emitter, and collector contact compensation regions 9, 10, and 11, a surface protection insulating film 12, and contact windows as necessary. form.

FIG. 2 shows a cross-sectional structure of an integrated circuit device obtained by forming electrode wiring 13 after the above-described steps. Note that 14 is the contact window mentioned above. Here, resistance 15. Daigun Kado 2 Injista 16. Elements such as a transistor 17 and a diode 18 are formed respectively. Generally, a plurality of these elements are manufactured, and the high-power transistor 16, which serves as a main current path, is turned on and off to control voltage and current, amplify signals, and the like.

In a semiconductor device configured in this manner, each element is separated from each other by a dielectric material, so that it is possible to handle high voltage signals. However, since the electrode wiring 13, which is a signal transmission path, is formed on the same first main surface 19, the high power transistor 16 that turns on and off a large current has a large pattern width on the input side and output side. The electrode wiring 13 must be provided on the first main surface 19 side, which causes a reduction in the degree of integration.Furthermore, elements that handle high voltage usually generate a large amount of heat. However, since the high-power transistor 16, which generates the largest amount of heat, is entirely surrounded by the insulating film 6 with low thermal conductivity, the heat generated at each junction within the high-power transistor 16 is poorly dissipated, and the element There has been a problem in that the upper limit of the power that can be handled is restricted.

[Object and structure of the invention]

Therefore, the present invention has been made in view of the above-mentioned conventional problems, and its purpose is to provide a high-voltage semiconductor device that can handle high-power and high-voltage signals, and a method for manufacturing the same. There is a particular thing.

In order to achieve such an object, the present invention forms a plurality of islands insulated and separated through an insulating film in a support substrate, and semiconductor elements and semiconductor elements are respectively formed on the first main surface of the plurality of islands. In a semiconductor device in which electrode wiring is formed to electrically connect elements of the semiconductor device, an island having no insulating film on the bottom surface is formed on at least one of the islands, and an island is formed. Input/output signal electrodes to the semiconductor element are provided on the second main surface of the semiconductor element. This semiconductor device also includes a step of selectively forming a highly impurity region of the same conductivity type on the first main surface side of the semiconductor substrate, and a step of partially removing the first main surface side of the semiconductor substrate. a step of selectively leaving a part of the remaining area, and forming an insulating film on the other surface and other remaining area without forming an insulating film on at least a part of the surface in which at least one of the remaining areas faces the second main surface; forming a second
a process of depositing and forming a support substrate material from the main surface side of the semiconductor substrate, and removing the semiconductor substrate from the first main surface side until at least the insulating film is exposed to form an island in which the remaining regions are mutually insulated and isolated. a step of forming a semiconductor element in the island;
Forming electrode wiring for electrically connecting each semiconductor element on the first main surface of the island, and forming electrodes for inputting and outputting signals on the second main surface of the island without an insulating film. It is manufactured by a method that includes

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

3(a) to 3(,) are cross-sectional process diagrams of essential parts showing an example of the method for manufacturing a semiconductor device according to the present invention. The same parts as those in the above-mentioned figures have the same reference numerals. , the same figure (
As shown in a), As is deposited on the surface of the n-type substrate 10 made of St.
After forming a buried layer 2 with a sheet resistance of 50 QJ'g3 by ion implantation at a dose of lX10 Cya, a first mask material layer 3 and a second mask material layer 31 for processing the St substrate 1 are formed on the surface thereof. A groove etching window 4 necessary for separation is formed by photolithography. In this case, the first mask material layer 3 is made of S with a film thickness of 5000×, for example.
The second mask material layer 31 is a 5102 film with a thickness of 500X and a 5iaN4 film with a thickness of 1200X.
A composite mask material layer is formed with a film and a film thickness of 5oooXoc, v, p 5toz film e[tfm L Next, so-called anisotropic etching is performed using an alkaline etching solution consisting of a mixture of KOH aqueous solution and alcohol to form separation grooves 5 in the substrate 1, as shown in FIG. 1B. Next, the first mask material layer 3 is removed. At this time, the second
The C, V, and D SiO2 films of the mask material layer 31 are also removed. Next, thermal oxidation is performed in wet 02 gas at about 1100° C. for about 5 hours to form a S film with a thickness of 1°5 pm on the area excluding the second mask material layer 31, as shown in FIG.
An insulating film 6 made of an iOz film is formed.

In this case, a 5isN4 film is formed on the surface of the buried layer 2 covered with the second mask material layer 31 shown in FIG. 5102 film is not formed. Next, this substrate 1 is immersed in a hot phosphoric acid solution to form a second mask material layer 31.
The second 513N4 film was removed by etching, and then etching was performed in dilute hydrofluoric acid to form the second insulating film 6, which was made of a 5iOz film with a film thickness of 15 μnt, without thinning it.
The 5iOz film with a thickness of 50OA of the mask material layer 31 is removed. Here, according to the inventors' experiments, 4 wt% H
By etching with an F aqueous solution for about 8 minutes, the remaining 5io2 film of the second mask material layer 31 was removed and the buried layer 2 could be exposed. In this case, the thickness of the insulating film 6 is approximately 1°4.
It was μnt. Subsequently, Si is deposited on the insulating film 6 and the exposed buried layer 2 to a thickness of about 500 .mu.212 to form a supporting substrate material T. In this case, a single crystal layer 71 is formed on the buried layer 2 where the insulating film 6 is not formed, and a polycrystalline layer 72 is formed on the surface where the insulating film 6 is formed. This process requires extremely high temperatures and long periods of time, so
Although the impurities in the buried layer 2 will diffuse into the single crystal layer 71, it should be noted that this only enhances the effects of the present invention, as will be described later, and does not cause any inconvenience. It is. Further, since a part of the supporting substrate material T having a thickness of about 59 Qpm is used as a current path of the element as described later, adding impurities is an effective means for lowering the resistance value. Next, as shown in FIG. 2D, the back surface of the substrate 1 is removed by polishing or etching to expose the insulating film 6. As a result, the semiconductor region that was part of the substrate 1 is now surrounded by islands 8 and 8 surrounded by the insulating film 6.
' are formed, and these islands 8, 8' are isolated from each other. In this case, a collector compensation region 11' connected to the bottom of the insulating film 6 is formed in the region where the second mask material layer 31 described above is formed. Next, as shown in FIG. 8(e), impurities are doped into this island 8° 8' to form contact compensation regions 9 and 10 for the paste and emitter, respectively, and a surface protective film 12 is formed. In this case, the contact window 14 is opened as necessary.

FIG. 4 shows that after the above-described steps are performed, electrode wiring 13 is formed on the first main surface 19 and second main surface 20, and an electrode 13' is formed on the contact compensation region 11' of the collector. Resistance 15. High power transistor 16. Transistor 17. This figure shows the cross-sectional structure of an integrated circuit device in which a diode 18 and a diode 18 are respectively formed. In this case, a plurality of these elements are manufactured on the same substrate.

According to such a configuration, the high power transistor 16 is
Since it is possible to arrange the electrode 13', which is the input/output side of large current, on the second main surface 20 side different from the first main surface 19, the large power transistor 16 requires a large area. It becomes possible to halve the area occupied by the electrode wiring. Further, when the second main surface 20 is bonded to the so-called mounting package of the integrated circuit device, this part can be brought into contact with gold having good thermal conductivity, which greatly improves the heat dissipation effect. can be realized. Furthermore, in the conventional structure, the bottom surface of the high-power transistor 16 is covered with an insulating film 6 having low thermal conductivity, but in the structure of the embodiment described above, this insulating film 6 is not provided, and the bottom surface of the high-power transistor 16 is made of the same material as the substrate 1. Therefore, it is also possible to improve heat dissipation. By the way, the insulation film 6 is 5lo2. When the substrate 1 is made of Sl, the ratio of its thermal conductivity is Qst/Qsioz = (1,5W
/em-deg)/(0,014W/em-deg), and the effect is extremely large.

Note that the supporting substrate material T formed on the second main surface 20 side described above was made to have a thickness of about 500 Pm in the step 4 shown in FIG. Although it is ground to a thickness of about 50 μm just before being mounted on the support substrate material 1, there is no need to consider the reduction in the heat dissipation effect due to the thickness of the support substrate material 1. Also, as shown in FIG. 3(a)
Since the n+ buried N2 formed in the process of 1 causes a spread 9 of approximately several 1 Open due to the formation of the support substrate material 1 and the subsequent heat treatment, the collector compensation region 11' extends to the second main surface 20 (Illll). n buried N2, and there is no increase in the parasitic series resistance of the high power transistor 16.

However, in the above embodiment, the composite mask material layer 31 for processing the Si substrate 1 is a 5iOz film with a film thickness of about 50OA from the n+ buried layer 2 side on the Si substrate 1, and a Si film with a film thickness of 120OA.
3N4 film and 500OA film thickness C, V, D Sin
Although a case has been described in which a composite layer is formed by sequentially laminating films, the present invention is not particularly limited as long as the film is made of a material that can be selectively processed with other mask layers 3.

Further, in the above embodiment, the electrode 13' formed on the contact compensation region 11' of the collector is formed by depositing a metal layer, but it is also possible to use an Au-8i eutectic layer. Of course. In addition, since the main path for heat and signals is on the contact compensation region 11, this electrode 13'
1, and other areas may be reserved for mounting reasons.Also, in the above-mentioned embodiments, the case where the present invention is applied to a high-power, high-voltage transistor has been explained. It goes without saying that it can be applied to , PNPN elements, junction field effect transistors, electrostatic conduction transistors, etc. [Effects of the Invention] As explained above, according to the present invention, the area occupied by the element can be reduced by reducing the electrode wiring area. Improved heat dissipation makes it possible to increase the control current and voltage of the element, making it possible to create a high-surface single-voltage device that can handle high power and high voltage signals for this type of semiconductor device, and improve performance. can be significantly improved. In particular, it is possible to significantly improve the characteristics of this type of semiconductor device, which has traditionally had poor heat dissipation and the so-called thermal runaway of bipolar transistors, which limits the operating ambient temperature and controllable power and voltage.
1'Each streak can be heard with excellent results.

[Brief explanation of the drawing]

Figures 1 (a) to (e) and 2 are cross-sectional configuration diagrams of essential parts showing an example of a conventional method for manufacturing a semiconductor device, and Figure 3 (&)
〜(-3 and FIG. 4 are main part cross-sectional tR configuration diagrams showing an example of a method for manufacturing a semiconductor device according to the present invention. 1. Semiconductor substrate, 2. @e@buried layer, 3@- 1 fist mask material layer, 31 φ...composite mask material layer, 4...ya-
Etched window, 5... Separation groove, 6 Insulating film, 7
...Fist support substrate material, 11@Yaku・9 single crystal layer, 72@・
・Polycrystalline layer, 8゜13 '11 @・Raijima, 9・Φ・
Fist base contact supplementary area, 10-...Emitter net tR (P region, 11'φ...Collector supplementary 4)' region, 12...Surface protection insulating film, 13@...'...Electrode Wiring, 13'...electrode, 14--contact window, 15...resistor, 16-meiken/high power transistor, 17--3 transistor, 1BII...diode, 19... Φ・@1 principal surface, 20...#@2nd principal surface. Patent applicant: Masaki Yamakawa, agent of Nippon Telegraph and Telephone Public Corporation

Claims (2)

[Claims] (1) A plurality of first islands formed in a supporting substrate insulated and separated via an insulating film, and a second island on which an insulating film is not formed on the bottom surface of at least one of the plurality of first islands. , the above-mentioned No. 1. a semiconductor element formed in the second island;
．． an electrode wiring formed on the first main surface of the second island and electrically connecting the elements;
1. A semiconductor device comprising: an electrode formed on a main surface of the semiconductor element for inputting/outputting signals to/from the semiconductor element; (2) selectively forming a highly impurity region of the same conductivity type on the first main surface side of the semiconductor substrate;
selectively leaving a part of the semiconductor substrate by partially removing the main surface side of the semiconductor substrate, and forming an insulating film on at least a part of the surface where at least one of the remaining regions faces the second main surface. a step of forming an insulating film on the other surface and other remaining region without causing the insulating film to form, a step of depositing and forming a support substrate material from the second main surface side, and a step of forming at least the insulating film from the first main surface side. forming an island in which the remaining region is mutually insulated and isolated by removing the semiconductor substrate until a film is exposed; forming a semiconductor element in the island; and forming an island on a first main surface of the island. The method is characterized in that it includes at least the step of forming electrode wiring for electrically connecting each of the semiconductor elements, and forming electrodes for inputting and outputting signals on the second main surface of the island having no insulating film. A method for manufacturing a semiconductor device.